ti_adc.c revision 307775
1/*- 2 * Copyright 2014 Luiz Otavio O Souza <loos@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD: stable/11/sys/arm/ti/ti_adc.c 307775 2016-10-22 15:26:32Z gonzo $"); 29 30#include "opt_evdev.h" 31 32#include <sys/param.h> 33#include <sys/systm.h> 34#include <sys/bus.h> 35 36#include <sys/conf.h> 37#include <sys/kernel.h> 38#include <sys/limits.h> 39#include <sys/lock.h> 40#include <sys/module.h> 41#include <sys/mutex.h> 42#include <sys/condvar.h> 43#include <sys/resource.h> 44#include <sys/rman.h> 45#include <sys/sysctl.h> 46#include <sys/selinfo.h> 47#include <sys/poll.h> 48#include <sys/uio.h> 49 50#include <machine/bus.h> 51 52#include <dev/fdt/fdt_common.h> 53#include <dev/ofw/openfirm.h> 54#include <dev/ofw/ofw_bus.h> 55#include <dev/ofw/ofw_bus_subr.h> 56 57#ifdef EVDEV_SUPPORT 58#include <dev/evdev/input.h> 59#include <dev/evdev/evdev.h> 60#endif 61 62#include <arm/ti/ti_prcm.h> 63#include <arm/ti/ti_adcreg.h> 64#include <arm/ti/ti_adcvar.h> 65 66#undef DEBUG_TSC 67 68#define DEFAULT_CHARGE_DELAY 0x400 69#define STEPDLY_OPEN 0x98 70 71#define ORDER_XP 0 72#define ORDER_XN 1 73#define ORDER_YP 2 74#define ORDER_YN 3 75 76/* Define our 8 steps, one for each input channel. */ 77static struct ti_adc_input ti_adc_inputs[TI_ADC_NPINS] = { 78 { .stepconfig = ADC_STEPCFG(1), .stepdelay = ADC_STEPDLY(1) }, 79 { .stepconfig = ADC_STEPCFG(2), .stepdelay = ADC_STEPDLY(2) }, 80 { .stepconfig = ADC_STEPCFG(3), .stepdelay = ADC_STEPDLY(3) }, 81 { .stepconfig = ADC_STEPCFG(4), .stepdelay = ADC_STEPDLY(4) }, 82 { .stepconfig = ADC_STEPCFG(5), .stepdelay = ADC_STEPDLY(5) }, 83 { .stepconfig = ADC_STEPCFG(6), .stepdelay = ADC_STEPDLY(6) }, 84 { .stepconfig = ADC_STEPCFG(7), .stepdelay = ADC_STEPDLY(7) }, 85 { .stepconfig = ADC_STEPCFG(8), .stepdelay = ADC_STEPDLY(8) }, 86}; 87 88static int ti_adc_samples[5] = { 0, 2, 4, 8, 16 }; 89 90static int ti_adc_detach(device_t dev); 91 92#ifdef EVDEV_SUPPORT 93static void 94ti_adc_ev_report(struct ti_adc_softc *sc) 95{ 96 97 evdev_push_event(sc->sc_evdev, EV_ABS, ABS_X, sc->sc_x); 98 evdev_push_event(sc->sc_evdev, EV_ABS, ABS_Y, sc->sc_y); 99 evdev_push_event(sc->sc_evdev, EV_KEY, BTN_TOUCH, sc->sc_pen_down); 100 evdev_sync(sc->sc_evdev); 101} 102#endif /* EVDEV */ 103 104static void 105ti_adc_enable(struct ti_adc_softc *sc) 106{ 107 uint32_t reg; 108 109 TI_ADC_LOCK_ASSERT(sc); 110 111 if (sc->sc_last_state == 1) 112 return; 113 114 /* Enable the FIFO0 threshold and the end of sequence interrupt. */ 115 ADC_WRITE4(sc, ADC_IRQENABLE_SET, 116 ADC_IRQ_FIFO0_THRES | ADC_IRQ_FIFO1_THRES | ADC_IRQ_END_OF_SEQ); 117 118 reg = ADC_CTRL_STEP_WP | ADC_CTRL_STEP_ID; 119 if (sc->sc_tsc_wires > 0) { 120 reg |= ADC_CTRL_TSC_ENABLE; 121 switch (sc->sc_tsc_wires) { 122 case 4: 123 reg |= ADC_CTRL_TSC_4WIRE; 124 break; 125 case 5: 126 reg |= ADC_CTRL_TSC_5WIRE; 127 break; 128 case 8: 129 reg |= ADC_CTRL_TSC_8WIRE; 130 break; 131 default: 132 break; 133 } 134 } 135 reg |= ADC_CTRL_ENABLE; 136 /* Enable the ADC. Run thru enabled steps, start the conversions. */ 137 ADC_WRITE4(sc, ADC_CTRL, reg); 138 139 sc->sc_last_state = 1; 140} 141 142static void 143ti_adc_disable(struct ti_adc_softc *sc) 144{ 145 int count; 146 uint32_t data; 147 148 TI_ADC_LOCK_ASSERT(sc); 149 150 if (sc->sc_last_state == 0) 151 return; 152 153 /* Disable all the enabled steps. */ 154 ADC_WRITE4(sc, ADC_STEPENABLE, 0); 155 156 /* Disable the ADC. */ 157 ADC_WRITE4(sc, ADC_CTRL, ADC_READ4(sc, ADC_CTRL) & ~ADC_CTRL_ENABLE); 158 159 /* Disable the FIFO0 threshold and the end of sequence interrupt. */ 160 ADC_WRITE4(sc, ADC_IRQENABLE_CLR, 161 ADC_IRQ_FIFO0_THRES | ADC_IRQ_FIFO1_THRES | ADC_IRQ_END_OF_SEQ); 162 163 /* ACK any pending interrupt. */ 164 ADC_WRITE4(sc, ADC_IRQSTATUS, ADC_READ4(sc, ADC_IRQSTATUS)); 165 166 /* Drain the FIFO data. */ 167 count = ADC_READ4(sc, ADC_FIFO0COUNT) & ADC_FIFO_COUNT_MSK; 168 while (count > 0) { 169 data = ADC_READ4(sc, ADC_FIFO0DATA); 170 count = ADC_READ4(sc, ADC_FIFO0COUNT) & ADC_FIFO_COUNT_MSK; 171 } 172 173 count = ADC_READ4(sc, ADC_FIFO1COUNT) & ADC_FIFO_COUNT_MSK; 174 while (count > 0) { 175 data = ADC_READ4(sc, ADC_FIFO1DATA); 176 count = ADC_READ4(sc, ADC_FIFO1COUNT) & ADC_FIFO_COUNT_MSK; 177 } 178 179 sc->sc_last_state = 0; 180} 181 182static int 183ti_adc_setup(struct ti_adc_softc *sc) 184{ 185 int ain, i; 186 uint32_t enabled; 187 188 TI_ADC_LOCK_ASSERT(sc); 189 190 /* Check for enabled inputs. */ 191 enabled = sc->sc_tsc_enabled; 192 for (i = 0; i < sc->sc_adc_nchannels; i++) { 193 ain = sc->sc_adc_channels[i]; 194 if (ti_adc_inputs[ain].enable) 195 enabled |= (1U << (ain + 1)); 196 } 197 198 /* Set the ADC global status. */ 199 if (enabled != 0) { 200 ti_adc_enable(sc); 201 /* Update the enabled steps. */ 202 if (enabled != ADC_READ4(sc, ADC_STEPENABLE)) 203 ADC_WRITE4(sc, ADC_STEPENABLE, enabled); 204 } else 205 ti_adc_disable(sc); 206 207 return (0); 208} 209 210static void 211ti_adc_input_setup(struct ti_adc_softc *sc, int32_t ain) 212{ 213 struct ti_adc_input *input; 214 uint32_t reg, val; 215 216 TI_ADC_LOCK_ASSERT(sc); 217 218 input = &ti_adc_inputs[ain]; 219 reg = input->stepconfig; 220 val = ADC_READ4(sc, reg); 221 222 /* Set single ended operation. */ 223 val &= ~ADC_STEP_DIFF_CNTRL; 224 225 /* Set the negative voltage reference. */ 226 val &= ~ADC_STEP_RFM_MSK; 227 228 /* Set the positive voltage reference. */ 229 val &= ~ADC_STEP_RFP_MSK; 230 231 /* Set the samples average. */ 232 val &= ~ADC_STEP_AVG_MSK; 233 val |= input->samples << ADC_STEP_AVG_SHIFT; 234 235 /* Select the desired input. */ 236 val &= ~ADC_STEP_INP_MSK; 237 val |= ain << ADC_STEP_INP_SHIFT; 238 239 /* Set the ADC to one-shot mode. */ 240 val &= ~ADC_STEP_MODE_MSK; 241 242 ADC_WRITE4(sc, reg, val); 243} 244 245static void 246ti_adc_reset(struct ti_adc_softc *sc) 247{ 248 int ain, i; 249 250 TI_ADC_LOCK_ASSERT(sc); 251 252 /* Disable all the inputs. */ 253 for (i = 0; i < sc->sc_adc_nchannels; i++) { 254 ain = sc->sc_adc_channels[i]; 255 ti_adc_inputs[ain].enable = 0; 256 } 257} 258 259static int 260ti_adc_clockdiv_proc(SYSCTL_HANDLER_ARGS) 261{ 262 int error, reg; 263 struct ti_adc_softc *sc; 264 265 sc = (struct ti_adc_softc *)arg1; 266 267 TI_ADC_LOCK(sc); 268 reg = (int)ADC_READ4(sc, ADC_CLKDIV) + 1; 269 TI_ADC_UNLOCK(sc); 270 271 error = sysctl_handle_int(oidp, ®, sizeof(reg), req); 272 if (error != 0 || req->newptr == NULL) 273 return (error); 274 275 /* 276 * The actual written value is the prescaler setting - 1. 277 * Enforce a minimum value of 10 (i.e. 9) which limits the maximum 278 * ADC clock to ~2.4Mhz (CLK_M_OSC / 10). 279 */ 280 reg--; 281 if (reg < 9) 282 reg = 9; 283 if (reg > USHRT_MAX) 284 reg = USHRT_MAX; 285 286 TI_ADC_LOCK(sc); 287 /* Disable the ADC. */ 288 ti_adc_disable(sc); 289 /* Update the ADC prescaler setting. */ 290 ADC_WRITE4(sc, ADC_CLKDIV, reg); 291 /* Enable the ADC again. */ 292 ti_adc_setup(sc); 293 TI_ADC_UNLOCK(sc); 294 295 return (0); 296} 297 298static int 299ti_adc_enable_proc(SYSCTL_HANDLER_ARGS) 300{ 301 int error; 302 int32_t enable; 303 struct ti_adc_softc *sc; 304 struct ti_adc_input *input; 305 306 input = (struct ti_adc_input *)arg1; 307 sc = input->sc; 308 309 enable = input->enable; 310 error = sysctl_handle_int(oidp, &enable, sizeof(enable), 311 req); 312 if (error != 0 || req->newptr == NULL) 313 return (error); 314 315 if (enable) 316 enable = 1; 317 318 TI_ADC_LOCK(sc); 319 /* Setup the ADC as needed. */ 320 if (input->enable != enable) { 321 input->enable = enable; 322 ti_adc_setup(sc); 323 if (input->enable == 0) 324 input->value = 0; 325 } 326 TI_ADC_UNLOCK(sc); 327 328 return (0); 329} 330 331static int 332ti_adc_open_delay_proc(SYSCTL_HANDLER_ARGS) 333{ 334 int error, reg; 335 struct ti_adc_softc *sc; 336 struct ti_adc_input *input; 337 338 input = (struct ti_adc_input *)arg1; 339 sc = input->sc; 340 341 TI_ADC_LOCK(sc); 342 reg = (int)ADC_READ4(sc, input->stepdelay) & ADC_STEP_OPEN_DELAY; 343 TI_ADC_UNLOCK(sc); 344 345 error = sysctl_handle_int(oidp, ®, sizeof(reg), req); 346 if (error != 0 || req->newptr == NULL) 347 return (error); 348 349 if (reg < 0) 350 reg = 0; 351 352 TI_ADC_LOCK(sc); 353 ADC_WRITE4(sc, input->stepdelay, reg & ADC_STEP_OPEN_DELAY); 354 TI_ADC_UNLOCK(sc); 355 356 return (0); 357} 358 359static int 360ti_adc_samples_avg_proc(SYSCTL_HANDLER_ARGS) 361{ 362 int error, samples, i; 363 struct ti_adc_softc *sc; 364 struct ti_adc_input *input; 365 366 input = (struct ti_adc_input *)arg1; 367 sc = input->sc; 368 369 if (input->samples > nitems(ti_adc_samples)) 370 input->samples = nitems(ti_adc_samples); 371 samples = ti_adc_samples[input->samples]; 372 373 error = sysctl_handle_int(oidp, &samples, 0, req); 374 if (error != 0 || req->newptr == NULL) 375 return (error); 376 377 TI_ADC_LOCK(sc); 378 if (samples != ti_adc_samples[input->samples]) { 379 input->samples = 0; 380 for (i = 0; i < nitems(ti_adc_samples); i++) 381 if (samples >= ti_adc_samples[i]) 382 input->samples = i; 383 ti_adc_input_setup(sc, input->input); 384 } 385 TI_ADC_UNLOCK(sc); 386 387 return (error); 388} 389 390static void 391ti_adc_read_data(struct ti_adc_softc *sc) 392{ 393 int count, ain; 394 struct ti_adc_input *input; 395 uint32_t data; 396 397 TI_ADC_LOCK_ASSERT(sc); 398 399 /* Read the available data. */ 400 count = ADC_READ4(sc, ADC_FIFO0COUNT) & ADC_FIFO_COUNT_MSK; 401 while (count > 0) { 402 data = ADC_READ4(sc, ADC_FIFO0DATA); 403 ain = (data & ADC_FIFO_STEP_ID_MSK) >> ADC_FIFO_STEP_ID_SHIFT; 404 input = &ti_adc_inputs[ain]; 405 if (input->enable == 0) 406 input->value = 0; 407 else 408 input->value = (int32_t)(data & ADC_FIFO_DATA_MSK); 409 count = ADC_READ4(sc, ADC_FIFO0COUNT) & ADC_FIFO_COUNT_MSK; 410 } 411} 412 413static int 414cmp_values(const void *a, const void *b) 415{ 416 const uint32_t *v1, *v2; 417 v1 = a; 418 v2 = b; 419 if (*v1 < *v2) 420 return -1; 421 if (*v1 > *v2) 422 return 1; 423 424 return (0); 425} 426 427static void 428ti_adc_tsc_read_data(struct ti_adc_softc *sc) 429{ 430 int count; 431 uint32_t data[16]; 432 uint32_t x, y; 433 int i, start, end; 434 435 TI_ADC_LOCK_ASSERT(sc); 436 437 /* Read the available data. */ 438 count = ADC_READ4(sc, ADC_FIFO1COUNT) & ADC_FIFO_COUNT_MSK; 439 if (count == 0) 440 return; 441 442 i = 0; 443 while (count > 0) { 444 data[i++] = ADC_READ4(sc, ADC_FIFO1DATA) & ADC_FIFO_DATA_MSK; 445 count = ADC_READ4(sc, ADC_FIFO1COUNT) & ADC_FIFO_COUNT_MSK; 446 } 447 448 if (sc->sc_coord_readouts > 3) { 449 start = 1; 450 end = sc->sc_coord_readouts - 1; 451 qsort(data, sc->sc_coord_readouts, 452 sizeof(data[0]), &cmp_values); 453 qsort(&data[sc->sc_coord_readouts + 2], 454 sc->sc_coord_readouts, 455 sizeof(data[0]), &cmp_values); 456 } 457 else { 458 start = 0; 459 end = sc->sc_coord_readouts; 460 } 461 462 x = y = 0; 463 for (i = start; i < end; i++) 464 y += data[i]; 465 y /= (end - start); 466 467 for (i = sc->sc_coord_readouts + 2 + start; i < sc->sc_coord_readouts + 2 + end; i++) 468 x += data[i]; 469 x /= (end - start); 470 471#ifdef DEBUG_TSC 472 device_printf(sc->sc_dev, "touchscreen x: %d, y: %d\n", x, y); 473#endif 474 475#ifdef EVDEV_SUPPORT 476 if ((sc->sc_x != x) || (sc->sc_y != y)) { 477 sc->sc_x = x; 478 sc->sc_y = y; 479 ti_adc_ev_report(sc); 480 } 481#endif 482} 483 484static void 485ti_adc_intr_locked(struct ti_adc_softc *sc, uint32_t status) 486{ 487 /* Read the available data. */ 488 if (status & ADC_IRQ_FIFO0_THRES) 489 ti_adc_read_data(sc); 490} 491 492static void 493ti_adc_tsc_intr_locked(struct ti_adc_softc *sc, uint32_t status) 494{ 495 /* Read the available data. */ 496 if (status & ADC_IRQ_FIFO1_THRES) 497 ti_adc_tsc_read_data(sc); 498 499} 500 501static void 502ti_adc_intr(void *arg) 503{ 504 struct ti_adc_softc *sc; 505 uint32_t status, rawstatus; 506 507 sc = (struct ti_adc_softc *)arg; 508 509 TI_ADC_LOCK(sc); 510 511 rawstatus = ADC_READ4(sc, ADC_IRQSTATUS_RAW); 512 status = ADC_READ4(sc, ADC_IRQSTATUS); 513 514 if (rawstatus & ADC_IRQ_HW_PEN_ASYNC) { 515 sc->sc_pen_down = 1; 516 status |= ADC_IRQ_HW_PEN_ASYNC; 517 ADC_WRITE4(sc, ADC_IRQENABLE_CLR, 518 ADC_IRQ_HW_PEN_ASYNC); 519#ifdef EVDEV_SUPPORT 520 ti_adc_ev_report(sc); 521#endif 522 } 523 524 if (rawstatus & ADC_IRQ_PEN_UP) { 525 sc->sc_pen_down = 0; 526 status |= ADC_IRQ_PEN_UP; 527#ifdef EVDEV_SUPPORT 528 ti_adc_ev_report(sc); 529#endif 530 } 531 532 if (status & ADC_IRQ_FIFO0_THRES) 533 ti_adc_intr_locked(sc, status); 534 535 if (status & ADC_IRQ_FIFO1_THRES) 536 ti_adc_tsc_intr_locked(sc, status); 537 538 if (status) { 539 /* ACK the interrupt. */ 540 ADC_WRITE4(sc, ADC_IRQSTATUS, status); 541 } 542 543 /* Start the next conversion ? */ 544 if (status & ADC_IRQ_END_OF_SEQ) 545 ti_adc_setup(sc); 546 547 TI_ADC_UNLOCK(sc); 548} 549 550static void 551ti_adc_sysctl_init(struct ti_adc_softc *sc) 552{ 553 char pinbuf[3]; 554 struct sysctl_ctx_list *ctx; 555 struct sysctl_oid *tree_node, *inp_node, *inpN_node; 556 struct sysctl_oid_list *tree, *inp_tree, *inpN_tree; 557 int ain, i; 558 559 /* 560 * Add per-pin sysctl tree/handlers. 561 */ 562 ctx = device_get_sysctl_ctx(sc->sc_dev); 563 tree_node = device_get_sysctl_tree(sc->sc_dev); 564 tree = SYSCTL_CHILDREN(tree_node); 565 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "clockdiv", 566 CTLFLAG_RW | CTLTYPE_UINT, sc, 0, 567 ti_adc_clockdiv_proc, "IU", "ADC clock prescaler"); 568 inp_node = SYSCTL_ADD_NODE(ctx, tree, OID_AUTO, "ain", 569 CTLFLAG_RD, NULL, "ADC inputs"); 570 inp_tree = SYSCTL_CHILDREN(inp_node); 571 572 for (i = 0; i < sc->sc_adc_nchannels; i++) { 573 ain = sc->sc_adc_channels[i]; 574 575 snprintf(pinbuf, sizeof(pinbuf), "%d", ain); 576 inpN_node = SYSCTL_ADD_NODE(ctx, inp_tree, OID_AUTO, pinbuf, 577 CTLFLAG_RD, NULL, "ADC input"); 578 inpN_tree = SYSCTL_CHILDREN(inpN_node); 579 580 SYSCTL_ADD_PROC(ctx, inpN_tree, OID_AUTO, "enable", 581 CTLFLAG_RW | CTLTYPE_UINT, &ti_adc_inputs[ain], 0, 582 ti_adc_enable_proc, "IU", "Enable ADC input"); 583 SYSCTL_ADD_PROC(ctx, inpN_tree, OID_AUTO, "open_delay", 584 CTLFLAG_RW | CTLTYPE_UINT, &ti_adc_inputs[ain], 0, 585 ti_adc_open_delay_proc, "IU", "ADC open delay"); 586 SYSCTL_ADD_PROC(ctx, inpN_tree, OID_AUTO, "samples_avg", 587 CTLFLAG_RW | CTLTYPE_UINT, &ti_adc_inputs[ain], 0, 588 ti_adc_samples_avg_proc, "IU", "ADC samples average"); 589 SYSCTL_ADD_INT(ctx, inpN_tree, OID_AUTO, "input", 590 CTLFLAG_RD, &ti_adc_inputs[ain].value, 0, 591 "Converted raw value for the ADC input"); 592 } 593} 594 595static void 596ti_adc_inputs_init(struct ti_adc_softc *sc) 597{ 598 int ain, i; 599 struct ti_adc_input *input; 600 601 TI_ADC_LOCK(sc); 602 for (i = 0; i < sc->sc_adc_nchannels; i++) { 603 ain = sc->sc_adc_channels[i]; 604 input = &ti_adc_inputs[ain]; 605 input->sc = sc; 606 input->input = ain; 607 input->value = 0; 608 input->enable = 0; 609 input->samples = 0; 610 ti_adc_input_setup(sc, ain); 611 } 612 TI_ADC_UNLOCK(sc); 613} 614 615static void 616ti_adc_tsc_init(struct ti_adc_softc *sc) 617{ 618 int i, start_step, end_step; 619 uint32_t stepconfig, val; 620 621 TI_ADC_LOCK(sc); 622 623 /* X coordinates */ 624 stepconfig = ADC_STEP_FIFO1 | (4 << ADC_STEP_AVG_SHIFT) | 625 ADC_STEP_MODE_HW_ONESHOT | sc->sc_xp_bit; 626 if (sc->sc_tsc_wires == 4) 627 stepconfig |= ADC_STEP_INP(sc->sc_yp_inp) | sc->sc_xn_bit; 628 else if (sc->sc_tsc_wires == 5) 629 stepconfig |= ADC_STEP_INP(4) | 630 sc->sc_xn_bit | sc->sc_yn_bit | sc->sc_yp_bit; 631 else if (sc->sc_tsc_wires == 8) 632 stepconfig |= ADC_STEP_INP(sc->sc_yp_inp) | sc->sc_xn_bit; 633 634 start_step = ADC_STEPS - sc->sc_coord_readouts + 1; 635 end_step = start_step + sc->sc_coord_readouts - 1; 636 for (i = start_step; i <= end_step; i++) { 637 ADC_WRITE4(sc, ADC_STEPCFG(i), stepconfig); 638 ADC_WRITE4(sc, ADC_STEPDLY(i), STEPDLY_OPEN); 639 } 640 641 /* Y coordinates */ 642 stepconfig = ADC_STEP_FIFO1 | (4 << ADC_STEP_AVG_SHIFT) | 643 ADC_STEP_MODE_HW_ONESHOT | sc->sc_yn_bit | 644 ADC_STEP_INM(8); 645 if (sc->sc_tsc_wires == 4) 646 stepconfig |= ADC_STEP_INP(sc->sc_xp_inp) | sc->sc_yp_bit; 647 else if (sc->sc_tsc_wires == 5) 648 stepconfig |= ADC_STEP_INP(4) | 649 sc->sc_xp_bit | sc->sc_xn_bit | sc->sc_yp_bit; 650 else if (sc->sc_tsc_wires == 8) 651 stepconfig |= ADC_STEP_INP(sc->sc_xp_inp) | sc->sc_yp_bit; 652 653 start_step = ADC_STEPS - (sc->sc_coord_readouts*2 + 2) + 1; 654 end_step = start_step + sc->sc_coord_readouts - 1; 655 for (i = start_step; i <= end_step; i++) { 656 ADC_WRITE4(sc, ADC_STEPCFG(i), stepconfig); 657 ADC_WRITE4(sc, ADC_STEPDLY(i), STEPDLY_OPEN); 658 } 659 660 /* Charge config */ 661 val = ADC_READ4(sc, ADC_IDLECONFIG); 662 ADC_WRITE4(sc, ADC_TC_CHARGE_STEPCONFIG, val); 663 ADC_WRITE4(sc, ADC_TC_CHARGE_DELAY, sc->sc_charge_delay); 664 665 /* 2 steps for Z */ 666 start_step = ADC_STEPS - (sc->sc_coord_readouts + 2) + 1; 667 stepconfig = ADC_STEP_FIFO1 | (4 << ADC_STEP_AVG_SHIFT) | 668 ADC_STEP_MODE_HW_ONESHOT | sc->sc_yp_bit | 669 sc->sc_xn_bit | ADC_STEP_INP(sc->sc_xp_inp) | 670 ADC_STEP_INM(8); 671 ADC_WRITE4(sc, ADC_STEPCFG(start_step), stepconfig); 672 ADC_WRITE4(sc, ADC_STEPDLY(start_step), STEPDLY_OPEN); 673 start_step++; 674 stepconfig |= ADC_STEP_INP(sc->sc_yn_inp); 675 ADC_WRITE4(sc, ADC_STEPCFG(start_step), stepconfig); 676 ADC_WRITE4(sc, ADC_STEPDLY(start_step), STEPDLY_OPEN); 677 678 ADC_WRITE4(sc, ADC_FIFO1THRESHOLD, (sc->sc_coord_readouts*2 + 2) - 1); 679 680 sc->sc_tsc_enabled = 1; 681 start_step = ADC_STEPS - (sc->sc_coord_readouts*2 + 2) + 1; 682 end_step = ADC_STEPS; 683 for (i = start_step; i <= end_step; i++) { 684 sc->sc_tsc_enabled |= (1 << i); 685 } 686 687 688 TI_ADC_UNLOCK(sc); 689} 690 691static void 692ti_adc_idlestep_init(struct ti_adc_softc *sc) 693{ 694 uint32_t val; 695 696 val = ADC_STEP_YNN_SW | ADC_STEP_INM(8) | ADC_STEP_INP(8) | ADC_STEP_YPN_SW; 697 698 ADC_WRITE4(sc, ADC_IDLECONFIG, val); 699} 700 701static int 702ti_adc_config_wires(struct ti_adc_softc *sc, int *wire_configs, int nwire_configs) 703{ 704 int i; 705 int wire, ai; 706 707 for (i = 0; i < nwire_configs; i++) { 708 wire = wire_configs[i] & 0xf; 709 ai = (wire_configs[i] >> 4) & 0xf; 710 switch (wire) { 711 case ORDER_XP: 712 sc->sc_xp_bit = ADC_STEP_XPP_SW; 713 sc->sc_xp_inp = ai; 714 break; 715 case ORDER_XN: 716 sc->sc_xn_bit = ADC_STEP_XNN_SW; 717 sc->sc_xn_inp = ai; 718 break; 719 case ORDER_YP: 720 sc->sc_yp_bit = ADC_STEP_YPP_SW; 721 sc->sc_yp_inp = ai; 722 break; 723 case ORDER_YN: 724 sc->sc_yn_bit = ADC_STEP_YNN_SW; 725 sc->sc_yn_inp = ai; 726 break; 727 default: 728 device_printf(sc->sc_dev, "Invalid wire config\n"); 729 return (-1); 730 } 731 } 732 return (0); 733} 734 735static int 736ti_adc_probe(device_t dev) 737{ 738 739 if (!ofw_bus_is_compatible(dev, "ti,am3359-tscadc")) 740 return (ENXIO); 741 device_set_desc(dev, "TI ADC controller"); 742 743 return (BUS_PROBE_DEFAULT); 744} 745 746static int 747ti_adc_attach(device_t dev) 748{ 749 int err, rid, i; 750 struct ti_adc_softc *sc; 751 uint32_t rev, reg; 752 phandle_t node, child; 753 pcell_t cell; 754 int *channels; 755 int nwire_configs; 756 int *wire_configs; 757 758 sc = device_get_softc(dev); 759 sc->sc_dev = dev; 760 761 node = ofw_bus_get_node(dev); 762 763 sc->sc_tsc_wires = 0; 764 sc->sc_coord_readouts = 1; 765 sc->sc_x_plate_resistance = 0; 766 sc->sc_charge_delay = DEFAULT_CHARGE_DELAY; 767 /* Read "tsc" node properties */ 768 child = ofw_bus_find_child(node, "tsc"); 769 if (child != 0 && OF_hasprop(child, "ti,wires")) { 770 if ((OF_getprop(child, "ti,wires", &cell, sizeof(cell))) > 0) 771 sc->sc_tsc_wires = fdt32_to_cpu(cell); 772 if ((OF_getprop(child, "ti,coordinate-readouts", &cell, sizeof(cell))) > 0) 773 sc->sc_coord_readouts = fdt32_to_cpu(cell); 774 if ((OF_getprop(child, "ti,x-plate-resistance", &cell, sizeof(cell))) > 0) 775 sc->sc_x_plate_resistance = fdt32_to_cpu(cell); 776 if ((OF_getprop(child, "ti,charge-delay", &cell, sizeof(cell))) > 0) 777 sc->sc_charge_delay = fdt32_to_cpu(cell); 778 nwire_configs = OF_getencprop_alloc(child, "ti,wire-config", 779 sizeof(*wire_configs), (void **)&wire_configs); 780 if (nwire_configs != sc->sc_tsc_wires) { 781 device_printf(sc->sc_dev, 782 "invalid number of ti,wire-config: %d (should be %d)\n", 783 nwire_configs, sc->sc_tsc_wires); 784 OF_prop_free(wire_configs); 785 return (EINVAL); 786 } 787 err = ti_adc_config_wires(sc, wire_configs, nwire_configs); 788 OF_prop_free(wire_configs); 789 if (err) 790 return (EINVAL); 791 } 792 793 /* Read "adc" node properties */ 794 child = ofw_bus_find_child(node, "adc"); 795 if (child != 0) { 796 sc->sc_adc_nchannels = OF_getencprop_alloc(child, "ti,adc-channels", 797 sizeof(*channels), (void **)&channels); 798 if (sc->sc_adc_nchannels > 0) { 799 for (i = 0; i < sc->sc_adc_nchannels; i++) 800 sc->sc_adc_channels[i] = channels[i]; 801 OF_prop_free(channels); 802 } 803 } 804 805 /* Sanity check FDT data */ 806 if (sc->sc_tsc_wires + sc->sc_adc_nchannels > TI_ADC_NPINS) { 807 device_printf(dev, "total number of chanels (%d) is larger than %d\n", 808 sc->sc_tsc_wires + sc->sc_adc_nchannels, TI_ADC_NPINS); 809 return (ENXIO); 810 } 811 812 rid = 0; 813 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 814 RF_ACTIVE); 815 if (!sc->sc_mem_res) { 816 device_printf(dev, "cannot allocate memory window\n"); 817 return (ENXIO); 818 } 819 820 /* Activate the ADC_TSC module. */ 821 err = ti_prcm_clk_enable(TSC_ADC_CLK); 822 if (err) 823 return (err); 824 825 rid = 0; 826 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 827 RF_ACTIVE); 828 if (!sc->sc_irq_res) { 829 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 830 device_printf(dev, "cannot allocate interrupt\n"); 831 return (ENXIO); 832 } 833 834 if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 835 NULL, ti_adc_intr, sc, &sc->sc_intrhand) != 0) { 836 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); 837 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 838 device_printf(dev, "Unable to setup the irq handler.\n"); 839 return (ENXIO); 840 } 841 842 /* Check the ADC revision. */ 843 rev = ADC_READ4(sc, ADC_REVISION); 844 device_printf(dev, 845 "scheme: %#x func: %#x rtl: %d rev: %d.%d custom rev: %d\n", 846 (rev & ADC_REV_SCHEME_MSK) >> ADC_REV_SCHEME_SHIFT, 847 (rev & ADC_REV_FUNC_MSK) >> ADC_REV_FUNC_SHIFT, 848 (rev & ADC_REV_RTL_MSK) >> ADC_REV_RTL_SHIFT, 849 (rev & ADC_REV_MAJOR_MSK) >> ADC_REV_MAJOR_SHIFT, 850 rev & ADC_REV_MINOR_MSK, 851 (rev & ADC_REV_CUSTOM_MSK) >> ADC_REV_CUSTOM_SHIFT); 852 853 reg = ADC_READ4(sc, ADC_CTRL); 854 ADC_WRITE4(sc, ADC_CTRL, reg | ADC_CTRL_STEP_WP | ADC_CTRL_STEP_ID); 855 856 /* 857 * Set the ADC prescaler to 2400 if touchscreen is not enabled 858 * and to 24 if it is. This sets the ADC clock to ~10Khz and 859 * ~1Mhz respectively (CLK_M_OSC / prescaler). 860 */ 861 if (sc->sc_tsc_wires) 862 ADC_WRITE4(sc, ADC_CLKDIV, 24 - 1); 863 else 864 ADC_WRITE4(sc, ADC_CLKDIV, 2400 - 1); 865 866 TI_ADC_LOCK_INIT(sc); 867 868 ti_adc_idlestep_init(sc); 869 ti_adc_inputs_init(sc); 870 ti_adc_sysctl_init(sc); 871 ti_adc_tsc_init(sc); 872 873 TI_ADC_LOCK(sc); 874 ti_adc_setup(sc); 875 TI_ADC_UNLOCK(sc); 876 877#ifdef EVDEV_SUPPORT 878 if (sc->sc_tsc_wires > 0) { 879 sc->sc_evdev = evdev_alloc(); 880 evdev_set_name(sc->sc_evdev, device_get_desc(dev)); 881 evdev_set_phys(sc->sc_evdev, device_get_nameunit(dev)); 882 evdev_set_id(sc->sc_evdev, BUS_VIRTUAL, 0, 0, 0); 883 evdev_support_prop(sc->sc_evdev, INPUT_PROP_DIRECT); 884 evdev_support_event(sc->sc_evdev, EV_SYN); 885 evdev_support_event(sc->sc_evdev, EV_ABS); 886 evdev_support_event(sc->sc_evdev, EV_KEY); 887 888 evdev_support_abs(sc->sc_evdev, ABS_X, 0, 0, 889 ADC_MAX_VALUE, 0, 0, 0); 890 evdev_support_abs(sc->sc_evdev, ABS_Y, 0, 0, 891 ADC_MAX_VALUE, 0, 0, 0); 892 893 evdev_support_key(sc->sc_evdev, BTN_TOUCH); 894 895 err = evdev_register(sc->sc_evdev); 896 if (err) { 897 device_printf(dev, 898 "failed to register evdev: error=%d\n", err); 899 ti_adc_detach(dev); 900 return (err); 901 } 902 903 sc->sc_pen_down = 0; 904 sc->sc_x = -1; 905 sc->sc_y = -1; 906 } 907#endif /* EVDEV */ 908 909 return (0); 910} 911 912static int 913ti_adc_detach(device_t dev) 914{ 915 struct ti_adc_softc *sc; 916 917 sc = device_get_softc(dev); 918 919 /* Turn off the ADC. */ 920 TI_ADC_LOCK(sc); 921 ti_adc_reset(sc); 922 ti_adc_setup(sc); 923 924#ifdef EVDEV_SUPPORT 925 evdev_free(sc->sc_evdev); 926#endif 927 928 TI_ADC_UNLOCK(sc); 929 930 TI_ADC_LOCK_DESTROY(sc); 931 932 if (sc->sc_intrhand) 933 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intrhand); 934 if (sc->sc_irq_res) 935 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); 936 if (sc->sc_mem_res) 937 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 938 939 return (bus_generic_detach(dev)); 940} 941 942static device_method_t ti_adc_methods[] = { 943 DEVMETHOD(device_probe, ti_adc_probe), 944 DEVMETHOD(device_attach, ti_adc_attach), 945 DEVMETHOD(device_detach, ti_adc_detach), 946 947 DEVMETHOD_END 948}; 949 950static driver_t ti_adc_driver = { 951 "ti_adc", 952 ti_adc_methods, 953 sizeof(struct ti_adc_softc), 954}; 955 956static devclass_t ti_adc_devclass; 957 958DRIVER_MODULE(ti_adc, simplebus, ti_adc_driver, ti_adc_devclass, 0, 0); 959MODULE_VERSION(ti_adc, 1); 960MODULE_DEPEND(ti_adc, simplebus, 1, 1, 1); 961#ifdef EVDEV_SUPPORT 962MODULE_DEPEND(ti_adc, evdev, 1, 1, 1); 963#endif 964