if_cpswvar.h revision 330897 
1/*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2012 Damjan Marion <dmarion@Freebsd.org>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 *
28 * $FreeBSD: stable/11/sys/arm/ti/cpsw/if_cpswvar.h 330897 2018-03-14 03:19:51Z eadler $
29 */
30
31#ifndef	_IF_CPSWVAR_H
32#define	_IF_CPSWVAR_H
33
34#define	CPSW_PORTS		2
35#define	CPSW_INTR_COUNT		4
36
37/* MII BUS  */
38#define	CPSW_MIIBUS_RETRIES	20
39#define	CPSW_MIIBUS_DELAY	100
40
41#define	CPSW_MAX_ALE_ENTRIES	1024
42
43#define	CPSW_SYSCTL_COUNT	34
44
45#ifdef CPSW_ETHERSWITCH
46#define	CPSW_CPU_PORT		0
47#define	CPSW_PORTS_MASK		0x7
48#define	CPSW_VLANS		128	/* Arbitrary number. */
49
50struct cpsw_vlangroups {
51	int vid;
52};
53#endif
54
55struct cpsw_slot {
56	uint32_t bd_offset;  /* Offset of corresponding BD within CPPI RAM. */
57	bus_dmamap_t dmamap;
58	struct ifnet *ifp;
59	struct mbuf *mbuf;
60	STAILQ_ENTRY(cpsw_slot) next;
61};
62STAILQ_HEAD(cpsw_slots, cpsw_slot);
63
64struct cpsw_queue {
65	struct mtx	lock;
66	int		running;
67	int		teardown;
68	struct cpsw_slots active;
69	struct cpsw_slots avail;
70	uint32_t	queue_adds; /* total bufs added */
71	uint32_t	queue_removes; /* total bufs removed */
72	uint32_t	queue_removes_at_last_tick; /* Used by watchdog */
73	uint32_t	queue_restart;
74	int		queue_slots;
75	int		active_queue_len;
76	int		max_active_queue_len;
77	int		avail_queue_len;
78	int		max_avail_queue_len;
79	int		longest_chain; /* Largest # segments in a single packet. */
80	int		hdp_offset;
81};
82
83struct cpsw_port {
84	device_t	dev;
85	int		phy;
86	int		vlan;
87};
88
89struct cpsw_softc {
90	device_t	dev;
91	int		active_slave;
92	int		debug;
93	int		dualemac;
94	phandle_t	node;
95	struct bintime	attach_uptime; /* system uptime when attach happened. */
96	struct cpsw_port port[2];
97	unsigned	coal_us;
98
99	/* RX and TX buffer tracking */
100	struct cpsw_queue rx, tx;
101
102	/* We expect 1 memory resource and 4 interrupts from the device tree. */
103	int		mem_rid;
104	struct resource	*mem_res;
105	struct resource	*irq_res[CPSW_INTR_COUNT];
106	void		*ih_cookie[CPSW_INTR_COUNT];
107
108	/* A buffer full of nulls for TX padding. */
109	void		*nullpad;
110
111	bus_dma_tag_t	mbuf_dtag;
112
113	struct {
114		int resets;
115		int timer;
116		struct callout  callout;
117	} watchdog;
118
119	/* 64-bit versions of 32-bit hardware statistics counters */
120	uint64_t shadow_stats[CPSW_SYSCTL_COUNT];
121
122	/* CPPI STATERAM has 512 slots for building TX/RX queues. */
123	/* TODO: Size here supposedly varies with different versions
124	   of the controller.  Check DaVinci specs and find a good
125	   way to adjust this.  One option is to have a separate
126	   Device Tree parameter for number slots; another option
127	   is to calculate it from the memory size in the device tree. */
128	struct cpsw_slot _slots[CPSW_CPPI_RAM_SIZE / sizeof(struct cpsw_cpdma_bd)];
129	struct cpsw_slots avail;
130};
131
132struct cpswp_softc {
133	device_t	dev;
134	device_t	miibus;
135	device_t	pdev;
136	int		media_status;
137	int		unit;
138	int		vlan;
139	struct bintime	init_uptime; /* system uptime when init happened. */
140	struct callout	mii_callout;
141	struct cpsw_softc *swsc;
142	struct ifnet	*ifp;
143	struct mii_data	*mii;
144	struct mtx	lock;
145	uint32_t	if_flags;
146	uint32_t	phy;
147	uint32_t	phyaccess;
148	uint32_t	physel;
149};
150
151#endif /*_IF_CPSWVAR_H */
152