if_cpsw.c revision 312757
1/*- 2 * Copyright (c) 2012 Damjan Marion <dmarion@Freebsd.org> 3 * Copyright (c) 2016 Rubicon Communications, LLC (Netgate) 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28/* 29 * TI Common Platform Ethernet Switch (CPSW) Driver 30 * Found in TI8148 "DaVinci" and AM335x "Sitara" SoCs. 31 * 32 * This controller is documented in the AM335x Technical Reference 33 * Manual, in the TMS320DM814x DaVinci Digital Video Processors TRM 34 * and in the TMS320C6452 3 Port Switch Ethernet Subsystem TRM. 35 * 36 * It is basically a single Ethernet port (port 0) wired internally to 37 * a 3-port store-and-forward switch connected to two independent 38 * "sliver" controllers (port 1 and port 2). You can operate the 39 * controller in a variety of different ways by suitably configuring 40 * the slivers and the Address Lookup Engine (ALE) that routes packets 41 * between the ports. 42 * 43 * This code was developed and tested on a BeagleBone with 44 * an AM335x SoC. 45 */ 46 47#include <sys/cdefs.h> 48__FBSDID("$FreeBSD: stable/11/sys/arm/ti/cpsw/if_cpsw.c 312757 2017-01-25 15:27:05Z loos $"); 49 50#include "opt_cpsw.h" 51 52#include <sys/param.h> 53#include <sys/bus.h> 54#include <sys/kernel.h> 55#include <sys/lock.h> 56#include <sys/mbuf.h> 57#include <sys/module.h> 58#include <sys/mutex.h> 59#include <sys/rman.h> 60#include <sys/socket.h> 61#include <sys/sockio.h> 62#include <sys/sysctl.h> 63 64#include <machine/bus.h> 65#include <machine/resource.h> 66#include <machine/stdarg.h> 67 68#include <net/ethernet.h> 69#include <net/bpf.h> 70#include <net/if.h> 71#include <net/if_dl.h> 72#include <net/if_media.h> 73#include <net/if_types.h> 74 75#include <arm/ti/ti_scm.h> 76#include <arm/ti/am335x/am335x_scm.h> 77 78#include <dev/mii/mii.h> 79#include <dev/mii/miivar.h> 80 81#include <dev/fdt/fdt_common.h> 82#include <dev/ofw/ofw_bus.h> 83#include <dev/ofw/ofw_bus_subr.h> 84 85#ifdef CPSW_ETHERSWITCH 86#include <dev/etherswitch/etherswitch.h> 87#include "etherswitch_if.h" 88#endif 89 90#include "if_cpswreg.h" 91#include "if_cpswvar.h" 92 93#include "miibus_if.h" 94 95/* Device probe/attach/detach. */ 96static int cpsw_probe(device_t); 97static int cpsw_attach(device_t); 98static int cpsw_detach(device_t); 99static int cpswp_probe(device_t); 100static int cpswp_attach(device_t); 101static int cpswp_detach(device_t); 102 103static phandle_t cpsw_get_node(device_t, device_t); 104 105/* Device Init/shutdown. */ 106static int cpsw_shutdown(device_t); 107static void cpswp_init(void *); 108static void cpswp_init_locked(void *); 109static void cpswp_stop_locked(struct cpswp_softc *); 110 111/* Device Suspend/Resume. */ 112static int cpsw_suspend(device_t); 113static int cpsw_resume(device_t); 114 115/* Ioctl. */ 116static int cpswp_ioctl(struct ifnet *, u_long command, caddr_t data); 117 118static int cpswp_miibus_readreg(device_t, int phy, int reg); 119static int cpswp_miibus_writereg(device_t, int phy, int reg, int value); 120static void cpswp_miibus_statchg(device_t); 121 122/* Send/Receive packets. */ 123static void cpsw_intr_rx(void *arg); 124static struct mbuf *cpsw_rx_dequeue(struct cpsw_softc *); 125static void cpsw_rx_enqueue(struct cpsw_softc *); 126static void cpswp_start(struct ifnet *); 127static void cpsw_intr_tx(void *); 128static void cpswp_tx_enqueue(struct cpswp_softc *); 129static int cpsw_tx_dequeue(struct cpsw_softc *); 130 131/* Misc interrupts and watchdog. */ 132static void cpsw_intr_rx_thresh(void *); 133static void cpsw_intr_misc(void *); 134static void cpswp_tick(void *); 135static void cpswp_ifmedia_sts(struct ifnet *, struct ifmediareq *); 136static int cpswp_ifmedia_upd(struct ifnet *); 137static void cpsw_tx_watchdog(void *); 138 139/* ALE support */ 140static void cpsw_ale_read_entry(struct cpsw_softc *, uint16_t, uint32_t *); 141static void cpsw_ale_write_entry(struct cpsw_softc *, uint16_t, uint32_t *); 142static int cpsw_ale_mc_entry_set(struct cpsw_softc *, uint8_t, int, uint8_t *); 143static void cpsw_ale_dump_table(struct cpsw_softc *); 144static int cpsw_ale_update_vlan_table(struct cpsw_softc *, int, int, int, int, 145 int); 146static int cpswp_ale_update_addresses(struct cpswp_softc *, int); 147 148/* Statistics and sysctls. */ 149static void cpsw_add_sysctls(struct cpsw_softc *); 150static void cpsw_stats_collect(struct cpsw_softc *); 151static int cpsw_stats_sysctl(SYSCTL_HANDLER_ARGS); 152 153#ifdef CPSW_ETHERSWITCH 154static etherswitch_info_t *cpsw_getinfo(device_t); 155static int cpsw_getport(device_t, etherswitch_port_t *); 156static int cpsw_setport(device_t, etherswitch_port_t *); 157static int cpsw_getconf(device_t, etherswitch_conf_t *); 158static int cpsw_getvgroup(device_t, etherswitch_vlangroup_t *); 159static int cpsw_setvgroup(device_t, etherswitch_vlangroup_t *); 160static int cpsw_readreg(device_t, int); 161static int cpsw_writereg(device_t, int, int); 162static int cpsw_readphy(device_t, int, int); 163static int cpsw_writephy(device_t, int, int, int); 164#endif 165 166/* 167 * Arbitrary limit on number of segments in an mbuf to be transmitted. 168 * Packets with more segments than this will be defragmented before 169 * they are queued. 170 */ 171#define CPSW_TXFRAGS 16 172 173/* Shared resources. */ 174static device_method_t cpsw_methods[] = { 175 /* Device interface */ 176 DEVMETHOD(device_probe, cpsw_probe), 177 DEVMETHOD(device_attach, cpsw_attach), 178 DEVMETHOD(device_detach, cpsw_detach), 179 DEVMETHOD(device_shutdown, cpsw_shutdown), 180 DEVMETHOD(device_suspend, cpsw_suspend), 181 DEVMETHOD(device_resume, cpsw_resume), 182 /* Bus interface */ 183 DEVMETHOD(bus_add_child, device_add_child_ordered), 184 /* OFW methods */ 185 DEVMETHOD(ofw_bus_get_node, cpsw_get_node), 186#ifdef CPSW_ETHERSWITCH 187 /* etherswitch interface */ 188 DEVMETHOD(etherswitch_getinfo, cpsw_getinfo), 189 DEVMETHOD(etherswitch_readreg, cpsw_readreg), 190 DEVMETHOD(etherswitch_writereg, cpsw_writereg), 191 DEVMETHOD(etherswitch_readphyreg, cpsw_readphy), 192 DEVMETHOD(etherswitch_writephyreg, cpsw_writephy), 193 DEVMETHOD(etherswitch_getport, cpsw_getport), 194 DEVMETHOD(etherswitch_setport, cpsw_setport), 195 DEVMETHOD(etherswitch_getvgroup, cpsw_getvgroup), 196 DEVMETHOD(etherswitch_setvgroup, cpsw_setvgroup), 197 DEVMETHOD(etherswitch_getconf, cpsw_getconf), 198#endif 199 DEVMETHOD_END 200}; 201 202static driver_t cpsw_driver = { 203 "cpswss", 204 cpsw_methods, 205 sizeof(struct cpsw_softc), 206}; 207 208static devclass_t cpsw_devclass; 209 210DRIVER_MODULE(cpswss, simplebus, cpsw_driver, cpsw_devclass, 0, 0); 211 212/* Port/Slave resources. */ 213static device_method_t cpswp_methods[] = { 214 /* Device interface */ 215 DEVMETHOD(device_probe, cpswp_probe), 216 DEVMETHOD(device_attach, cpswp_attach), 217 DEVMETHOD(device_detach, cpswp_detach), 218 /* MII interface */ 219 DEVMETHOD(miibus_readreg, cpswp_miibus_readreg), 220 DEVMETHOD(miibus_writereg, cpswp_miibus_writereg), 221 DEVMETHOD(miibus_statchg, cpswp_miibus_statchg), 222 DEVMETHOD_END 223}; 224 225static driver_t cpswp_driver = { 226 "cpsw", 227 cpswp_methods, 228 sizeof(struct cpswp_softc), 229}; 230 231static devclass_t cpswp_devclass; 232 233#ifdef CPSW_ETHERSWITCH 234DRIVER_MODULE(etherswitch, cpswss, etherswitch_driver, etherswitch_devclass, 0, 0); 235MODULE_DEPEND(cpswss, etherswitch, 1, 1, 1); 236#endif 237 238DRIVER_MODULE(cpsw, cpswss, cpswp_driver, cpswp_devclass, 0, 0); 239DRIVER_MODULE(miibus, cpsw, miibus_driver, miibus_devclass, 0, 0); 240MODULE_DEPEND(cpsw, ether, 1, 1, 1); 241MODULE_DEPEND(cpsw, miibus, 1, 1, 1); 242 243#ifdef CPSW_ETHERSWITCH 244static struct cpsw_vlangroups cpsw_vgroups[CPSW_VLANS]; 245#endif 246 247static uint32_t slave_mdio_addr[] = { 0x4a100200, 0x4a100300 }; 248 249static struct resource_spec irq_res_spec[] = { 250 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 251 { SYS_RES_IRQ, 1, RF_ACTIVE | RF_SHAREABLE }, 252 { SYS_RES_IRQ, 2, RF_ACTIVE | RF_SHAREABLE }, 253 { SYS_RES_IRQ, 3, RF_ACTIVE | RF_SHAREABLE }, 254 { -1, 0 } 255}; 256 257static struct { 258 void (*cb)(void *); 259} cpsw_intr_cb[] = { 260 { cpsw_intr_rx_thresh }, 261 { cpsw_intr_rx }, 262 { cpsw_intr_tx }, 263 { cpsw_intr_misc }, 264}; 265 266/* Number of entries here must match size of stats 267 * array in struct cpswp_softc. */ 268static struct cpsw_stat { 269 int reg; 270 char *oid; 271} cpsw_stat_sysctls[CPSW_SYSCTL_COUNT] = { 272 {0x00, "GoodRxFrames"}, 273 {0x04, "BroadcastRxFrames"}, 274 {0x08, "MulticastRxFrames"}, 275 {0x0C, "PauseRxFrames"}, 276 {0x10, "RxCrcErrors"}, 277 {0x14, "RxAlignErrors"}, 278 {0x18, "OversizeRxFrames"}, 279 {0x1c, "RxJabbers"}, 280 {0x20, "ShortRxFrames"}, 281 {0x24, "RxFragments"}, 282 {0x30, "RxOctets"}, 283 {0x34, "GoodTxFrames"}, 284 {0x38, "BroadcastTxFrames"}, 285 {0x3c, "MulticastTxFrames"}, 286 {0x40, "PauseTxFrames"}, 287 {0x44, "DeferredTxFrames"}, 288 {0x48, "CollisionsTxFrames"}, 289 {0x4c, "SingleCollisionTxFrames"}, 290 {0x50, "MultipleCollisionTxFrames"}, 291 {0x54, "ExcessiveCollisions"}, 292 {0x58, "LateCollisions"}, 293 {0x5c, "TxUnderrun"}, 294 {0x60, "CarrierSenseErrors"}, 295 {0x64, "TxOctets"}, 296 {0x68, "RxTx64OctetFrames"}, 297 {0x6c, "RxTx65to127OctetFrames"}, 298 {0x70, "RxTx128to255OctetFrames"}, 299 {0x74, "RxTx256to511OctetFrames"}, 300 {0x78, "RxTx512to1024OctetFrames"}, 301 {0x7c, "RxTx1024upOctetFrames"}, 302 {0x80, "NetOctets"}, 303 {0x84, "RxStartOfFrameOverruns"}, 304 {0x88, "RxMiddleOfFrameOverruns"}, 305 {0x8c, "RxDmaOverruns"} 306}; 307 308/* 309 * Basic debug support. 310 */ 311 312static void 313cpsw_debugf_head(const char *funcname) 314{ 315 int t = (int)(time_second % (24 * 60 * 60)); 316 317 printf("%02d:%02d:%02d %s ", t / (60 * 60), (t / 60) % 60, t % 60, funcname); 318} 319 320static void 321cpsw_debugf(const char *fmt, ...) 322{ 323 va_list ap; 324 325 va_start(ap, fmt); 326 vprintf(fmt, ap); 327 va_end(ap); 328 printf("\n"); 329 330} 331 332#define CPSW_DEBUGF(_sc, a) do { \ 333 if ((_sc)->debug) { \ 334 cpsw_debugf_head(__func__); \ 335 cpsw_debugf a; \ 336 } \ 337} while (0) 338 339/* 340 * Locking macros 341 */ 342#define CPSW_TX_LOCK(sc) do { \ 343 mtx_assert(&(sc)->rx.lock, MA_NOTOWNED); \ 344 mtx_lock(&(sc)->tx.lock); \ 345} while (0) 346 347#define CPSW_TX_UNLOCK(sc) mtx_unlock(&(sc)->tx.lock) 348#define CPSW_TX_LOCK_ASSERT(sc) mtx_assert(&(sc)->tx.lock, MA_OWNED) 349 350#define CPSW_RX_LOCK(sc) do { \ 351 mtx_assert(&(sc)->tx.lock, MA_NOTOWNED); \ 352 mtx_lock(&(sc)->rx.lock); \ 353} while (0) 354 355#define CPSW_RX_UNLOCK(sc) mtx_unlock(&(sc)->rx.lock) 356#define CPSW_RX_LOCK_ASSERT(sc) mtx_assert(&(sc)->rx.lock, MA_OWNED) 357 358#define CPSW_PORT_LOCK(_sc) do { \ 359 mtx_assert(&(_sc)->lock, MA_NOTOWNED); \ 360 mtx_lock(&(_sc)->lock); \ 361} while (0) 362 363#define CPSW_PORT_UNLOCK(_sc) mtx_unlock(&(_sc)->lock) 364#define CPSW_PORT_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->lock, MA_OWNED) 365 366/* 367 * Read/Write macros 368 */ 369#define cpsw_read_4(_sc, _reg) bus_read_4((_sc)->mem_res, (_reg)) 370#define cpsw_write_4(_sc, _reg, _val) \ 371 bus_write_4((_sc)->mem_res, (_reg), (_val)) 372 373#define cpsw_cpdma_bd_offset(i) (CPSW_CPPI_RAM_OFFSET + ((i)*16)) 374 375#define cpsw_cpdma_bd_paddr(sc, slot) \ 376 BUS_SPACE_PHYSADDR(sc->mem_res, slot->bd_offset) 377#define cpsw_cpdma_read_bd(sc, slot, val) \ 378 bus_read_region_4(sc->mem_res, slot->bd_offset, (uint32_t *) val, 4) 379#define cpsw_cpdma_write_bd(sc, slot, val) \ 380 bus_write_region_4(sc->mem_res, slot->bd_offset, (uint32_t *) val, 4) 381#define cpsw_cpdma_write_bd_next(sc, slot, next_slot) \ 382 cpsw_write_4(sc, slot->bd_offset, cpsw_cpdma_bd_paddr(sc, next_slot)) 383#define cpsw_cpdma_write_bd_flags(sc, slot, val) \ 384 bus_write_2(sc->mem_res, slot->bd_offset + 14, val) 385#define cpsw_cpdma_read_bd_flags(sc, slot) \ 386 bus_read_2(sc->mem_res, slot->bd_offset + 14) 387#define cpsw_write_hdp_slot(sc, queue, slot) \ 388 cpsw_write_4(sc, (queue)->hdp_offset, cpsw_cpdma_bd_paddr(sc, slot)) 389#define CP_OFFSET (CPSW_CPDMA_TX_CP(0) - CPSW_CPDMA_TX_HDP(0)) 390#define cpsw_read_cp(sc, queue) \ 391 cpsw_read_4(sc, (queue)->hdp_offset + CP_OFFSET) 392#define cpsw_write_cp(sc, queue, val) \ 393 cpsw_write_4(sc, (queue)->hdp_offset + CP_OFFSET, (val)) 394#define cpsw_write_cp_slot(sc, queue, slot) \ 395 cpsw_write_cp(sc, queue, cpsw_cpdma_bd_paddr(sc, slot)) 396 397#if 0 398/* XXX temporary function versions for debugging. */ 399static void 400cpsw_write_hdp_slotX(struct cpsw_softc *sc, struct cpsw_queue *queue, struct cpsw_slot *slot) 401{ 402 uint32_t reg = queue->hdp_offset; 403 uint32_t v = cpsw_cpdma_bd_paddr(sc, slot); 404 CPSW_DEBUGF(("HDP <=== 0x%08x (was 0x%08x)", v, cpsw_read_4(sc, reg))); 405 cpsw_write_4(sc, reg, v); 406} 407 408static void 409cpsw_write_cp_slotX(struct cpsw_softc *sc, struct cpsw_queue *queue, struct cpsw_slot *slot) 410{ 411 uint32_t v = cpsw_cpdma_bd_paddr(sc, slot); 412 CPSW_DEBUGF(("CP <=== 0x%08x (expecting 0x%08x)", v, cpsw_read_cp(sc, queue))); 413 cpsw_write_cp(sc, queue, v); 414} 415#endif 416 417/* 418 * Expanded dump routines for verbose debugging. 419 */ 420static void 421cpsw_dump_slot(struct cpsw_softc *sc, struct cpsw_slot *slot) 422{ 423 static const char *flags[] = {"SOP", "EOP", "Owner", "EOQ", 424 "TDownCmplt", "PassCRC", "Long", "Short", "MacCtl", "Overrun", 425 "PktErr1", "PortEn/PktErr0", "RxVlanEncap", "Port2", "Port1", 426 "Port0"}; 427 struct cpsw_cpdma_bd bd; 428 const char *sep; 429 int i; 430 431 cpsw_cpdma_read_bd(sc, slot, &bd); 432 printf("BD Addr : 0x%08x Next : 0x%08x\n", 433 cpsw_cpdma_bd_paddr(sc, slot), bd.next); 434 printf(" BufPtr: 0x%08x BufLen: 0x%08x\n", bd.bufptr, bd.buflen); 435 printf(" BufOff: 0x%08x PktLen: 0x%08x\n", bd.bufoff, bd.pktlen); 436 printf(" Flags: "); 437 sep = ""; 438 for (i = 0; i < 16; ++i) { 439 if (bd.flags & (1 << (15 - i))) { 440 printf("%s%s", sep, flags[i]); 441 sep = ","; 442 } 443 } 444 printf("\n"); 445 if (slot->mbuf) { 446 printf(" Ether: %14D\n", 447 (char *)(slot->mbuf->m_data), " "); 448 printf(" Packet: %16D\n", 449 (char *)(slot->mbuf->m_data) + 14, " "); 450 } 451} 452 453#define CPSW_DUMP_SLOT(cs, slot) do { \ 454 IF_DEBUG(sc) { \ 455 cpsw_dump_slot(sc, slot); \ 456 } \ 457} while (0) 458 459static void 460cpsw_dump_queue(struct cpsw_softc *sc, struct cpsw_slots *q) 461{ 462 struct cpsw_slot *slot; 463 int i = 0; 464 int others = 0; 465 466 STAILQ_FOREACH(slot, q, next) { 467 if (i > CPSW_TXFRAGS) 468 ++others; 469 else 470 cpsw_dump_slot(sc, slot); 471 ++i; 472 } 473 if (others) 474 printf(" ... and %d more.\n", others); 475 printf("\n"); 476} 477 478#define CPSW_DUMP_QUEUE(sc, q) do { \ 479 IF_DEBUG(sc) { \ 480 cpsw_dump_queue(sc, q); \ 481 } \ 482} while (0) 483 484static void 485cpsw_init_slots(struct cpsw_softc *sc) 486{ 487 struct cpsw_slot *slot; 488 int i; 489 490 STAILQ_INIT(&sc->avail); 491 492 /* Put the slot descriptors onto the global avail list. */ 493 for (i = 0; i < nitems(sc->_slots); i++) { 494 slot = &sc->_slots[i]; 495 slot->bd_offset = cpsw_cpdma_bd_offset(i); 496 STAILQ_INSERT_TAIL(&sc->avail, slot, next); 497 } 498} 499 500static int 501cpsw_add_slots(struct cpsw_softc *sc, struct cpsw_queue *queue, int requested) 502{ 503 const int max_slots = nitems(sc->_slots); 504 struct cpsw_slot *slot; 505 int i; 506 507 if (requested < 0) 508 requested = max_slots; 509 510 for (i = 0; i < requested; ++i) { 511 slot = STAILQ_FIRST(&sc->avail); 512 if (slot == NULL) 513 return (0); 514 if (bus_dmamap_create(sc->mbuf_dtag, 0, &slot->dmamap)) { 515 device_printf(sc->dev, "failed to create dmamap\n"); 516 return (ENOMEM); 517 } 518 STAILQ_REMOVE_HEAD(&sc->avail, next); 519 STAILQ_INSERT_TAIL(&queue->avail, slot, next); 520 ++queue->avail_queue_len; 521 ++queue->queue_slots; 522 } 523 return (0); 524} 525 526static void 527cpsw_free_slot(struct cpsw_softc *sc, struct cpsw_slot *slot) 528{ 529 int error; 530 531 if (slot->dmamap) { 532 if (slot->mbuf) 533 bus_dmamap_unload(sc->mbuf_dtag, slot->dmamap); 534 error = bus_dmamap_destroy(sc->mbuf_dtag, slot->dmamap); 535 KASSERT(error == 0, ("Mapping still active")); 536 slot->dmamap = NULL; 537 } 538 if (slot->mbuf) { 539 m_freem(slot->mbuf); 540 slot->mbuf = NULL; 541 } 542} 543 544static void 545cpsw_reset(struct cpsw_softc *sc) 546{ 547 int i; 548 549 callout_stop(&sc->watchdog.callout); 550 551 /* Reset RMII/RGMII wrapper. */ 552 cpsw_write_4(sc, CPSW_WR_SOFT_RESET, 1); 553 while (cpsw_read_4(sc, CPSW_WR_SOFT_RESET) & 1) 554 ; 555 556 /* Disable TX and RX interrupts for all cores. */ 557 for (i = 0; i < 3; ++i) { 558 cpsw_write_4(sc, CPSW_WR_C_RX_THRESH_EN(i), 0x00); 559 cpsw_write_4(sc, CPSW_WR_C_TX_EN(i), 0x00); 560 cpsw_write_4(sc, CPSW_WR_C_RX_EN(i), 0x00); 561 cpsw_write_4(sc, CPSW_WR_C_MISC_EN(i), 0x00); 562 } 563 564 /* Reset CPSW subsystem. */ 565 cpsw_write_4(sc, CPSW_SS_SOFT_RESET, 1); 566 while (cpsw_read_4(sc, CPSW_SS_SOFT_RESET) & 1) 567 ; 568 569 /* Reset Sliver port 1 and 2 */ 570 for (i = 0; i < 2; i++) { 571 /* Reset */ 572 cpsw_write_4(sc, CPSW_SL_SOFT_RESET(i), 1); 573 while (cpsw_read_4(sc, CPSW_SL_SOFT_RESET(i)) & 1) 574 ; 575 } 576 577 /* Reset DMA controller. */ 578 cpsw_write_4(sc, CPSW_CPDMA_SOFT_RESET, 1); 579 while (cpsw_read_4(sc, CPSW_CPDMA_SOFT_RESET) & 1) 580 ; 581 582 /* Disable TX & RX DMA */ 583 cpsw_write_4(sc, CPSW_CPDMA_TX_CONTROL, 0); 584 cpsw_write_4(sc, CPSW_CPDMA_RX_CONTROL, 0); 585 586 /* Clear all queues. */ 587 for (i = 0; i < 8; i++) { 588 cpsw_write_4(sc, CPSW_CPDMA_TX_HDP(i), 0); 589 cpsw_write_4(sc, CPSW_CPDMA_RX_HDP(i), 0); 590 cpsw_write_4(sc, CPSW_CPDMA_TX_CP(i), 0); 591 cpsw_write_4(sc, CPSW_CPDMA_RX_CP(i), 0); 592 } 593 594 /* Clear all interrupt Masks */ 595 cpsw_write_4(sc, CPSW_CPDMA_RX_INTMASK_CLEAR, 0xFFFFFFFF); 596 cpsw_write_4(sc, CPSW_CPDMA_TX_INTMASK_CLEAR, 0xFFFFFFFF); 597} 598 599static void 600cpsw_init(struct cpsw_softc *sc) 601{ 602 struct cpsw_slot *slot; 603 uint32_t reg; 604 605 /* Disable the interrupt pacing. */ 606 reg = cpsw_read_4(sc, CPSW_WR_INT_CONTROL); 607 reg &= ~(CPSW_WR_INT_PACE_EN | CPSW_WR_INT_PRESCALE_MASK); 608 cpsw_write_4(sc, CPSW_WR_INT_CONTROL, reg); 609 610 /* Clear ALE */ 611 cpsw_write_4(sc, CPSW_ALE_CONTROL, CPSW_ALE_CTL_CLEAR_TBL); 612 613 /* Enable ALE */ 614 reg = CPSW_ALE_CTL_ENABLE; 615 if (sc->dualemac) 616 reg |= CPSW_ALE_CTL_VLAN_AWARE; 617 cpsw_write_4(sc, CPSW_ALE_CONTROL, reg); 618 619 /* Set Host Port Mapping. */ 620 cpsw_write_4(sc, CPSW_PORT_P0_CPDMA_TX_PRI_MAP, 0x76543210); 621 cpsw_write_4(sc, CPSW_PORT_P0_CPDMA_RX_CH_MAP, 0); 622 623 /* Initialize ALE: set host port to forwarding(3). */ 624 cpsw_write_4(sc, CPSW_ALE_PORTCTL(0), 625 ALE_PORTCTL_INGRESS | ALE_PORTCTL_FORWARD); 626 627 cpsw_write_4(sc, CPSW_SS_PTYPE, 0); 628 629 /* Enable statistics for ports 0, 1 and 2 */ 630 cpsw_write_4(sc, CPSW_SS_STAT_PORT_EN, 7); 631 632 /* Turn off flow control. */ 633 cpsw_write_4(sc, CPSW_SS_FLOW_CONTROL, 0); 634 635 /* Make IP hdr aligned with 4 */ 636 cpsw_write_4(sc, CPSW_CPDMA_RX_BUFFER_OFFSET, 2); 637 638 /* Initialize RX Buffer Descriptors */ 639 cpsw_write_4(sc, CPSW_CPDMA_RX_PENDTHRESH(0), 0); 640 cpsw_write_4(sc, CPSW_CPDMA_RX_FREEBUFFER(0), 0); 641 642 /* Enable TX & RX DMA */ 643 cpsw_write_4(sc, CPSW_CPDMA_TX_CONTROL, 1); 644 cpsw_write_4(sc, CPSW_CPDMA_RX_CONTROL, 1); 645 646 /* Enable Interrupts for core 0 */ 647 cpsw_write_4(sc, CPSW_WR_C_RX_THRESH_EN(0), 0xFF); 648 cpsw_write_4(sc, CPSW_WR_C_RX_EN(0), 0xFF); 649 cpsw_write_4(sc, CPSW_WR_C_TX_EN(0), 0xFF); 650 cpsw_write_4(sc, CPSW_WR_C_MISC_EN(0), 0x1F); 651 652 /* Enable host Error Interrupt */ 653 cpsw_write_4(sc, CPSW_CPDMA_DMA_INTMASK_SET, 3); 654 655 /* Enable interrupts for RX and TX on Channel 0 */ 656 cpsw_write_4(sc, CPSW_CPDMA_RX_INTMASK_SET, 657 CPSW_CPDMA_RX_INT(0) | CPSW_CPDMA_RX_INT_THRESH(0)); 658 cpsw_write_4(sc, CPSW_CPDMA_TX_INTMASK_SET, 1); 659 660 /* Initialze MDIO - ENABLE, PREAMBLE=0, FAULTENB, CLKDIV=0xFF */ 661 /* TODO Calculate MDCLK=CLK/(CLKDIV+1) */ 662 cpsw_write_4(sc, MDIOCONTROL, MDIOCTL_ENABLE | MDIOCTL_FAULTENB | 0xff); 663 664 /* Select MII in GMII_SEL, Internal Delay mode */ 665 //ti_scm_reg_write_4(0x650, 0); 666 667 /* Initialize active queues. */ 668 slot = STAILQ_FIRST(&sc->tx.active); 669 if (slot != NULL) 670 cpsw_write_hdp_slot(sc, &sc->tx, slot); 671 slot = STAILQ_FIRST(&sc->rx.active); 672 if (slot != NULL) 673 cpsw_write_hdp_slot(sc, &sc->rx, slot); 674 cpsw_rx_enqueue(sc); 675 cpsw_write_4(sc, CPSW_CPDMA_RX_FREEBUFFER(0), sc->rx.active_queue_len); 676 cpsw_write_4(sc, CPSW_CPDMA_RX_PENDTHRESH(0), CPSW_TXFRAGS); 677 678 /* Activate network interface. */ 679 sc->rx.running = 1; 680 sc->tx.running = 1; 681 sc->watchdog.timer = 0; 682 callout_init(&sc->watchdog.callout, 0); 683 callout_reset(&sc->watchdog.callout, hz, cpsw_tx_watchdog, sc); 684} 685 686/* 687 * 688 * Device Probe, Attach, Detach. 689 * 690 */ 691 692static int 693cpsw_probe(device_t dev) 694{ 695 696 if (!ofw_bus_status_okay(dev)) 697 return (ENXIO); 698 699 if (!ofw_bus_is_compatible(dev, "ti,cpsw")) 700 return (ENXIO); 701 702 device_set_desc(dev, "3-port Switch Ethernet Subsystem"); 703 return (BUS_PROBE_DEFAULT); 704} 705 706static int 707cpsw_intr_attach(struct cpsw_softc *sc) 708{ 709 int i; 710 711 for (i = 0; i < CPSW_INTR_COUNT; i++) { 712 if (bus_setup_intr(sc->dev, sc->irq_res[i], 713 INTR_TYPE_NET | INTR_MPSAFE, NULL, 714 cpsw_intr_cb[i].cb, sc, &sc->ih_cookie[i]) != 0) { 715 return (-1); 716 } 717 } 718 719 return (0); 720} 721 722static void 723cpsw_intr_detach(struct cpsw_softc *sc) 724{ 725 int i; 726 727 for (i = 0; i < CPSW_INTR_COUNT; i++) { 728 if (sc->ih_cookie[i]) { 729 bus_teardown_intr(sc->dev, sc->irq_res[i], 730 sc->ih_cookie[i]); 731 } 732 } 733} 734 735static int 736cpsw_get_fdt_data(struct cpsw_softc *sc, int port) 737{ 738 char *name; 739 int len, phy, vlan; 740 pcell_t phy_id[3], vlan_id; 741 phandle_t child; 742 unsigned long mdio_child_addr; 743 744 /* Find any slave with phy_id */ 745 phy = -1; 746 vlan = -1; 747 for (child = OF_child(sc->node); child != 0; child = OF_peer(child)) { 748 if (OF_getprop_alloc(child, "name", 1, (void **)&name) < 0) 749 continue; 750 if (sscanf(name, "slave@%x", &mdio_child_addr) != 1) { 751 OF_prop_free(name); 752 continue; 753 } 754 OF_prop_free(name); 755 if (mdio_child_addr != slave_mdio_addr[port]) 756 continue; 757 758 len = OF_getproplen(child, "phy_id"); 759 if (len / sizeof(pcell_t) == 2) { 760 /* Get phy address from fdt */ 761 if (OF_getencprop(child, "phy_id", phy_id, len) > 0) 762 phy = phy_id[1]; 763 } 764 765 len = OF_getproplen(child, "dual_emac_res_vlan"); 766 if (len / sizeof(pcell_t) == 1) { 767 /* Get phy address from fdt */ 768 if (OF_getencprop(child, "dual_emac_res_vlan", 769 &vlan_id, len) > 0) { 770 vlan = vlan_id; 771 } 772 } 773 774 break; 775 } 776 if (phy == -1) 777 return (ENXIO); 778 sc->port[port].phy = phy; 779 sc->port[port].vlan = vlan; 780 781 return (0); 782} 783 784static int 785cpsw_attach(device_t dev) 786{ 787 bus_dma_segment_t segs[1]; 788 int error, i, nsegs; 789 struct cpsw_softc *sc; 790 uint32_t reg; 791 792 sc = device_get_softc(dev); 793 sc->dev = dev; 794 sc->node = ofw_bus_get_node(dev); 795 getbinuptime(&sc->attach_uptime); 796 797 if (OF_getencprop(sc->node, "active_slave", &sc->active_slave, 798 sizeof(sc->active_slave)) <= 0) { 799 sc->active_slave = 0; 800 } 801 if (sc->active_slave > 1) 802 sc->active_slave = 1; 803 804 if (OF_hasprop(sc->node, "dual_emac")) 805 sc->dualemac = 1; 806 807 for (i = 0; i < CPSW_PORTS; i++) { 808 if (!sc->dualemac && i != sc->active_slave) 809 continue; 810 if (cpsw_get_fdt_data(sc, i) != 0) { 811 device_printf(dev, 812 "failed to get PHY address from FDT\n"); 813 return (ENXIO); 814 } 815 } 816 817 /* Initialize mutexes */ 818 mtx_init(&sc->tx.lock, device_get_nameunit(dev), 819 "cpsw TX lock", MTX_DEF); 820 mtx_init(&sc->rx.lock, device_get_nameunit(dev), 821 "cpsw RX lock", MTX_DEF); 822 823 /* Allocate IRQ resources */ 824 error = bus_alloc_resources(dev, irq_res_spec, sc->irq_res); 825 if (error) { 826 device_printf(dev, "could not allocate IRQ resources\n"); 827 cpsw_detach(dev); 828 return (ENXIO); 829 } 830 831 sc->mem_rid = 0; 832 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 833 &sc->mem_rid, RF_ACTIVE); 834 if (sc->mem_res == NULL) { 835 device_printf(sc->dev, "failed to allocate memory resource\n"); 836 cpsw_detach(dev); 837 return (ENXIO); 838 } 839 840 reg = cpsw_read_4(sc, CPSW_SS_IDVER); 841 device_printf(dev, "CPSW SS Version %d.%d (%d)\n", (reg >> 8 & 0x7), 842 reg & 0xFF, (reg >> 11) & 0x1F); 843 844 cpsw_add_sysctls(sc); 845 846 /* Allocate a busdma tag and DMA safe memory for mbufs. */ 847 error = bus_dma_tag_create( 848 bus_get_dma_tag(sc->dev), /* parent */ 849 1, 0, /* alignment, boundary */ 850 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 851 BUS_SPACE_MAXADDR, /* highaddr */ 852 NULL, NULL, /* filtfunc, filtfuncarg */ 853 MCLBYTES, CPSW_TXFRAGS, /* maxsize, nsegments */ 854 MCLBYTES, 0, /* maxsegsz, flags */ 855 NULL, NULL, /* lockfunc, lockfuncarg */ 856 &sc->mbuf_dtag); /* dmatag */ 857 if (error) { 858 device_printf(dev, "bus_dma_tag_create failed\n"); 859 cpsw_detach(dev); 860 return (error); 861 } 862 863 /* Allocate the null mbuf and pre-sync it. */ 864 sc->null_mbuf = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 865 memset(sc->null_mbuf->m_data, 0, sc->null_mbuf->m_ext.ext_size); 866 bus_dmamap_create(sc->mbuf_dtag, 0, &sc->null_mbuf_dmamap); 867 bus_dmamap_load_mbuf_sg(sc->mbuf_dtag, sc->null_mbuf_dmamap, 868 sc->null_mbuf, segs, &nsegs, BUS_DMA_NOWAIT); 869 bus_dmamap_sync(sc->mbuf_dtag, sc->null_mbuf_dmamap, 870 BUS_DMASYNC_PREWRITE); 871 sc->null_mbuf_paddr = segs[0].ds_addr; 872 873 cpsw_init_slots(sc); 874 875 /* Allocate slots to TX and RX queues. */ 876 STAILQ_INIT(&sc->rx.avail); 877 STAILQ_INIT(&sc->rx.active); 878 STAILQ_INIT(&sc->tx.avail); 879 STAILQ_INIT(&sc->tx.active); 880 // For now: 128 slots to TX, rest to RX. 881 // XXX TODO: start with 32/64 and grow dynamically based on demand. 882 if (cpsw_add_slots(sc, &sc->tx, 128) || 883 cpsw_add_slots(sc, &sc->rx, -1)) { 884 device_printf(dev, "failed to allocate dmamaps\n"); 885 cpsw_detach(dev); 886 return (ENOMEM); 887 } 888 device_printf(dev, "Initial queue size TX=%d RX=%d\n", 889 sc->tx.queue_slots, sc->rx.queue_slots); 890 891 sc->tx.hdp_offset = CPSW_CPDMA_TX_HDP(0); 892 sc->rx.hdp_offset = CPSW_CPDMA_RX_HDP(0); 893 894 if (cpsw_intr_attach(sc) == -1) { 895 device_printf(dev, "failed to setup interrupts\n"); 896 cpsw_detach(dev); 897 return (ENXIO); 898 } 899 900#ifdef CPSW_ETHERSWITCH 901 for (i = 0; i < CPSW_VLANS; i++) 902 cpsw_vgroups[i].vid = -1; 903#endif 904 905 /* Reset the controller. */ 906 cpsw_reset(sc); 907 cpsw_init(sc); 908 909 for (i = 0; i < CPSW_PORTS; i++) { 910 if (!sc->dualemac && i != sc->active_slave) 911 continue; 912 sc->port[i].dev = device_add_child(dev, "cpsw", i); 913 if (sc->port[i].dev == NULL) { 914 cpsw_detach(dev); 915 return (ENXIO); 916 } 917 } 918 bus_generic_probe(dev); 919 bus_generic_attach(dev); 920 921 return (0); 922} 923 924static int 925cpsw_detach(device_t dev) 926{ 927 struct cpsw_softc *sc; 928 int error, i; 929 930 bus_generic_detach(dev); 931 sc = device_get_softc(dev); 932 933 for (i = 0; i < CPSW_PORTS; i++) { 934 if (sc->port[i].dev) 935 device_delete_child(dev, sc->port[i].dev); 936 } 937 938 if (device_is_attached(dev)) { 939 callout_stop(&sc->watchdog.callout); 940 callout_drain(&sc->watchdog.callout); 941 } 942 943 /* Stop and release all interrupts */ 944 cpsw_intr_detach(sc); 945 946 /* Free dmamaps and mbufs */ 947 for (i = 0; i < nitems(sc->_slots); ++i) 948 cpsw_free_slot(sc, &sc->_slots[i]); 949 950 /* Free null mbuf. */ 951 if (sc->null_mbuf_dmamap) { 952 bus_dmamap_unload(sc->mbuf_dtag, sc->null_mbuf_dmamap); 953 error = bus_dmamap_destroy(sc->mbuf_dtag, sc->null_mbuf_dmamap); 954 KASSERT(error == 0, ("Mapping still active")); 955 m_freem(sc->null_mbuf); 956 } 957 958 /* Free DMA tag */ 959 if (sc->mbuf_dtag) { 960 error = bus_dma_tag_destroy(sc->mbuf_dtag); 961 KASSERT(error == 0, ("Unable to destroy DMA tag")); 962 } 963 964 /* Free IO memory handler */ 965 if (sc->mem_res != NULL) 966 bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid, sc->mem_res); 967 bus_release_resources(dev, irq_res_spec, sc->irq_res); 968 969 /* Destroy mutexes */ 970 mtx_destroy(&sc->rx.lock); 971 mtx_destroy(&sc->tx.lock); 972 973 /* Detach the switch device, if present. */ 974 error = bus_generic_detach(dev); 975 if (error != 0) 976 return (error); 977 978 return (device_delete_children(dev)); 979} 980 981static phandle_t 982cpsw_get_node(device_t bus, device_t dev) 983{ 984 985 /* Share controller node with port device. */ 986 return (ofw_bus_get_node(bus)); 987} 988 989static int 990cpswp_probe(device_t dev) 991{ 992 993 if (device_get_unit(dev) > 1) { 994 device_printf(dev, "Only two ports are supported.\n"); 995 return (ENXIO); 996 } 997 device_set_desc(dev, "Ethernet Switch Port"); 998 999 return (BUS_PROBE_DEFAULT); 1000} 1001 1002static int 1003cpswp_attach(device_t dev) 1004{ 1005 int error; 1006 struct ifnet *ifp; 1007 struct cpswp_softc *sc; 1008 uint32_t reg; 1009 uint8_t mac_addr[ETHER_ADDR_LEN]; 1010 1011 sc = device_get_softc(dev); 1012 sc->dev = dev; 1013 sc->pdev = device_get_parent(dev); 1014 sc->swsc = device_get_softc(sc->pdev); 1015 sc->unit = device_get_unit(dev); 1016 sc->phy = sc->swsc->port[sc->unit].phy; 1017 sc->vlan = sc->swsc->port[sc->unit].vlan; 1018 if (sc->swsc->dualemac && sc->vlan == -1) 1019 sc->vlan = sc->unit + 1; 1020 1021 if (sc->unit == 0) { 1022 sc->physel = MDIOUSERPHYSEL0; 1023 sc->phyaccess = MDIOUSERACCESS0; 1024 } else { 1025 sc->physel = MDIOUSERPHYSEL1; 1026 sc->phyaccess = MDIOUSERACCESS1; 1027 } 1028 1029 mtx_init(&sc->lock, device_get_nameunit(dev), "cpsw port lock", 1030 MTX_DEF); 1031 1032 /* Allocate network interface */ 1033 ifp = sc->ifp = if_alloc(IFT_ETHER); 1034 if (ifp == NULL) { 1035 cpswp_detach(dev); 1036 return (ENXIO); 1037 } 1038 1039 if_initname(ifp, device_get_name(sc->dev), sc->unit); 1040 ifp->if_softc = sc; 1041 ifp->if_flags = IFF_SIMPLEX | IFF_MULTICAST | IFF_BROADCAST; 1042 ifp->if_capabilities = IFCAP_VLAN_MTU | IFCAP_HWCSUM; //FIXME VLAN? 1043 ifp->if_capenable = ifp->if_capabilities; 1044 1045 ifp->if_init = cpswp_init; 1046 ifp->if_start = cpswp_start; 1047 ifp->if_ioctl = cpswp_ioctl; 1048 1049 ifp->if_snd.ifq_drv_maxlen = sc->swsc->tx.queue_slots; 1050 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 1051 IFQ_SET_READY(&ifp->if_snd); 1052 1053 /* Get high part of MAC address from control module (mac_id[0|1]_hi) */ 1054 ti_scm_reg_read_4(SCM_MAC_ID0_HI + sc->unit * 8, ®); 1055 mac_addr[0] = reg & 0xFF; 1056 mac_addr[1] = (reg >> 8) & 0xFF; 1057 mac_addr[2] = (reg >> 16) & 0xFF; 1058 mac_addr[3] = (reg >> 24) & 0xFF; 1059 1060 /* Get low part of MAC address from control module (mac_id[0|1]_lo) */ 1061 ti_scm_reg_read_4(SCM_MAC_ID0_LO + sc->unit * 8, ®); 1062 mac_addr[4] = reg & 0xFF; 1063 mac_addr[5] = (reg >> 8) & 0xFF; 1064 1065 error = mii_attach(dev, &sc->miibus, ifp, cpswp_ifmedia_upd, 1066 cpswp_ifmedia_sts, BMSR_DEFCAPMASK, sc->phy, MII_OFFSET_ANY, 0); 1067 if (error) { 1068 device_printf(dev, "attaching PHYs failed\n"); 1069 cpswp_detach(dev); 1070 return (error); 1071 } 1072 sc->mii = device_get_softc(sc->miibus); 1073 1074 /* Select PHY and enable interrupts */ 1075 cpsw_write_4(sc->swsc, sc->physel, 1076 MDIO_PHYSEL_LINKINTENB | (sc->phy & 0x1F)); 1077 1078 ether_ifattach(sc->ifp, mac_addr); 1079 callout_init(&sc->mii_callout, 0); 1080 1081 return (0); 1082} 1083 1084static int 1085cpswp_detach(device_t dev) 1086{ 1087 struct cpswp_softc *sc; 1088 1089 sc = device_get_softc(dev); 1090 CPSW_DEBUGF(sc->swsc, ("")); 1091 if (device_is_attached(dev)) { 1092 ether_ifdetach(sc->ifp); 1093 CPSW_PORT_LOCK(sc); 1094 cpswp_stop_locked(sc); 1095 CPSW_PORT_UNLOCK(sc); 1096 callout_drain(&sc->mii_callout); 1097 } 1098 1099 bus_generic_detach(dev); 1100 1101 if_free(sc->ifp); 1102 mtx_destroy(&sc->lock); 1103 1104 return (0); 1105} 1106 1107/* 1108 * 1109 * Init/Shutdown. 1110 * 1111 */ 1112 1113static int 1114cpsw_ports_down(struct cpsw_softc *sc) 1115{ 1116 struct cpswp_softc *psc; 1117 struct ifnet *ifp1, *ifp2; 1118 1119 if (!sc->dualemac) 1120 return (1); 1121 psc = device_get_softc(sc->port[0].dev); 1122 ifp1 = psc->ifp; 1123 psc = device_get_softc(sc->port[1].dev); 1124 ifp2 = psc->ifp; 1125 if ((ifp1->if_flags & IFF_UP) == 0 && (ifp2->if_flags & IFF_UP) == 0) 1126 return (1); 1127 1128 return (0); 1129} 1130 1131static void 1132cpswp_init(void *arg) 1133{ 1134 struct cpswp_softc *sc = arg; 1135 1136 CPSW_DEBUGF(sc->swsc, ("")); 1137 CPSW_PORT_LOCK(sc); 1138 cpswp_init_locked(arg); 1139 CPSW_PORT_UNLOCK(sc); 1140} 1141 1142static void 1143cpswp_init_locked(void *arg) 1144{ 1145#ifdef CPSW_ETHERSWITCH 1146 int i; 1147#endif 1148 struct cpswp_softc *sc = arg; 1149 struct ifnet *ifp; 1150 uint32_t reg; 1151 1152 CPSW_DEBUGF(sc->swsc, ("")); 1153 CPSW_PORT_LOCK_ASSERT(sc); 1154 ifp = sc->ifp; 1155 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1156 return; 1157 1158 getbinuptime(&sc->init_uptime); 1159 1160 if (!sc->swsc->rx.running && !sc->swsc->tx.running) { 1161 /* Reset the controller. */ 1162 cpsw_reset(sc->swsc); 1163 cpsw_init(sc->swsc); 1164 } 1165 1166 /* Set Slave Mapping. */ 1167 cpsw_write_4(sc->swsc, CPSW_SL_RX_PRI_MAP(sc->unit), 0x76543210); 1168 cpsw_write_4(sc->swsc, CPSW_PORT_P_TX_PRI_MAP(sc->unit + 1), 1169 0x33221100); 1170 cpsw_write_4(sc->swsc, CPSW_SL_RX_MAXLEN(sc->unit), 0x5f2); 1171 /* Enable MAC RX/TX modules. */ 1172 /* TODO: Docs claim that IFCTL_B and IFCTL_A do the same thing? */ 1173 /* Huh? Docs call bit 0 "Loopback" some places, "FullDuplex" others. */ 1174 reg = cpsw_read_4(sc->swsc, CPSW_SL_MACCONTROL(sc->unit)); 1175 reg |= CPSW_SL_MACTL_GMII_ENABLE; 1176 cpsw_write_4(sc->swsc, CPSW_SL_MACCONTROL(sc->unit), reg); 1177 1178 /* Initialize ALE: set port to forwarding, initialize addrs */ 1179 cpsw_write_4(sc->swsc, CPSW_ALE_PORTCTL(sc->unit + 1), 1180 ALE_PORTCTL_INGRESS | ALE_PORTCTL_FORWARD); 1181 cpswp_ale_update_addresses(sc, 1); 1182 1183 if (sc->swsc->dualemac) { 1184 /* Set Port VID. */ 1185 cpsw_write_4(sc->swsc, CPSW_PORT_P_VLAN(sc->unit + 1), 1186 sc->vlan & 0xfff); 1187 cpsw_ale_update_vlan_table(sc->swsc, sc->vlan, 1188 (1 << (sc->unit + 1)) | (1 << 0), /* Member list */ 1189 (1 << (sc->unit + 1)) | (1 << 0), /* Untagged egress */ 1190 (1 << (sc->unit + 1)) | (1 << 0), 0); /* mcast reg flood */ 1191#ifdef CPSW_ETHERSWITCH 1192 for (i = 0; i < CPSW_VLANS; i++) { 1193 if (cpsw_vgroups[i].vid != -1) 1194 continue; 1195 cpsw_vgroups[i].vid = sc->vlan; 1196 break; 1197 } 1198#endif 1199 } 1200 1201 mii_mediachg(sc->mii); 1202 callout_reset(&sc->mii_callout, hz, cpswp_tick, sc); 1203 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1204 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1205} 1206 1207static int 1208cpsw_shutdown(device_t dev) 1209{ 1210 struct cpsw_softc *sc; 1211 struct cpswp_softc *psc; 1212 int i; 1213 1214 sc = device_get_softc(dev); 1215 CPSW_DEBUGF(sc, ("")); 1216 for (i = 0; i < CPSW_PORTS; i++) { 1217 if (!sc->dualemac && i != sc->active_slave) 1218 continue; 1219 psc = device_get_softc(sc->port[i].dev); 1220 CPSW_PORT_LOCK(psc); 1221 cpswp_stop_locked(psc); 1222 CPSW_PORT_UNLOCK(psc); 1223 } 1224 1225 return (0); 1226} 1227 1228static void 1229cpsw_rx_teardown(struct cpsw_softc *sc) 1230{ 1231 int i = 0; 1232 1233 CPSW_RX_LOCK(sc); 1234 CPSW_DEBUGF(sc, ("starting RX teardown")); 1235 sc->rx.teardown = 1; 1236 cpsw_write_4(sc, CPSW_CPDMA_RX_TEARDOWN, 0); 1237 CPSW_RX_UNLOCK(sc); 1238 while (sc->rx.running) { 1239 if (++i > 10) { 1240 device_printf(sc->dev, 1241 "Unable to cleanly shutdown receiver\n"); 1242 return; 1243 } 1244 DELAY(200); 1245 } 1246 if (!sc->rx.running) 1247 CPSW_DEBUGF(sc, ("finished RX teardown (%d retries)", i)); 1248} 1249 1250static void 1251cpsw_tx_teardown(struct cpsw_softc *sc) 1252{ 1253 int i = 0; 1254 1255 CPSW_TX_LOCK(sc); 1256 CPSW_DEBUGF(sc, ("starting TX teardown")); 1257 /* Start the TX queue teardown if queue is not empty. */ 1258 if (STAILQ_FIRST(&sc->tx.active) != NULL) 1259 cpsw_write_4(sc, CPSW_CPDMA_TX_TEARDOWN, 0); 1260 else 1261 sc->tx.teardown = 1; 1262 cpsw_tx_dequeue(sc); 1263 while (sc->tx.running && ++i < 10) { 1264 DELAY(200); 1265 cpsw_tx_dequeue(sc); 1266 } 1267 if (sc->tx.running) { 1268 device_printf(sc->dev, 1269 "Unable to cleanly shutdown transmitter\n"); 1270 } 1271 CPSW_DEBUGF(sc, 1272 ("finished TX teardown (%d retries, %d idle buffers)", i, 1273 sc->tx.active_queue_len)); 1274 CPSW_TX_UNLOCK(sc); 1275} 1276 1277static void 1278cpswp_stop_locked(struct cpswp_softc *sc) 1279{ 1280 struct ifnet *ifp; 1281 uint32_t reg; 1282 1283 ifp = sc->ifp; 1284 CPSW_DEBUGF(sc->swsc, ("")); 1285 CPSW_PORT_LOCK_ASSERT(sc); 1286 1287 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 1288 return; 1289 1290 /* Disable interface */ 1291 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1292 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1293 1294 /* Stop ticker */ 1295 callout_stop(&sc->mii_callout); 1296 1297 /* Tear down the RX/TX queues. */ 1298 if (cpsw_ports_down(sc->swsc)) { 1299 cpsw_rx_teardown(sc->swsc); 1300 cpsw_tx_teardown(sc->swsc); 1301 } 1302 1303 /* Stop MAC RX/TX modules. */ 1304 reg = cpsw_read_4(sc->swsc, CPSW_SL_MACCONTROL(sc->unit)); 1305 reg &= ~CPSW_SL_MACTL_GMII_ENABLE; 1306 cpsw_write_4(sc->swsc, CPSW_SL_MACCONTROL(sc->unit), reg); 1307 1308 if (cpsw_ports_down(sc->swsc)) { 1309 /* Capture stats before we reset controller. */ 1310 cpsw_stats_collect(sc->swsc); 1311 1312 cpsw_reset(sc->swsc); 1313 cpsw_init(sc->swsc); 1314 } 1315} 1316 1317/* 1318 * Suspend/Resume. 1319 */ 1320 1321static int 1322cpsw_suspend(device_t dev) 1323{ 1324 struct cpsw_softc *sc; 1325 struct cpswp_softc *psc; 1326 int i; 1327 1328 sc = device_get_softc(dev); 1329 CPSW_DEBUGF(sc, ("")); 1330 for (i = 0; i < CPSW_PORTS; i++) { 1331 if (!sc->dualemac && i != sc->active_slave) 1332 continue; 1333 psc = device_get_softc(sc->port[i].dev); 1334 CPSW_PORT_LOCK(psc); 1335 cpswp_stop_locked(psc); 1336 CPSW_PORT_UNLOCK(psc); 1337 } 1338 1339 return (0); 1340} 1341 1342static int 1343cpsw_resume(device_t dev) 1344{ 1345 struct cpsw_softc *sc; 1346 1347 sc = device_get_softc(dev); 1348 CPSW_DEBUGF(sc, ("UNIMPLEMENTED")); 1349 1350 return (0); 1351} 1352 1353/* 1354 * 1355 * IOCTL 1356 * 1357 */ 1358 1359static void 1360cpsw_set_promisc(struct cpswp_softc *sc, int set) 1361{ 1362 uint32_t reg; 1363 1364 /* 1365 * Enabling promiscuous mode requires ALE_BYPASS to be enabled. 1366 * That disables the ALE forwarding logic and causes every 1367 * packet to be sent only to the host port. In bypass mode, 1368 * the ALE processes host port transmit packets the same as in 1369 * normal mode. 1370 */ 1371 reg = cpsw_read_4(sc->swsc, CPSW_ALE_CONTROL); 1372 reg &= ~CPSW_ALE_CTL_BYPASS; 1373 if (set) 1374 reg |= CPSW_ALE_CTL_BYPASS; 1375 cpsw_write_4(sc->swsc, CPSW_ALE_CONTROL, reg); 1376} 1377 1378static void 1379cpsw_set_allmulti(struct cpswp_softc *sc, int set) 1380{ 1381 if (set) { 1382 printf("All-multicast mode unimplemented\n"); 1383 } 1384} 1385 1386static int 1387cpswp_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1388{ 1389 struct cpswp_softc *sc; 1390 struct ifreq *ifr; 1391 int error; 1392 uint32_t changed; 1393 1394 error = 0; 1395 sc = ifp->if_softc; 1396 ifr = (struct ifreq *)data; 1397 1398 switch (command) { 1399 case SIOCSIFFLAGS: 1400 CPSW_PORT_LOCK(sc); 1401 if (ifp->if_flags & IFF_UP) { 1402 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1403 changed = ifp->if_flags ^ sc->if_flags; 1404 CPSW_DEBUGF(sc->swsc, 1405 ("SIOCSIFFLAGS: UP & RUNNING (changed=0x%x)", 1406 changed)); 1407 if (changed & IFF_PROMISC) 1408 cpsw_set_promisc(sc, 1409 ifp->if_flags & IFF_PROMISC); 1410 if (changed & IFF_ALLMULTI) 1411 cpsw_set_allmulti(sc, 1412 ifp->if_flags & IFF_ALLMULTI); 1413 } else { 1414 CPSW_DEBUGF(sc->swsc, 1415 ("SIOCSIFFLAGS: starting up")); 1416 cpswp_init_locked(sc); 1417 } 1418 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1419 CPSW_DEBUGF(sc->swsc, ("SIOCSIFFLAGS: shutting down")); 1420 cpswp_stop_locked(sc); 1421 } 1422 1423 sc->if_flags = ifp->if_flags; 1424 CPSW_PORT_UNLOCK(sc); 1425 break; 1426 case SIOCADDMULTI: 1427 cpswp_ale_update_addresses(sc, 0); 1428 break; 1429 case SIOCDELMULTI: 1430 /* Ugh. DELMULTI doesn't provide the specific address 1431 being removed, so the best we can do is remove 1432 everything and rebuild it all. */ 1433 cpswp_ale_update_addresses(sc, 1); 1434 break; 1435 case SIOCGIFMEDIA: 1436 case SIOCSIFMEDIA: 1437 error = ifmedia_ioctl(ifp, ifr, &sc->mii->mii_media, command); 1438 break; 1439 default: 1440 error = ether_ioctl(ifp, command, data); 1441 } 1442 return (error); 1443} 1444 1445/* 1446 * 1447 * MIIBUS 1448 * 1449 */ 1450static int 1451cpswp_miibus_ready(struct cpsw_softc *sc, uint32_t reg) 1452{ 1453 uint32_t r, retries = CPSW_MIIBUS_RETRIES; 1454 1455 while (--retries) { 1456 r = cpsw_read_4(sc, reg); 1457 if ((r & MDIO_PHYACCESS_GO) == 0) 1458 return (1); 1459 DELAY(CPSW_MIIBUS_DELAY); 1460 } 1461 1462 return (0); 1463} 1464 1465static int 1466cpswp_miibus_readreg(device_t dev, int phy, int reg) 1467{ 1468 struct cpswp_softc *sc; 1469 uint32_t cmd, r; 1470 1471 sc = device_get_softc(dev); 1472 if (!cpswp_miibus_ready(sc->swsc, sc->phyaccess)) { 1473 device_printf(dev, "MDIO not ready to read\n"); 1474 return (0); 1475 } 1476 1477 /* Set GO, reg, phy */ 1478 cmd = MDIO_PHYACCESS_GO | (reg & 0x1F) << 21 | (phy & 0x1F) << 16; 1479 cpsw_write_4(sc->swsc, sc->phyaccess, cmd); 1480 1481 if (!cpswp_miibus_ready(sc->swsc, sc->phyaccess)) { 1482 device_printf(dev, "MDIO timed out during read\n"); 1483 return (0); 1484 } 1485 1486 r = cpsw_read_4(sc->swsc, sc->phyaccess); 1487 if ((r & MDIO_PHYACCESS_ACK) == 0) { 1488 device_printf(dev, "Failed to read from PHY.\n"); 1489 r = 0; 1490 } 1491 return (r & 0xFFFF); 1492} 1493 1494static int 1495cpswp_miibus_writereg(device_t dev, int phy, int reg, int value) 1496{ 1497 struct cpswp_softc *sc; 1498 uint32_t cmd; 1499 1500 sc = device_get_softc(dev); 1501 if (!cpswp_miibus_ready(sc->swsc, sc->phyaccess)) { 1502 device_printf(dev, "MDIO not ready to write\n"); 1503 return (0); 1504 } 1505 1506 /* Set GO, WRITE, reg, phy, and value */ 1507 cmd = MDIO_PHYACCESS_GO | MDIO_PHYACCESS_WRITE | 1508 (reg & 0x1F) << 21 | (phy & 0x1F) << 16 | (value & 0xFFFF); 1509 cpsw_write_4(sc->swsc, sc->phyaccess, cmd); 1510 1511 if (!cpswp_miibus_ready(sc->swsc, sc->phyaccess)) { 1512 device_printf(dev, "MDIO timed out during write\n"); 1513 return (0); 1514 } 1515 1516 return (0); 1517} 1518 1519static void 1520cpswp_miibus_statchg(device_t dev) 1521{ 1522 struct cpswp_softc *sc; 1523 uint32_t mac_control, reg; 1524 1525 sc = device_get_softc(dev); 1526 CPSW_DEBUGF(sc->swsc, ("")); 1527 1528 reg = CPSW_SL_MACCONTROL(sc->unit); 1529 mac_control = cpsw_read_4(sc->swsc, reg); 1530 mac_control &= ~(CPSW_SL_MACTL_GIG | CPSW_SL_MACTL_IFCTL_A | 1531 CPSW_SL_MACTL_IFCTL_B | CPSW_SL_MACTL_FULLDUPLEX); 1532 1533 switch(IFM_SUBTYPE(sc->mii->mii_media_active)) { 1534 case IFM_1000_SX: 1535 case IFM_1000_LX: 1536 case IFM_1000_CX: 1537 case IFM_1000_T: 1538 mac_control |= CPSW_SL_MACTL_GIG; 1539 break; 1540 1541 case IFM_100_TX: 1542 mac_control |= CPSW_SL_MACTL_IFCTL_A; 1543 break; 1544 } 1545 if (sc->mii->mii_media_active & IFM_FDX) 1546 mac_control |= CPSW_SL_MACTL_FULLDUPLEX; 1547 1548 cpsw_write_4(sc->swsc, reg, mac_control); 1549} 1550 1551/* 1552 * 1553 * Transmit/Receive Packets. 1554 * 1555 */ 1556static void 1557cpsw_intr_rx(void *arg) 1558{ 1559 struct cpsw_softc *sc; 1560 struct ifnet *ifp; 1561 struct mbuf *received, *next; 1562 1563 sc = (struct cpsw_softc *)arg; 1564 CPSW_RX_LOCK(sc); 1565 if (sc->rx.teardown) { 1566 sc->rx.running = 0; 1567 sc->rx.teardown = 0; 1568 cpsw_write_cp(sc, &sc->rx, 0xfffffffc); 1569 } 1570 received = cpsw_rx_dequeue(sc); 1571 cpsw_rx_enqueue(sc); 1572 cpsw_write_4(sc, CPSW_CPDMA_CPDMA_EOI_VECTOR, 1); 1573 CPSW_RX_UNLOCK(sc); 1574 1575 while (received != NULL) { 1576 next = received->m_nextpkt; 1577 received->m_nextpkt = NULL; 1578 ifp = received->m_pkthdr.rcvif; 1579 (*ifp->if_input)(ifp, received); 1580 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 1581 received = next; 1582 } 1583} 1584 1585static struct mbuf * 1586cpsw_rx_dequeue(struct cpsw_softc *sc) 1587{ 1588 struct cpsw_cpdma_bd bd; 1589 struct cpsw_slot *last, *slot; 1590 struct cpswp_softc *psc; 1591 struct mbuf *mb_head, *mb_tail; 1592 int port, removed = 0; 1593 1594 last = NULL; 1595 mb_head = mb_tail = NULL; 1596 1597 /* Pull completed packets off hardware RX queue. */ 1598 while ((slot = STAILQ_FIRST(&sc->rx.active)) != NULL) { 1599 cpsw_cpdma_read_bd(sc, slot, &bd); 1600 1601 /* 1602 * Stop on packets still in use by hardware, but do not stop 1603 * on packets with the teardown complete flag, they will be 1604 * discarded later. 1605 */ 1606 if ((bd.flags & (CPDMA_BD_OWNER | CPDMA_BD_TDOWNCMPLT)) == 1607 CPDMA_BD_OWNER) 1608 break; 1609 1610 last = slot; 1611 ++removed; 1612 STAILQ_REMOVE_HEAD(&sc->rx.active, next); 1613 STAILQ_INSERT_TAIL(&sc->rx.avail, slot, next); 1614 1615 bus_dmamap_sync(sc->mbuf_dtag, slot->dmamap, BUS_DMASYNC_POSTREAD); 1616 bus_dmamap_unload(sc->mbuf_dtag, slot->dmamap); 1617 1618 if (bd.flags & CPDMA_BD_TDOWNCMPLT) { 1619 CPSW_DEBUGF(sc, ("RX teardown is complete")); 1620 m_freem(slot->mbuf); 1621 slot->mbuf = NULL; 1622 sc->rx.running = 0; 1623 sc->rx.teardown = 0; 1624 break; 1625 } 1626 1627 port = (bd.flags & CPDMA_BD_PORT_MASK) - 1; 1628 KASSERT(port >= 0 && port <= 1, 1629 ("patcket received with invalid port: %d", port)); 1630 psc = device_get_softc(sc->port[port].dev); 1631 1632 /* Set up mbuf */ 1633 /* TODO: track SOP/EOP bits to assemble a full mbuf 1634 out of received fragments. */ 1635 slot->mbuf->m_data += bd.bufoff; 1636 slot->mbuf->m_len = bd.pktlen - 4; 1637 slot->mbuf->m_pkthdr.len = bd.pktlen - 4; 1638 slot->mbuf->m_flags |= M_PKTHDR; 1639 slot->mbuf->m_pkthdr.rcvif = psc->ifp; 1640 slot->mbuf->m_nextpkt = NULL; 1641 1642 if ((psc->ifp->if_capenable & IFCAP_RXCSUM) != 0) { 1643 /* check for valid CRC by looking into pkt_err[5:4] */ 1644 if ((bd.flags & CPDMA_BD_PKT_ERR_MASK) == 0) { 1645 slot->mbuf->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1646 slot->mbuf->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1647 slot->mbuf->m_pkthdr.csum_data = 0xffff; 1648 } 1649 } 1650 1651 /* Add mbuf to packet list to be returned. */ 1652 if (mb_tail) { 1653 mb_tail->m_nextpkt = slot->mbuf; 1654 } else { 1655 mb_head = slot->mbuf; 1656 } 1657 mb_tail = slot->mbuf; 1658 slot->mbuf = NULL; 1659 if (sc->rx_batch > 0 && sc->rx_batch == removed) 1660 break; 1661 } 1662 1663 if (removed != 0) { 1664 cpsw_write_cp_slot(sc, &sc->rx, last); 1665 sc->rx.queue_removes += removed; 1666 sc->rx.avail_queue_len += removed; 1667 sc->rx.active_queue_len -= removed; 1668 if (sc->rx.avail_queue_len > sc->rx.max_avail_queue_len) 1669 sc->rx.max_avail_queue_len = sc->rx.avail_queue_len; 1670 CPSW_DEBUGF(sc, ("Removed %d received packet(s) from RX queue", removed)); 1671 } 1672 1673 return (mb_head); 1674} 1675 1676static void 1677cpsw_rx_enqueue(struct cpsw_softc *sc) 1678{ 1679 bus_dma_segment_t seg[1]; 1680 struct cpsw_cpdma_bd bd; 1681 struct cpsw_slot *first_new_slot, *last_old_slot, *next, *slot; 1682 int error, nsegs, added = 0; 1683 uint32_t flags; 1684 1685 /* Register new mbufs with hardware. */ 1686 first_new_slot = NULL; 1687 last_old_slot = STAILQ_LAST(&sc->rx.active, cpsw_slot, next); 1688 while ((slot = STAILQ_FIRST(&sc->rx.avail)) != NULL) { 1689 if (first_new_slot == NULL) 1690 first_new_slot = slot; 1691 if (slot->mbuf == NULL) { 1692 slot->mbuf = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1693 if (slot->mbuf == NULL) { 1694 device_printf(sc->dev, 1695 "Unable to fill RX queue\n"); 1696 break; 1697 } 1698 slot->mbuf->m_len = 1699 slot->mbuf->m_pkthdr.len = 1700 slot->mbuf->m_ext.ext_size; 1701 } 1702 1703 error = bus_dmamap_load_mbuf_sg(sc->mbuf_dtag, slot->dmamap, 1704 slot->mbuf, seg, &nsegs, BUS_DMA_NOWAIT); 1705 1706 KASSERT(nsegs == 1, ("More than one segment (nsegs=%d)", nsegs)); 1707 KASSERT(error == 0, ("DMA error (error=%d)", error)); 1708 if (error != 0 || nsegs != 1) { 1709 device_printf(sc->dev, 1710 "%s: Can't prep RX buf for DMA (nsegs=%d, error=%d)\n", 1711 __func__, nsegs, error); 1712 bus_dmamap_unload(sc->mbuf_dtag, slot->dmamap); 1713 m_freem(slot->mbuf); 1714 slot->mbuf = NULL; 1715 break; 1716 } 1717 1718 bus_dmamap_sync(sc->mbuf_dtag, slot->dmamap, BUS_DMASYNC_PREREAD); 1719 1720 /* Create and submit new rx descriptor. */ 1721 if ((next = STAILQ_NEXT(slot, next)) != NULL) 1722 bd.next = cpsw_cpdma_bd_paddr(sc, next); 1723 else 1724 bd.next = 0; 1725 bd.bufptr = seg->ds_addr; 1726 bd.bufoff = 0; 1727 bd.buflen = MCLBYTES - 1; 1728 bd.pktlen = bd.buflen; 1729 bd.flags = CPDMA_BD_OWNER; 1730 cpsw_cpdma_write_bd(sc, slot, &bd); 1731 ++added; 1732 1733 STAILQ_REMOVE_HEAD(&sc->rx.avail, next); 1734 STAILQ_INSERT_TAIL(&sc->rx.active, slot, next); 1735 } 1736 1737 if (added == 0 || first_new_slot == NULL) 1738 return; 1739 1740 CPSW_DEBUGF(sc, ("Adding %d buffers to RX queue", added)); 1741 1742 /* Link new entries to hardware RX queue. */ 1743 if (last_old_slot == NULL) { 1744 /* Start a fresh queue. */ 1745 cpsw_write_hdp_slot(sc, &sc->rx, first_new_slot); 1746 } else { 1747 /* Add buffers to end of current queue. */ 1748 cpsw_cpdma_write_bd_next(sc, last_old_slot, first_new_slot); 1749 /* If underrun, restart queue. */ 1750 if ((flags = cpsw_cpdma_read_bd_flags(sc, last_old_slot)) & 1751 CPDMA_BD_EOQ) { 1752 flags &= ~CPDMA_BD_EOQ; 1753 cpsw_cpdma_write_bd_flags(sc, last_old_slot, flags); 1754 cpsw_write_hdp_slot(sc, &sc->rx, first_new_slot); 1755 sc->rx.queue_restart++; 1756 } 1757 } 1758 sc->rx.queue_adds += added; 1759 sc->rx.avail_queue_len -= added; 1760 sc->rx.active_queue_len += added; 1761 cpsw_write_4(sc, CPSW_CPDMA_RX_FREEBUFFER(0), added); 1762 if (sc->rx.active_queue_len > sc->rx.max_active_queue_len) { 1763 sc->rx.max_active_queue_len = sc->rx.active_queue_len; 1764 } 1765} 1766 1767static void 1768cpswp_start(struct ifnet *ifp) 1769{ 1770 struct cpswp_softc *sc; 1771 1772 sc = ifp->if_softc; 1773 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || 1774 sc->swsc->tx.running == 0) { 1775 return; 1776 } 1777 CPSW_TX_LOCK(sc->swsc); 1778 cpswp_tx_enqueue(sc); 1779 cpsw_tx_dequeue(sc->swsc); 1780 CPSW_TX_UNLOCK(sc->swsc); 1781} 1782 1783static void 1784cpsw_intr_tx(void *arg) 1785{ 1786 struct cpsw_softc *sc; 1787 1788 sc = (struct cpsw_softc *)arg; 1789 CPSW_TX_LOCK(sc); 1790 if (cpsw_read_4(sc, CPSW_CPDMA_TX_CP(0)) == 0xfffffffc) 1791 cpsw_write_cp(sc, &sc->tx, 0xfffffffc); 1792 cpsw_tx_dequeue(sc); 1793 cpsw_write_4(sc, CPSW_CPDMA_CPDMA_EOI_VECTOR, 2); 1794 CPSW_TX_UNLOCK(sc); 1795} 1796 1797static void 1798cpswp_tx_enqueue(struct cpswp_softc *sc) 1799{ 1800 bus_dma_segment_t segs[CPSW_TXFRAGS]; 1801 struct cpsw_cpdma_bd bd; 1802 struct cpsw_slot *first_new_slot, *last, *last_old_slot, *next, *slot; 1803 struct mbuf *m0; 1804 int error, nsegs, seg, added = 0, padlen; 1805 1806 /* Pull pending packets from IF queue and prep them for DMA. */ 1807 last = NULL; 1808 first_new_slot = NULL; 1809 last_old_slot = STAILQ_LAST(&sc->swsc->tx.active, cpsw_slot, next); 1810 while ((slot = STAILQ_FIRST(&sc->swsc->tx.avail)) != NULL) { 1811 IF_DEQUEUE(&sc->ifp->if_snd, m0); 1812 if (m0 == NULL) 1813 break; 1814 1815 slot->mbuf = m0; 1816 padlen = ETHER_MIN_LEN - slot->mbuf->m_pkthdr.len; 1817 if (padlen < 0) 1818 padlen = 0; 1819 1820 /* Create mapping in DMA memory */ 1821 error = bus_dmamap_load_mbuf_sg(sc->swsc->mbuf_dtag, 1822 slot->dmamap, slot->mbuf, segs, &nsegs, BUS_DMA_NOWAIT); 1823 /* If the packet is too fragmented, try to simplify. */ 1824 if (error == EFBIG || 1825 (error == 0 && 1826 nsegs + (padlen > 0 ? 1 : 0) > sc->swsc->tx.avail_queue_len)) { 1827 bus_dmamap_unload(sc->swsc->mbuf_dtag, slot->dmamap); 1828 if (padlen > 0) /* May as well add padding. */ 1829 m_append(slot->mbuf, padlen, 1830 sc->swsc->null_mbuf->m_data); 1831 m0 = m_defrag(slot->mbuf, M_NOWAIT); 1832 if (m0 == NULL) { 1833 device_printf(sc->dev, 1834 "Can't defragment packet; dropping\n"); 1835 m_freem(slot->mbuf); 1836 } else { 1837 CPSW_DEBUGF(sc->swsc, 1838 ("Requeueing defragmented packet")); 1839 IF_PREPEND(&sc->ifp->if_snd, m0); 1840 } 1841 slot->mbuf = NULL; 1842 continue; 1843 } 1844 if (error != 0) { 1845 device_printf(sc->dev, 1846 "%s: Can't setup DMA (error=%d), dropping packet\n", 1847 __func__, error); 1848 bus_dmamap_unload(sc->swsc->mbuf_dtag, slot->dmamap); 1849 m_freem(slot->mbuf); 1850 slot->mbuf = NULL; 1851 break; 1852 } 1853 1854 bus_dmamap_sync(sc->swsc->mbuf_dtag, slot->dmamap, 1855 BUS_DMASYNC_PREWRITE); 1856 1857 CPSW_DEBUGF(sc->swsc, 1858 ("Queueing TX packet: %d segments + %d pad bytes", 1859 nsegs, padlen)); 1860 1861 if (first_new_slot == NULL) 1862 first_new_slot = slot; 1863 1864 /* Link from the previous descriptor. */ 1865 if (last != NULL) 1866 cpsw_cpdma_write_bd_next(sc->swsc, last, slot); 1867 1868 slot->ifp = sc->ifp; 1869 1870 /* If there is only one segment, the for() loop 1871 * gets skipped and the single buffer gets set up 1872 * as both SOP and EOP. */ 1873 if (nsegs > 1) { 1874 next = STAILQ_NEXT(slot, next); 1875 bd.next = cpsw_cpdma_bd_paddr(sc->swsc, next); 1876 } else 1877 bd.next = 0; 1878 /* Start by setting up the first buffer. */ 1879 bd.bufptr = segs[0].ds_addr; 1880 bd.bufoff = 0; 1881 bd.buflen = segs[0].ds_len; 1882 bd.pktlen = m_length(slot->mbuf, NULL) + padlen; 1883 bd.flags = CPDMA_BD_SOP | CPDMA_BD_OWNER; 1884 if (sc->swsc->dualemac) { 1885 bd.flags |= CPDMA_BD_TO_PORT; 1886 bd.flags |= ((sc->unit + 1) & CPDMA_BD_PORT_MASK); 1887 } 1888 for (seg = 1; seg < nsegs; ++seg) { 1889 /* Save the previous buffer (which isn't EOP) */ 1890 cpsw_cpdma_write_bd(sc->swsc, slot, &bd); 1891 STAILQ_REMOVE_HEAD(&sc->swsc->tx.avail, next); 1892 STAILQ_INSERT_TAIL(&sc->swsc->tx.active, slot, next); 1893 slot = STAILQ_FIRST(&sc->swsc->tx.avail); 1894 1895 /* Setup next buffer (which isn't SOP) */ 1896 if (nsegs > seg + 1) { 1897 next = STAILQ_NEXT(slot, next); 1898 bd.next = cpsw_cpdma_bd_paddr(sc->swsc, next); 1899 } else 1900 bd.next = 0; 1901 bd.bufptr = segs[seg].ds_addr; 1902 bd.bufoff = 0; 1903 bd.buflen = segs[seg].ds_len; 1904 bd.pktlen = 0; 1905 bd.flags = CPDMA_BD_OWNER; 1906 } 1907 /* Save the final buffer. */ 1908 if (padlen <= 0) 1909 bd.flags |= CPDMA_BD_EOP; 1910 else { 1911 next = STAILQ_NEXT(slot, next); 1912 bd.next = cpsw_cpdma_bd_paddr(sc->swsc, next); 1913 } 1914 cpsw_cpdma_write_bd(sc->swsc, slot, &bd); 1915 STAILQ_REMOVE_HEAD(&sc->swsc->tx.avail, next); 1916 STAILQ_INSERT_TAIL(&sc->swsc->tx.active, slot, next); 1917 1918 if (padlen > 0) { 1919 slot = STAILQ_FIRST(&sc->swsc->tx.avail); 1920 1921 /* Setup buffer of null pad bytes (definitely EOP). */ 1922 bd.next = 0; 1923 bd.bufptr = sc->swsc->null_mbuf_paddr; 1924 bd.bufoff = 0; 1925 bd.buflen = padlen; 1926 bd.pktlen = 0; 1927 bd.flags = CPDMA_BD_EOP | CPDMA_BD_OWNER; 1928 cpsw_cpdma_write_bd(sc->swsc, slot, &bd); 1929 ++nsegs; 1930 1931 STAILQ_REMOVE_HEAD(&sc->swsc->tx.avail, next); 1932 STAILQ_INSERT_TAIL(&sc->swsc->tx.active, slot, next); 1933 } 1934 1935 last = slot; 1936 1937 added += nsegs; 1938 if (nsegs > sc->swsc->tx.longest_chain) 1939 sc->swsc->tx.longest_chain = nsegs; 1940 1941 // TODO: Should we defer the BPF tap until 1942 // after all packets are queued? 1943 BPF_MTAP(sc->ifp, m0); 1944 } 1945 1946 if (first_new_slot == NULL) 1947 return; 1948 1949 /* Attach the list of new buffers to the hardware TX queue. */ 1950 if (last_old_slot != NULL && 1951 (cpsw_cpdma_read_bd_flags(sc->swsc, last_old_slot) & 1952 CPDMA_BD_EOQ) == 0) { 1953 /* Add buffers to end of current queue. */ 1954 cpsw_cpdma_write_bd_next(sc->swsc, last_old_slot, 1955 first_new_slot); 1956 } else { 1957 /* Start a fresh queue. */ 1958 cpsw_write_hdp_slot(sc->swsc, &sc->swsc->tx, first_new_slot); 1959 } 1960 sc->swsc->tx.queue_adds += added; 1961 sc->swsc->tx.avail_queue_len -= added; 1962 sc->swsc->tx.active_queue_len += added; 1963 if (sc->swsc->tx.active_queue_len > sc->swsc->tx.max_active_queue_len) { 1964 sc->swsc->tx.max_active_queue_len = sc->swsc->tx.active_queue_len; 1965 } 1966 CPSW_DEBUGF(sc->swsc, ("Queued %d TX packet(s)", added)); 1967} 1968 1969static int 1970cpsw_tx_dequeue(struct cpsw_softc *sc) 1971{ 1972 struct cpsw_slot *slot, *last_removed_slot = NULL; 1973 struct cpsw_cpdma_bd bd; 1974 uint32_t flags, removed = 0; 1975 1976 /* Pull completed buffers off the hardware TX queue. */ 1977 slot = STAILQ_FIRST(&sc->tx.active); 1978 while (slot != NULL) { 1979 flags = cpsw_cpdma_read_bd_flags(sc, slot); 1980 1981 /* TearDown complete is only marked on the SOP for the packet. */ 1982 if ((flags & (CPDMA_BD_SOP | CPDMA_BD_TDOWNCMPLT)) == 1983 (CPDMA_BD_SOP | CPDMA_BD_TDOWNCMPLT)) { 1984 sc->tx.teardown = 1; 1985 } 1986 1987 if ((flags & CPDMA_BD_OWNER) != 0 && sc->tx.teardown == 0) 1988 break; /* Hardware is still using this packet. */ 1989 1990 bus_dmamap_sync(sc->mbuf_dtag, slot->dmamap, BUS_DMASYNC_POSTWRITE); 1991 bus_dmamap_unload(sc->mbuf_dtag, slot->dmamap); 1992 m_freem(slot->mbuf); 1993 slot->mbuf = NULL; 1994 1995 if (slot->ifp) { 1996 if (sc->tx.teardown == 0) 1997 if_inc_counter(slot->ifp, IFCOUNTER_OPACKETS, 1); 1998 else 1999 if_inc_counter(slot->ifp, IFCOUNTER_OQDROPS, 1); 2000 } 2001 2002 /* Dequeue any additional buffers used by this packet. */ 2003 while (slot != NULL && slot->mbuf == NULL) { 2004 STAILQ_REMOVE_HEAD(&sc->tx.active, next); 2005 STAILQ_INSERT_TAIL(&sc->tx.avail, slot, next); 2006 ++removed; 2007 last_removed_slot = slot; 2008 slot = STAILQ_FIRST(&sc->tx.active); 2009 } 2010 2011 cpsw_write_cp_slot(sc, &sc->tx, last_removed_slot); 2012 2013 /* Restart the TX queue if necessary. */ 2014 cpsw_cpdma_read_bd(sc, last_removed_slot, &bd); 2015 if (slot != NULL && bd.next != 0 && (bd.flags & 2016 (CPDMA_BD_EOP | CPDMA_BD_OWNER | CPDMA_BD_EOQ)) == 2017 (CPDMA_BD_EOP | CPDMA_BD_EOQ)) { 2018 cpsw_write_hdp_slot(sc, &sc->tx, slot); 2019 sc->tx.queue_restart++; 2020 break; 2021 } 2022 } 2023 2024 if (removed != 0) { 2025 sc->tx.queue_removes += removed; 2026 sc->tx.active_queue_len -= removed; 2027 sc->tx.avail_queue_len += removed; 2028 if (sc->tx.avail_queue_len > sc->tx.max_avail_queue_len) 2029 sc->tx.max_avail_queue_len = sc->tx.avail_queue_len; 2030 CPSW_DEBUGF(sc, ("TX removed %d completed packet(s)", removed)); 2031 } 2032 2033 if (sc->tx.teardown && STAILQ_EMPTY(&sc->tx.active)) { 2034 CPSW_DEBUGF(sc, ("TX teardown is complete")); 2035 sc->tx.teardown = 0; 2036 sc->tx.running = 0; 2037 } 2038 2039 return (removed); 2040} 2041 2042/* 2043 * 2044 * Miscellaneous interrupts. 2045 * 2046 */ 2047 2048static void 2049cpsw_intr_rx_thresh(void *arg) 2050{ 2051 struct cpsw_softc *sc; 2052 struct ifnet *ifp; 2053 struct mbuf *received, *next; 2054 2055 sc = (struct cpsw_softc *)arg; 2056 CPSW_RX_LOCK(sc); 2057 received = cpsw_rx_dequeue(sc); 2058 cpsw_rx_enqueue(sc); 2059 cpsw_write_4(sc, CPSW_CPDMA_CPDMA_EOI_VECTOR, 0); 2060 CPSW_RX_UNLOCK(sc); 2061 2062 while (received != NULL) { 2063 next = received->m_nextpkt; 2064 received->m_nextpkt = NULL; 2065 ifp = received->m_pkthdr.rcvif; 2066 (*ifp->if_input)(ifp, received); 2067 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 2068 received = next; 2069 } 2070} 2071 2072static void 2073cpsw_intr_misc_host_error(struct cpsw_softc *sc) 2074{ 2075 uint32_t intstat; 2076 uint32_t dmastat; 2077 int txerr, rxerr, txchan, rxchan; 2078 2079 printf("\n\n"); 2080 device_printf(sc->dev, 2081 "HOST ERROR: PROGRAMMING ERROR DETECTED BY HARDWARE\n"); 2082 printf("\n\n"); 2083 intstat = cpsw_read_4(sc, CPSW_CPDMA_DMA_INTSTAT_MASKED); 2084 device_printf(sc->dev, "CPSW_CPDMA_DMA_INTSTAT_MASKED=0x%x\n", intstat); 2085 dmastat = cpsw_read_4(sc, CPSW_CPDMA_DMASTATUS); 2086 device_printf(sc->dev, "CPSW_CPDMA_DMASTATUS=0x%x\n", dmastat); 2087 2088 txerr = (dmastat >> 20) & 15; 2089 txchan = (dmastat >> 16) & 7; 2090 rxerr = (dmastat >> 12) & 15; 2091 rxchan = (dmastat >> 8) & 7; 2092 2093 switch (txerr) { 2094 case 0: break; 2095 case 1: printf("SOP error on TX channel %d\n", txchan); 2096 break; 2097 case 2: printf("Ownership bit not set on SOP buffer on TX channel %d\n", txchan); 2098 break; 2099 case 3: printf("Zero Next Buffer but not EOP on TX channel %d\n", txchan); 2100 break; 2101 case 4: printf("Zero Buffer Pointer on TX channel %d\n", txchan); 2102 break; 2103 case 5: printf("Zero Buffer Length on TX channel %d\n", txchan); 2104 break; 2105 case 6: printf("Packet length error on TX channel %d\n", txchan); 2106 break; 2107 default: printf("Unknown error on TX channel %d\n", txchan); 2108 break; 2109 } 2110 2111 if (txerr != 0) { 2112 printf("CPSW_CPDMA_TX%d_HDP=0x%x\n", 2113 txchan, cpsw_read_4(sc, CPSW_CPDMA_TX_HDP(txchan))); 2114 printf("CPSW_CPDMA_TX%d_CP=0x%x\n", 2115 txchan, cpsw_read_4(sc, CPSW_CPDMA_TX_CP(txchan))); 2116 cpsw_dump_queue(sc, &sc->tx.active); 2117 } 2118 2119 switch (rxerr) { 2120 case 0: break; 2121 case 2: printf("Ownership bit not set on RX channel %d\n", rxchan); 2122 break; 2123 case 4: printf("Zero Buffer Pointer on RX channel %d\n", rxchan); 2124 break; 2125 case 5: printf("Zero Buffer Length on RX channel %d\n", rxchan); 2126 break; 2127 case 6: printf("Buffer offset too big on RX channel %d\n", rxchan); 2128 break; 2129 default: printf("Unknown RX error on RX channel %d\n", rxchan); 2130 break; 2131 } 2132 2133 if (rxerr != 0) { 2134 printf("CPSW_CPDMA_RX%d_HDP=0x%x\n", 2135 rxchan, cpsw_read_4(sc,CPSW_CPDMA_RX_HDP(rxchan))); 2136 printf("CPSW_CPDMA_RX%d_CP=0x%x\n", 2137 rxchan, cpsw_read_4(sc, CPSW_CPDMA_RX_CP(rxchan))); 2138 cpsw_dump_queue(sc, &sc->rx.active); 2139 } 2140 2141 printf("\nALE Table\n"); 2142 cpsw_ale_dump_table(sc); 2143 2144 // XXX do something useful here?? 2145 panic("CPSW HOST ERROR INTERRUPT"); 2146 2147 // Suppress this interrupt in the future. 2148 cpsw_write_4(sc, CPSW_CPDMA_DMA_INTMASK_CLEAR, intstat); 2149 printf("XXX HOST ERROR INTERRUPT SUPPRESSED\n"); 2150 // The watchdog will probably reset the controller 2151 // in a little while. It will probably fail again. 2152} 2153 2154static void 2155cpsw_intr_misc(void *arg) 2156{ 2157 struct cpsw_softc *sc = arg; 2158 uint32_t stat = cpsw_read_4(sc, CPSW_WR_C_MISC_STAT(0)); 2159 2160 if (stat & CPSW_WR_C_MISC_EVNT_PEND) 2161 CPSW_DEBUGF(sc, ("Time sync event interrupt unimplemented")); 2162 if (stat & CPSW_WR_C_MISC_STAT_PEND) 2163 cpsw_stats_collect(sc); 2164 if (stat & CPSW_WR_C_MISC_HOST_PEND) 2165 cpsw_intr_misc_host_error(sc); 2166 if (stat & CPSW_WR_C_MISC_MDIOLINK) { 2167 cpsw_write_4(sc, MDIOLINKINTMASKED, 2168 cpsw_read_4(sc, MDIOLINKINTMASKED)); 2169 } 2170 if (stat & CPSW_WR_C_MISC_MDIOUSER) { 2171 CPSW_DEBUGF(sc, 2172 ("MDIO operation completed interrupt unimplemented")); 2173 } 2174 cpsw_write_4(sc, CPSW_CPDMA_CPDMA_EOI_VECTOR, 3); 2175} 2176 2177/* 2178 * 2179 * Periodic Checks and Watchdog. 2180 * 2181 */ 2182 2183static void 2184cpswp_tick(void *msc) 2185{ 2186 struct cpswp_softc *sc = msc; 2187 2188 /* Check for media type change */ 2189 mii_tick(sc->mii); 2190 if (sc->media_status != sc->mii->mii_media.ifm_media) { 2191 printf("%s: media type changed (ifm_media=%x)\n", __func__, 2192 sc->mii->mii_media.ifm_media); 2193 cpswp_ifmedia_upd(sc->ifp); 2194 } 2195 2196 /* Schedule another timeout one second from now */ 2197 callout_reset(&sc->mii_callout, hz, cpswp_tick, sc); 2198} 2199 2200static void 2201cpswp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2202{ 2203 struct cpswp_softc *sc; 2204 struct mii_data *mii; 2205 2206 sc = ifp->if_softc; 2207 CPSW_DEBUGF(sc->swsc, ("")); 2208 CPSW_PORT_LOCK(sc); 2209 2210 mii = sc->mii; 2211 mii_pollstat(mii); 2212 2213 ifmr->ifm_active = mii->mii_media_active; 2214 ifmr->ifm_status = mii->mii_media_status; 2215 CPSW_PORT_UNLOCK(sc); 2216} 2217 2218static int 2219cpswp_ifmedia_upd(struct ifnet *ifp) 2220{ 2221 struct cpswp_softc *sc; 2222 2223 sc = ifp->if_softc; 2224 CPSW_DEBUGF(sc->swsc, ("")); 2225 CPSW_PORT_LOCK(sc); 2226 mii_mediachg(sc->mii); 2227 sc->media_status = sc->mii->mii_media.ifm_media; 2228 CPSW_PORT_UNLOCK(sc); 2229 2230 return (0); 2231} 2232 2233static void 2234cpsw_tx_watchdog_full_reset(struct cpsw_softc *sc) 2235{ 2236 struct cpswp_softc *psc; 2237 int i; 2238 2239 cpsw_debugf_head("CPSW watchdog"); 2240 device_printf(sc->dev, "watchdog timeout\n"); 2241 printf("CPSW_CPDMA_TX%d_HDP=0x%x\n", 0, 2242 cpsw_read_4(sc, CPSW_CPDMA_TX_HDP(0))); 2243 printf("CPSW_CPDMA_TX%d_CP=0x%x\n", 0, 2244 cpsw_read_4(sc, CPSW_CPDMA_TX_CP(0))); 2245 cpsw_dump_queue(sc, &sc->tx.active); 2246 for (i = 0; i < CPSW_PORTS; i++) { 2247 if (!sc->dualemac && i != sc->active_slave) 2248 continue; 2249 psc = device_get_softc(sc->port[i].dev); 2250 CPSW_PORT_LOCK(psc); 2251 cpswp_stop_locked(psc); 2252 CPSW_PORT_UNLOCK(psc); 2253 } 2254} 2255 2256static void 2257cpsw_tx_watchdog(void *msc) 2258{ 2259 struct cpsw_softc *sc; 2260 2261 sc = msc; 2262 CPSW_TX_LOCK(sc); 2263 if (sc->tx.active_queue_len == 0 || !sc->tx.running) { 2264 sc->watchdog.timer = 0; /* Nothing to do. */ 2265 } else if (sc->tx.queue_removes > sc->tx.queue_removes_at_last_tick) { 2266 sc->watchdog.timer = 0; /* Stuff done while we weren't looking. */ 2267 } else if (cpsw_tx_dequeue(sc) > 0) { 2268 sc->watchdog.timer = 0; /* We just did something. */ 2269 } else { 2270 /* There was something to do but it didn't get done. */ 2271 ++sc->watchdog.timer; 2272 if (sc->watchdog.timer > 5) { 2273 sc->watchdog.timer = 0; 2274 ++sc->watchdog.resets; 2275 cpsw_tx_watchdog_full_reset(sc); 2276 } 2277 } 2278 sc->tx.queue_removes_at_last_tick = sc->tx.queue_removes; 2279 CPSW_TX_UNLOCK(sc); 2280 2281 /* Schedule another timeout one second from now */ 2282 callout_reset(&sc->watchdog.callout, hz, cpsw_tx_watchdog, sc); 2283} 2284 2285/* 2286 * 2287 * ALE support routines. 2288 * 2289 */ 2290 2291static void 2292cpsw_ale_read_entry(struct cpsw_softc *sc, uint16_t idx, uint32_t *ale_entry) 2293{ 2294 cpsw_write_4(sc, CPSW_ALE_TBLCTL, idx & 1023); 2295 ale_entry[0] = cpsw_read_4(sc, CPSW_ALE_TBLW0); 2296 ale_entry[1] = cpsw_read_4(sc, CPSW_ALE_TBLW1); 2297 ale_entry[2] = cpsw_read_4(sc, CPSW_ALE_TBLW2); 2298} 2299 2300static void 2301cpsw_ale_write_entry(struct cpsw_softc *sc, uint16_t idx, uint32_t *ale_entry) 2302{ 2303 cpsw_write_4(sc, CPSW_ALE_TBLW0, ale_entry[0]); 2304 cpsw_write_4(sc, CPSW_ALE_TBLW1, ale_entry[1]); 2305 cpsw_write_4(sc, CPSW_ALE_TBLW2, ale_entry[2]); 2306 cpsw_write_4(sc, CPSW_ALE_TBLCTL, 1 << 31 | (idx & 1023)); 2307} 2308 2309static void 2310cpsw_ale_remove_all_mc_entries(struct cpsw_softc *sc) 2311{ 2312 int i; 2313 uint32_t ale_entry[3]; 2314 2315 /* First four entries are link address and broadcast. */ 2316 for (i = 10; i < CPSW_MAX_ALE_ENTRIES; i++) { 2317 cpsw_ale_read_entry(sc, i, ale_entry); 2318 if ((ALE_TYPE(ale_entry) == ALE_TYPE_ADDR || 2319 ALE_TYPE(ale_entry) == ALE_TYPE_VLAN_ADDR) && 2320 ALE_MCAST(ale_entry) == 1) { /* MCast link addr */ 2321 ale_entry[0] = ale_entry[1] = ale_entry[2] = 0; 2322 cpsw_ale_write_entry(sc, i, ale_entry); 2323 } 2324 } 2325} 2326 2327static int 2328cpsw_ale_mc_entry_set(struct cpsw_softc *sc, uint8_t portmap, int vlan, 2329 uint8_t *mac) 2330{ 2331 int free_index = -1, matching_index = -1, i; 2332 uint32_t ale_entry[3], ale_type; 2333 2334 /* Find a matching entry or a free entry. */ 2335 for (i = 10; i < CPSW_MAX_ALE_ENTRIES; i++) { 2336 cpsw_ale_read_entry(sc, i, ale_entry); 2337 2338 /* Entry Type[61:60] is 0 for free entry */ 2339 if (free_index < 0 && ALE_TYPE(ale_entry) == 0) 2340 free_index = i; 2341 2342 if ((((ale_entry[1] >> 8) & 0xFF) == mac[0]) && 2343 (((ale_entry[1] >> 0) & 0xFF) == mac[1]) && 2344 (((ale_entry[0] >>24) & 0xFF) == mac[2]) && 2345 (((ale_entry[0] >>16) & 0xFF) == mac[3]) && 2346 (((ale_entry[0] >> 8) & 0xFF) == mac[4]) && 2347 (((ale_entry[0] >> 0) & 0xFF) == mac[5])) { 2348 matching_index = i; 2349 break; 2350 } 2351 } 2352 2353 if (matching_index < 0) { 2354 if (free_index < 0) 2355 return (ENOMEM); 2356 i = free_index; 2357 } 2358 2359 if (vlan != -1) 2360 ale_type = ALE_TYPE_VLAN_ADDR << 28 | vlan << 16; 2361 else 2362 ale_type = ALE_TYPE_ADDR << 28; 2363 2364 /* Set MAC address */ 2365 ale_entry[0] = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5]; 2366 ale_entry[1] = mac[0] << 8 | mac[1]; 2367 2368 /* Entry type[61:60] and Mcast fwd state[63:62] is fw(3). */ 2369 ale_entry[1] |= ALE_MCAST_FWD | ale_type; 2370 2371 /* Set portmask [68:66] */ 2372 ale_entry[2] = (portmap & 7) << 2; 2373 2374 cpsw_ale_write_entry(sc, i, ale_entry); 2375 2376 return 0; 2377} 2378 2379static void 2380cpsw_ale_dump_table(struct cpsw_softc *sc) { 2381 int i; 2382 uint32_t ale_entry[3]; 2383 for (i = 0; i < CPSW_MAX_ALE_ENTRIES; i++) { 2384 cpsw_ale_read_entry(sc, i, ale_entry); 2385 switch (ALE_TYPE(ale_entry)) { 2386 case ALE_TYPE_VLAN: 2387 printf("ALE[%4u] %08x %08x %08x ", i, ale_entry[2], 2388 ale_entry[1], ale_entry[0]); 2389 printf("type: %u ", ALE_TYPE(ale_entry)); 2390 printf("vlan: %u ", ALE_VLAN(ale_entry)); 2391 printf("untag: %u ", ALE_VLAN_UNTAG(ale_entry)); 2392 printf("reg flood: %u ", ALE_VLAN_REGFLOOD(ale_entry)); 2393 printf("unreg flood: %u ", ALE_VLAN_UNREGFLOOD(ale_entry)); 2394 printf("members: %u ", ALE_VLAN_MEMBERS(ale_entry)); 2395 printf("\n"); 2396 break; 2397 case ALE_TYPE_ADDR: 2398 case ALE_TYPE_VLAN_ADDR: 2399 printf("ALE[%4u] %08x %08x %08x ", i, ale_entry[2], 2400 ale_entry[1], ale_entry[0]); 2401 printf("type: %u ", ALE_TYPE(ale_entry)); 2402 printf("mac: %02x:%02x:%02x:%02x:%02x:%02x ", 2403 (ale_entry[1] >> 8) & 0xFF, 2404 (ale_entry[1] >> 0) & 0xFF, 2405 (ale_entry[0] >>24) & 0xFF, 2406 (ale_entry[0] >>16) & 0xFF, 2407 (ale_entry[0] >> 8) & 0xFF, 2408 (ale_entry[0] >> 0) & 0xFF); 2409 printf(ALE_MCAST(ale_entry) ? "mcast " : "ucast "); 2410 if (ALE_TYPE(ale_entry) == ALE_TYPE_VLAN_ADDR) 2411 printf("vlan: %u ", ALE_VLAN(ale_entry)); 2412 printf("port: %u ", ALE_PORTS(ale_entry)); 2413 printf("\n"); 2414 break; 2415 } 2416 } 2417 printf("\n"); 2418} 2419 2420static int 2421cpswp_ale_update_addresses(struct cpswp_softc *sc, int purge) 2422{ 2423 uint8_t *mac; 2424 uint32_t ale_entry[3], ale_type, portmask; 2425 struct ifmultiaddr *ifma; 2426 2427 if (sc->swsc->dualemac) { 2428 ale_type = ALE_TYPE_VLAN_ADDR << 28 | sc->vlan << 16; 2429 portmask = 1 << (sc->unit + 1) | 1 << 0; 2430 } else { 2431 ale_type = ALE_TYPE_ADDR << 28; 2432 portmask = 7; 2433 } 2434 2435 /* 2436 * Route incoming packets for our MAC address to Port 0 (host). 2437 * For simplicity, keep this entry at table index 0 for port 1 and 2438 * at index 2 for port 2 in the ALE. 2439 */ 2440 if_addr_rlock(sc->ifp); 2441 mac = LLADDR((struct sockaddr_dl *)sc->ifp->if_addr->ifa_addr); 2442 ale_entry[0] = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5]; 2443 ale_entry[1] = ale_type | mac[0] << 8 | mac[1]; /* addr entry + mac */ 2444 ale_entry[2] = 0; /* port = 0 */ 2445 cpsw_ale_write_entry(sc->swsc, 0 + 2 * sc->unit, ale_entry); 2446 2447 /* Set outgoing MAC Address for slave port. */ 2448 cpsw_write_4(sc->swsc, CPSW_PORT_P_SA_HI(sc->unit + 1), 2449 mac[3] << 24 | mac[2] << 16 | mac[1] << 8 | mac[0]); 2450 cpsw_write_4(sc->swsc, CPSW_PORT_P_SA_LO(sc->unit + 1), 2451 mac[5] << 8 | mac[4]); 2452 if_addr_runlock(sc->ifp); 2453 2454 /* Keep the broadcast address at table entry 1 (or 3). */ 2455 ale_entry[0] = 0xffffffff; /* Lower 32 bits of MAC */ 2456 /* ALE_MCAST_FWD, Addr type, upper 16 bits of Mac */ 2457 ale_entry[1] = ALE_MCAST_FWD | ale_type | 0xffff; 2458 ale_entry[2] = portmask << 2; 2459 cpsw_ale_write_entry(sc->swsc, 1 + 2 * sc->unit, ale_entry); 2460 2461 /* SIOCDELMULTI doesn't specify the particular address 2462 being removed, so we have to remove all and rebuild. */ 2463 if (purge) 2464 cpsw_ale_remove_all_mc_entries(sc->swsc); 2465 2466 /* Set other multicast addrs desired. */ 2467 if_maddr_rlock(sc->ifp); 2468 TAILQ_FOREACH(ifma, &sc->ifp->if_multiaddrs, ifma_link) { 2469 if (ifma->ifma_addr->sa_family != AF_LINK) 2470 continue; 2471 cpsw_ale_mc_entry_set(sc->swsc, portmask, sc->vlan, 2472 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 2473 } 2474 if_maddr_runlock(sc->ifp); 2475 2476 return (0); 2477} 2478 2479static int 2480cpsw_ale_update_vlan_table(struct cpsw_softc *sc, int vlan, int ports, 2481 int untag, int mcregflood, int mcunregflood) 2482{ 2483 int free_index, i, matching_index; 2484 uint32_t ale_entry[3]; 2485 2486 free_index = matching_index = -1; 2487 /* Find a matching entry or a free entry. */ 2488 for (i = 5; i < CPSW_MAX_ALE_ENTRIES; i++) { 2489 cpsw_ale_read_entry(sc, i, ale_entry); 2490 2491 /* Entry Type[61:60] is 0 for free entry */ 2492 if (free_index < 0 && ALE_TYPE(ale_entry) == 0) 2493 free_index = i; 2494 2495 if (ALE_VLAN(ale_entry) == vlan) { 2496 matching_index = i; 2497 break; 2498 } 2499 } 2500 2501 if (matching_index < 0) { 2502 if (free_index < 0) 2503 return (-1); 2504 i = free_index; 2505 } 2506 2507 ale_entry[0] = (untag & 7) << 24 | (mcregflood & 7) << 16 | 2508 (mcunregflood & 7) << 8 | (ports & 7); 2509 ale_entry[1] = ALE_TYPE_VLAN << 28 | vlan << 16; 2510 ale_entry[2] = 0; 2511 cpsw_ale_write_entry(sc, i, ale_entry); 2512 2513 return (0); 2514} 2515 2516/* 2517 * 2518 * Statistics and Sysctls. 2519 * 2520 */ 2521 2522#if 0 2523static void 2524cpsw_stats_dump(struct cpsw_softc *sc) 2525{ 2526 int i; 2527 uint32_t r; 2528 2529 for (i = 0; i < CPSW_SYSCTL_COUNT; ++i) { 2530 r = cpsw_read_4(sc, CPSW_STATS_OFFSET + 2531 cpsw_stat_sysctls[i].reg); 2532 CPSW_DEBUGF(sc, ("%s: %ju + %u = %ju", cpsw_stat_sysctls[i].oid, 2533 (intmax_t)sc->shadow_stats[i], r, 2534 (intmax_t)sc->shadow_stats[i] + r)); 2535 } 2536} 2537#endif 2538 2539static void 2540cpsw_stats_collect(struct cpsw_softc *sc) 2541{ 2542 int i; 2543 uint32_t r; 2544 2545 CPSW_DEBUGF(sc, ("Controller shadow statistics updated.")); 2546 2547 for (i = 0; i < CPSW_SYSCTL_COUNT; ++i) { 2548 r = cpsw_read_4(sc, CPSW_STATS_OFFSET + 2549 cpsw_stat_sysctls[i].reg); 2550 sc->shadow_stats[i] += r; 2551 cpsw_write_4(sc, CPSW_STATS_OFFSET + cpsw_stat_sysctls[i].reg, 2552 r); 2553 } 2554} 2555 2556static int 2557cpsw_stats_sysctl(SYSCTL_HANDLER_ARGS) 2558{ 2559 struct cpsw_softc *sc; 2560 struct cpsw_stat *stat; 2561 uint64_t result; 2562 2563 sc = (struct cpsw_softc *)arg1; 2564 stat = &cpsw_stat_sysctls[oidp->oid_number]; 2565 result = sc->shadow_stats[oidp->oid_number]; 2566 result += cpsw_read_4(sc, CPSW_STATS_OFFSET + stat->reg); 2567 return (sysctl_handle_64(oidp, &result, 0, req)); 2568} 2569 2570static int 2571cpsw_stat_attached(SYSCTL_HANDLER_ARGS) 2572{ 2573 struct cpsw_softc *sc; 2574 struct bintime t; 2575 unsigned result; 2576 2577 sc = (struct cpsw_softc *)arg1; 2578 getbinuptime(&t); 2579 bintime_sub(&t, &sc->attach_uptime); 2580 result = t.sec; 2581 return (sysctl_handle_int(oidp, &result, 0, req)); 2582} 2583 2584static int 2585cpsw_intr_coalesce(SYSCTL_HANDLER_ARGS) 2586{ 2587 int error; 2588 struct cpsw_softc *sc; 2589 uint32_t ctrl, intr_per_ms; 2590 2591 sc = (struct cpsw_softc *)arg1; 2592 error = sysctl_handle_int(oidp, &sc->coal_us, 0, req); 2593 if (error != 0 || req->newptr == NULL) 2594 return (error); 2595 2596 ctrl = cpsw_read_4(sc, CPSW_WR_INT_CONTROL); 2597 ctrl &= ~(CPSW_WR_INT_PACE_EN | CPSW_WR_INT_PRESCALE_MASK); 2598 if (sc->coal_us == 0) { 2599 /* Disable the interrupt pace hardware. */ 2600 cpsw_write_4(sc, CPSW_WR_INT_CONTROL, ctrl); 2601 cpsw_write_4(sc, CPSW_WR_C_RX_IMAX(0), 0); 2602 cpsw_write_4(sc, CPSW_WR_C_TX_IMAX(0), 0); 2603 return (0); 2604 } 2605 2606 if (sc->coal_us > CPSW_WR_C_IMAX_US_MAX) 2607 sc->coal_us = CPSW_WR_C_IMAX_US_MAX; 2608 if (sc->coal_us < CPSW_WR_C_IMAX_US_MIN) 2609 sc->coal_us = CPSW_WR_C_IMAX_US_MIN; 2610 intr_per_ms = 1000 / sc->coal_us; 2611 /* Just to make sure... */ 2612 if (intr_per_ms > CPSW_WR_C_IMAX_MAX) 2613 intr_per_ms = CPSW_WR_C_IMAX_MAX; 2614 if (intr_per_ms < CPSW_WR_C_IMAX_MIN) 2615 intr_per_ms = CPSW_WR_C_IMAX_MIN; 2616 2617 /* Set the prescale to produce 4us pulses from the 125 Mhz clock. */ 2618 ctrl |= (125 * 4) & CPSW_WR_INT_PRESCALE_MASK; 2619 2620 /* Enable the interrupt pace hardware. */ 2621 cpsw_write_4(sc, CPSW_WR_C_RX_IMAX(0), intr_per_ms); 2622 cpsw_write_4(sc, CPSW_WR_C_TX_IMAX(0), intr_per_ms); 2623 ctrl |= CPSW_WR_INT_C0_RX_PULSE | CPSW_WR_INT_C0_TX_PULSE; 2624 cpsw_write_4(sc, CPSW_WR_INT_CONTROL, ctrl); 2625 2626 return (0); 2627} 2628 2629static int 2630cpsw_stat_uptime(SYSCTL_HANDLER_ARGS) 2631{ 2632 struct cpsw_softc *swsc; 2633 struct cpswp_softc *sc; 2634 struct bintime t; 2635 unsigned result; 2636 2637 swsc = arg1; 2638 sc = device_get_softc(swsc->port[arg2].dev); 2639 if (sc->ifp->if_drv_flags & IFF_DRV_RUNNING) { 2640 getbinuptime(&t); 2641 bintime_sub(&t, &sc->init_uptime); 2642 result = t.sec; 2643 } else 2644 result = 0; 2645 return (sysctl_handle_int(oidp, &result, 0, req)); 2646} 2647 2648static void 2649cpsw_add_queue_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *node, 2650 struct cpsw_queue *queue) 2651{ 2652 struct sysctl_oid_list *parent; 2653 2654 parent = SYSCTL_CHILDREN(node); 2655 SYSCTL_ADD_INT(ctx, parent, OID_AUTO, "totalBuffers", 2656 CTLFLAG_RD, &queue->queue_slots, 0, 2657 "Total buffers currently assigned to this queue"); 2658 SYSCTL_ADD_INT(ctx, parent, OID_AUTO, "activeBuffers", 2659 CTLFLAG_RD, &queue->active_queue_len, 0, 2660 "Buffers currently registered with hardware controller"); 2661 SYSCTL_ADD_INT(ctx, parent, OID_AUTO, "maxActiveBuffers", 2662 CTLFLAG_RD, &queue->max_active_queue_len, 0, 2663 "Max value of activeBuffers since last driver reset"); 2664 SYSCTL_ADD_INT(ctx, parent, OID_AUTO, "availBuffers", 2665 CTLFLAG_RD, &queue->avail_queue_len, 0, 2666 "Buffers allocated to this queue but not currently " 2667 "registered with hardware controller"); 2668 SYSCTL_ADD_INT(ctx, parent, OID_AUTO, "maxAvailBuffers", 2669 CTLFLAG_RD, &queue->max_avail_queue_len, 0, 2670 "Max value of availBuffers since last driver reset"); 2671 SYSCTL_ADD_UINT(ctx, parent, OID_AUTO, "totalEnqueued", 2672 CTLFLAG_RD, &queue->queue_adds, 0, 2673 "Total buffers added to queue"); 2674 SYSCTL_ADD_UINT(ctx, parent, OID_AUTO, "totalDequeued", 2675 CTLFLAG_RD, &queue->queue_removes, 0, 2676 "Total buffers removed from queue"); 2677 SYSCTL_ADD_UINT(ctx, parent, OID_AUTO, "queueRestart", 2678 CTLFLAG_RD, &queue->queue_restart, 0, 2679 "Total times the queue has been restarted"); 2680 SYSCTL_ADD_UINT(ctx, parent, OID_AUTO, "longestChain", 2681 CTLFLAG_RD, &queue->longest_chain, 0, 2682 "Max buffers used for a single packet"); 2683} 2684 2685static void 2686cpsw_add_watchdog_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *node, 2687 struct cpsw_softc *sc) 2688{ 2689 struct sysctl_oid_list *parent; 2690 2691 parent = SYSCTL_CHILDREN(node); 2692 SYSCTL_ADD_INT(ctx, parent, OID_AUTO, "resets", 2693 CTLFLAG_RD, &sc->watchdog.resets, 0, 2694 "Total number of watchdog resets"); 2695} 2696 2697static void 2698cpsw_add_sysctls(struct cpsw_softc *sc) 2699{ 2700 struct sysctl_ctx_list *ctx; 2701 struct sysctl_oid *stats_node, *queue_node, *node; 2702 struct sysctl_oid_list *parent, *stats_parent, *queue_parent; 2703 struct sysctl_oid_list *ports_parent, *port_parent; 2704 char port[16]; 2705 int i; 2706 2707 ctx = device_get_sysctl_ctx(sc->dev); 2708 parent = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)); 2709 2710 SYSCTL_ADD_INT(ctx, parent, OID_AUTO, "debug", 2711 CTLFLAG_RW, &sc->debug, 0, "Enable switch debug messages"); 2712 2713 SYSCTL_ADD_INT(ctx, parent, OID_AUTO, "rx_batch", 2714 CTLFLAG_RW, &sc->rx_batch, 0, "Set the rx batch size"); 2715 2716 SYSCTL_ADD_PROC(ctx, parent, OID_AUTO, "attachedSecs", 2717 CTLTYPE_UINT | CTLFLAG_RD, sc, 0, cpsw_stat_attached, "IU", 2718 "Time since driver attach"); 2719 2720 SYSCTL_ADD_PROC(ctx, parent, OID_AUTO, "intr_coalesce_us", 2721 CTLTYPE_UINT | CTLFLAG_RW, sc, 0, cpsw_intr_coalesce, "IU", 2722 "minimum time between interrupts"); 2723 2724 node = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "ports", 2725 CTLFLAG_RD, NULL, "CPSW Ports Statistics"); 2726 ports_parent = SYSCTL_CHILDREN(node); 2727 for (i = 0; i < CPSW_PORTS; i++) { 2728 if (!sc->dualemac && i != sc->active_slave) 2729 continue; 2730 port[0] = '0' + i; 2731 port[1] = '\0'; 2732 node = SYSCTL_ADD_NODE(ctx, ports_parent, OID_AUTO, 2733 port, CTLFLAG_RD, NULL, "CPSW Port Statistics"); 2734 port_parent = SYSCTL_CHILDREN(node); 2735 SYSCTL_ADD_PROC(ctx, port_parent, OID_AUTO, "uptime", 2736 CTLTYPE_UINT | CTLFLAG_RD, sc, i, 2737 cpsw_stat_uptime, "IU", "Seconds since driver init"); 2738 } 2739 2740 stats_node = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "stats", 2741 CTLFLAG_RD, NULL, "CPSW Statistics"); 2742 stats_parent = SYSCTL_CHILDREN(stats_node); 2743 for (i = 0; i < CPSW_SYSCTL_COUNT; ++i) { 2744 SYSCTL_ADD_PROC(ctx, stats_parent, i, 2745 cpsw_stat_sysctls[i].oid, 2746 CTLTYPE_U64 | CTLFLAG_RD, sc, 0, 2747 cpsw_stats_sysctl, "IU", 2748 cpsw_stat_sysctls[i].oid); 2749 } 2750 2751 queue_node = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "queue", 2752 CTLFLAG_RD, NULL, "CPSW Queue Statistics"); 2753 queue_parent = SYSCTL_CHILDREN(queue_node); 2754 2755 node = SYSCTL_ADD_NODE(ctx, queue_parent, OID_AUTO, "tx", 2756 CTLFLAG_RD, NULL, "TX Queue Statistics"); 2757 cpsw_add_queue_sysctls(ctx, node, &sc->tx); 2758 2759 node = SYSCTL_ADD_NODE(ctx, queue_parent, OID_AUTO, "rx", 2760 CTLFLAG_RD, NULL, "RX Queue Statistics"); 2761 cpsw_add_queue_sysctls(ctx, node, &sc->rx); 2762 2763 node = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "watchdog", 2764 CTLFLAG_RD, NULL, "Watchdog Statistics"); 2765 cpsw_add_watchdog_sysctls(ctx, node, sc); 2766} 2767 2768#ifdef CPSW_ETHERSWITCH 2769static etherswitch_info_t etherswitch_info = { 2770 .es_nports = CPSW_PORTS + 1, 2771 .es_nvlangroups = CPSW_VLANS, 2772 .es_name = "TI Common Platform Ethernet Switch (CPSW)", 2773 .es_vlan_caps = ETHERSWITCH_VLAN_DOT1Q, 2774}; 2775 2776static etherswitch_info_t * 2777cpsw_getinfo(device_t dev) 2778{ 2779 return (ðerswitch_info); 2780} 2781 2782static int 2783cpsw_getport(device_t dev, etherswitch_port_t *p) 2784{ 2785 int err; 2786 struct cpsw_softc *sc; 2787 struct cpswp_softc *psc; 2788 struct ifmediareq *ifmr; 2789 uint32_t reg; 2790 2791 if (p->es_port < 0 || p->es_port > CPSW_PORTS) 2792 return (ENXIO); 2793 2794 err = 0; 2795 sc = device_get_softc(dev); 2796 if (p->es_port == CPSW_CPU_PORT) { 2797 p->es_flags |= ETHERSWITCH_PORT_CPU; 2798 ifmr = &p->es_ifmr; 2799 ifmr->ifm_current = ifmr->ifm_active = 2800 IFM_ETHER | IFM_1000_T | IFM_FDX; 2801 ifmr->ifm_mask = 0; 2802 ifmr->ifm_status = IFM_ACTIVE | IFM_AVALID; 2803 ifmr->ifm_count = 0; 2804 } else { 2805 psc = device_get_softc(sc->port[p->es_port - 1].dev); 2806 err = ifmedia_ioctl(psc->ifp, &p->es_ifr, 2807 &psc->mii->mii_media, SIOCGIFMEDIA); 2808 } 2809 reg = cpsw_read_4(sc, CPSW_PORT_P_VLAN(p->es_port)); 2810 p->es_pvid = reg & ETHERSWITCH_VID_MASK; 2811 2812 reg = cpsw_read_4(sc, CPSW_ALE_PORTCTL(p->es_port)); 2813 if (reg & ALE_PORTCTL_DROP_UNTAGGED) 2814 p->es_flags |= ETHERSWITCH_PORT_DROPUNTAGGED; 2815 if (reg & ALE_PORTCTL_INGRESS) 2816 p->es_flags |= ETHERSWITCH_PORT_INGRESS; 2817 2818 return (err); 2819} 2820 2821static int 2822cpsw_setport(device_t dev, etherswitch_port_t *p) 2823{ 2824 struct cpsw_softc *sc; 2825 struct cpswp_softc *psc; 2826 struct ifmedia *ifm; 2827 uint32_t reg; 2828 2829 if (p->es_port < 0 || p->es_port > CPSW_PORTS) 2830 return (ENXIO); 2831 2832 sc = device_get_softc(dev); 2833 if (p->es_pvid != 0) { 2834 cpsw_write_4(sc, CPSW_PORT_P_VLAN(p->es_port), 2835 p->es_pvid & ETHERSWITCH_VID_MASK); 2836 } 2837 2838 reg = cpsw_read_4(sc, CPSW_ALE_PORTCTL(p->es_port)); 2839 if (p->es_flags & ETHERSWITCH_PORT_DROPUNTAGGED) 2840 reg |= ALE_PORTCTL_DROP_UNTAGGED; 2841 else 2842 reg &= ~ALE_PORTCTL_DROP_UNTAGGED; 2843 if (p->es_flags & ETHERSWITCH_PORT_INGRESS) 2844 reg |= ALE_PORTCTL_INGRESS; 2845 else 2846 reg &= ~ALE_PORTCTL_INGRESS; 2847 cpsw_write_4(sc, CPSW_ALE_PORTCTL(p->es_port), reg); 2848 2849 /* CPU port does not allow media settings. */ 2850 if (p->es_port == CPSW_CPU_PORT) 2851 return (0); 2852 2853 psc = device_get_softc(sc->port[p->es_port - 1].dev); 2854 ifm = &psc->mii->mii_media; 2855 2856 return (ifmedia_ioctl(psc->ifp, &p->es_ifr, ifm, SIOCSIFMEDIA)); 2857} 2858 2859static int 2860cpsw_getconf(device_t dev, etherswitch_conf_t *conf) 2861{ 2862 2863 /* Return the VLAN mode. */ 2864 conf->cmd = ETHERSWITCH_CONF_VLAN_MODE; 2865 conf->vlan_mode = ETHERSWITCH_VLAN_DOT1Q; 2866 2867 return (0); 2868} 2869 2870static int 2871cpsw_getvgroup(device_t dev, etherswitch_vlangroup_t *vg) 2872{ 2873 int i, vid; 2874 uint32_t ale_entry[3]; 2875 struct cpsw_softc *sc; 2876 2877 sc = device_get_softc(dev); 2878 2879 if (vg->es_vlangroup >= CPSW_VLANS) 2880 return (EINVAL); 2881 2882 vg->es_vid = 0; 2883 vid = cpsw_vgroups[vg->es_vlangroup].vid; 2884 if (vid == -1) 2885 return (0); 2886 2887 for (i = 0; i < CPSW_MAX_ALE_ENTRIES; i++) { 2888 cpsw_ale_read_entry(sc, i, ale_entry); 2889 if (ALE_TYPE(ale_entry) != ALE_TYPE_VLAN) 2890 continue; 2891 if (vid != ALE_VLAN(ale_entry)) 2892 continue; 2893 2894 vg->es_fid = 0; 2895 vg->es_vid = ALE_VLAN(ale_entry) | ETHERSWITCH_VID_VALID; 2896 vg->es_member_ports = ALE_VLAN_MEMBERS(ale_entry); 2897 vg->es_untagged_ports = ALE_VLAN_UNTAG(ale_entry); 2898 } 2899 2900 return (0); 2901} 2902 2903static void 2904cpsw_remove_vlan(struct cpsw_softc *sc, int vlan) 2905{ 2906 int i; 2907 uint32_t ale_entry[3]; 2908 2909 for (i = 0; i < CPSW_MAX_ALE_ENTRIES; i++) { 2910 cpsw_ale_read_entry(sc, i, ale_entry); 2911 if (ALE_TYPE(ale_entry) != ALE_TYPE_VLAN) 2912 continue; 2913 if (vlan != ALE_VLAN(ale_entry)) 2914 continue; 2915 ale_entry[0] = ale_entry[1] = ale_entry[2] = 0; 2916 cpsw_ale_write_entry(sc, i, ale_entry); 2917 break; 2918 } 2919} 2920 2921static int 2922cpsw_setvgroup(device_t dev, etherswitch_vlangroup_t *vg) 2923{ 2924 int i; 2925 struct cpsw_softc *sc; 2926 2927 sc = device_get_softc(dev); 2928 2929 for (i = 0; i < CPSW_VLANS; i++) { 2930 /* Is this Vlan ID in use by another vlangroup ? */ 2931 if (vg->es_vlangroup != i && cpsw_vgroups[i].vid == vg->es_vid) 2932 return (EINVAL); 2933 } 2934 2935 if (vg->es_vid == 0) { 2936 if (cpsw_vgroups[vg->es_vlangroup].vid == -1) 2937 return (0); 2938 cpsw_remove_vlan(sc, cpsw_vgroups[vg->es_vlangroup].vid); 2939 cpsw_vgroups[vg->es_vlangroup].vid = -1; 2940 vg->es_untagged_ports = 0; 2941 vg->es_member_ports = 0; 2942 vg->es_vid = 0; 2943 return (0); 2944 } 2945 2946 vg->es_vid &= ETHERSWITCH_VID_MASK; 2947 vg->es_member_ports &= CPSW_PORTS_MASK; 2948 vg->es_untagged_ports &= CPSW_PORTS_MASK; 2949 2950 if (cpsw_vgroups[vg->es_vlangroup].vid != -1 && 2951 cpsw_vgroups[vg->es_vlangroup].vid != vg->es_vid) 2952 return (EINVAL); 2953 2954 cpsw_vgroups[vg->es_vlangroup].vid = vg->es_vid; 2955 cpsw_ale_update_vlan_table(sc, vg->es_vid, vg->es_member_ports, 2956 vg->es_untagged_ports, vg->es_member_ports, 0); 2957 2958 return (0); 2959} 2960 2961static int 2962cpsw_readreg(device_t dev, int addr) 2963{ 2964 2965 /* Not supported. */ 2966 return (0); 2967} 2968 2969static int 2970cpsw_writereg(device_t dev, int addr, int value) 2971{ 2972 2973 /* Not supported. */ 2974 return (0); 2975} 2976 2977static int 2978cpsw_readphy(device_t dev, int phy, int reg) 2979{ 2980 2981 /* Not supported. */ 2982 return (0); 2983} 2984 2985static int 2986cpsw_writephy(device_t dev, int phy, int reg, int data) 2987{ 2988 2989 /* Not supported. */ 2990 return (0); 2991} 2992#endif 2993