if_cpsw.c revision 310855
1/*- 2 * Copyright (c) 2012 Damjan Marion <dmarion@Freebsd.org> 3 * Copyright (c) 2016 Rubicon Communications, LLC (Netgate) 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28/* 29 * TI Common Platform Ethernet Switch (CPSW) Driver 30 * Found in TI8148 "DaVinci" and AM335x "Sitara" SoCs. 31 * 32 * This controller is documented in the AM335x Technical Reference 33 * Manual, in the TMS320DM814x DaVinci Digital Video Processors TRM 34 * and in the TMS320C6452 3 Port Switch Ethernet Subsystem TRM. 35 * 36 * It is basically a single Ethernet port (port 0) wired internally to 37 * a 3-port store-and-forward switch connected to two independent 38 * "sliver" controllers (port 1 and port 2). You can operate the 39 * controller in a variety of different ways by suitably configuring 40 * the slivers and the Address Lookup Engine (ALE) that routes packets 41 * between the ports. 42 * 43 * This code was developed and tested on a BeagleBone with 44 * an AM335x SoC. 45 */ 46 47#include <sys/cdefs.h> 48__FBSDID("$FreeBSD: stable/11/sys/arm/ti/cpsw/if_cpsw.c 310855 2016-12-30 20:18:50Z loos $"); 49 50#include <sys/param.h> 51#include <sys/systm.h> 52#include <sys/endian.h> 53#include <sys/mbuf.h> 54#include <sys/lock.h> 55#include <sys/mutex.h> 56#include <sys/kernel.h> 57#include <sys/module.h> 58#include <sys/socket.h> 59#include <sys/sysctl.h> 60 61#include <net/ethernet.h> 62#include <net/bpf.h> 63#include <net/if.h> 64#include <net/if_arp.h> 65#include <net/if_dl.h> 66#include <net/if_media.h> 67#include <net/if_types.h> 68#include <net/if_var.h> 69#include <net/if_vlan_var.h> 70 71#include <netinet/in_systm.h> 72#include <netinet/in.h> 73#include <netinet/ip.h> 74 75#include <sys/sockio.h> 76#include <sys/bus.h> 77#include <machine/bus.h> 78#include <sys/rman.h> 79#include <machine/resource.h> 80 81#include <arm/ti/ti_scm.h> 82#include <arm/ti/am335x/am335x_scm.h> 83 84#include <dev/mii/mii.h> 85#include <dev/mii/miivar.h> 86 87#include <dev/fdt/fdt_common.h> 88#include <dev/ofw/ofw_bus.h> 89#include <dev/ofw/ofw_bus_subr.h> 90 91#include "if_cpswreg.h" 92#include "if_cpswvar.h" 93 94#include "miibus_if.h" 95 96/* Device probe/attach/detach. */ 97static int cpsw_probe(device_t); 98static int cpsw_attach(device_t); 99static int cpsw_detach(device_t); 100static int cpswp_probe(device_t); 101static int cpswp_attach(device_t); 102static int cpswp_detach(device_t); 103 104static phandle_t cpsw_get_node(device_t, device_t); 105 106/* Device Init/shutdown. */ 107static int cpsw_shutdown(device_t); 108static void cpswp_init(void *); 109static void cpswp_init_locked(void *); 110static void cpswp_stop_locked(struct cpswp_softc *); 111 112/* Device Suspend/Resume. */ 113static int cpsw_suspend(device_t); 114static int cpsw_resume(device_t); 115 116/* Ioctl. */ 117static int cpswp_ioctl(struct ifnet *, u_long command, caddr_t data); 118 119static int cpswp_miibus_readreg(device_t, int phy, int reg); 120static int cpswp_miibus_writereg(device_t, int phy, int reg, int value); 121static void cpswp_miibus_statchg(device_t); 122 123/* Send/Receive packets. */ 124static void cpsw_intr_rx(void *arg); 125static struct mbuf *cpsw_rx_dequeue(struct cpsw_softc *); 126static void cpsw_rx_enqueue(struct cpsw_softc *); 127static void cpswp_start(struct ifnet *); 128static void cpswp_tx_enqueue(struct cpswp_softc *); 129static int cpsw_tx_dequeue(struct cpsw_softc *); 130 131/* Misc interrupts and watchdog. */ 132static void cpsw_intr_rx_thresh(void *); 133static void cpsw_intr_misc(void *); 134static void cpswp_tick(void *); 135static void cpswp_ifmedia_sts(struct ifnet *, struct ifmediareq *); 136static int cpswp_ifmedia_upd(struct ifnet *); 137static void cpsw_tx_watchdog(void *); 138 139/* ALE support */ 140static void cpsw_ale_read_entry(struct cpsw_softc *, uint16_t, uint32_t *); 141static void cpsw_ale_write_entry(struct cpsw_softc *, uint16_t, uint32_t *); 142static int cpsw_ale_mc_entry_set(struct cpsw_softc *, uint8_t, int, uint8_t *); 143static void cpsw_ale_dump_table(struct cpsw_softc *); 144static int cpsw_ale_update_vlan_table(struct cpsw_softc *, int, int, int, int, 145 int); 146static int cpswp_ale_update_addresses(struct cpswp_softc *, int); 147 148/* Statistics and sysctls. */ 149static void cpsw_add_sysctls(struct cpsw_softc *); 150static void cpsw_stats_collect(struct cpsw_softc *); 151static int cpsw_stats_sysctl(SYSCTL_HANDLER_ARGS); 152 153/* 154 * Arbitrary limit on number of segments in an mbuf to be transmitted. 155 * Packets with more segments than this will be defragmented before 156 * they are queued. 157 */ 158#define CPSW_TXFRAGS 16 159 160/* Shared resources. */ 161static device_method_t cpsw_methods[] = { 162 /* Device interface */ 163 DEVMETHOD(device_probe, cpsw_probe), 164 DEVMETHOD(device_attach, cpsw_attach), 165 DEVMETHOD(device_detach, cpsw_detach), 166 DEVMETHOD(device_shutdown, cpsw_shutdown), 167 DEVMETHOD(device_suspend, cpsw_suspend), 168 DEVMETHOD(device_resume, cpsw_resume), 169 /* OFW methods */ 170 DEVMETHOD(ofw_bus_get_node, cpsw_get_node), 171 DEVMETHOD_END 172}; 173 174static driver_t cpsw_driver = { 175 "cpswss", 176 cpsw_methods, 177 sizeof(struct cpsw_softc), 178}; 179 180static devclass_t cpsw_devclass; 181 182DRIVER_MODULE(cpswss, simplebus, cpsw_driver, cpsw_devclass, 0, 0); 183 184/* Port/Slave resources. */ 185static device_method_t cpswp_methods[] = { 186 /* Device interface */ 187 DEVMETHOD(device_probe, cpswp_probe), 188 DEVMETHOD(device_attach, cpswp_attach), 189 DEVMETHOD(device_detach, cpswp_detach), 190 /* MII interface */ 191 DEVMETHOD(miibus_readreg, cpswp_miibus_readreg), 192 DEVMETHOD(miibus_writereg, cpswp_miibus_writereg), 193 DEVMETHOD(miibus_statchg, cpswp_miibus_statchg), 194 DEVMETHOD_END 195}; 196 197static driver_t cpswp_driver = { 198 "cpsw", 199 cpswp_methods, 200 sizeof(struct cpswp_softc), 201}; 202 203static devclass_t cpswp_devclass; 204 205DRIVER_MODULE(cpsw, cpswss, cpswp_driver, cpswp_devclass, 0, 0); 206DRIVER_MODULE(miibus, cpsw, miibus_driver, miibus_devclass, 0, 0); 207MODULE_DEPEND(cpsw, ether, 1, 1, 1); 208MODULE_DEPEND(cpsw, miibus, 1, 1, 1); 209 210static uint32_t slave_mdio_addr[] = { 0x4a100200, 0x4a100300 }; 211 212static struct resource_spec irq_res_spec[] = { 213 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 214 { SYS_RES_IRQ, 1, RF_ACTIVE | RF_SHAREABLE }, 215 { SYS_RES_IRQ, 2, RF_ACTIVE | RF_SHAREABLE }, 216 { SYS_RES_IRQ, 3, RF_ACTIVE | RF_SHAREABLE }, 217 { -1, 0 } 218}; 219 220/* Number of entries here must match size of stats 221 * array in struct cpswp_softc. */ 222static struct cpsw_stat { 223 int reg; 224 char *oid; 225} cpsw_stat_sysctls[CPSW_SYSCTL_COUNT] = { 226 {0x00, "GoodRxFrames"}, 227 {0x04, "BroadcastRxFrames"}, 228 {0x08, "MulticastRxFrames"}, 229 {0x0C, "PauseRxFrames"}, 230 {0x10, "RxCrcErrors"}, 231 {0x14, "RxAlignErrors"}, 232 {0x18, "OversizeRxFrames"}, 233 {0x1c, "RxJabbers"}, 234 {0x20, "ShortRxFrames"}, 235 {0x24, "RxFragments"}, 236 {0x30, "RxOctets"}, 237 {0x34, "GoodTxFrames"}, 238 {0x38, "BroadcastTxFrames"}, 239 {0x3c, "MulticastTxFrames"}, 240 {0x40, "PauseTxFrames"}, 241 {0x44, "DeferredTxFrames"}, 242 {0x48, "CollisionsTxFrames"}, 243 {0x4c, "SingleCollisionTxFrames"}, 244 {0x50, "MultipleCollisionTxFrames"}, 245 {0x54, "ExcessiveCollisions"}, 246 {0x58, "LateCollisions"}, 247 {0x5c, "TxUnderrun"}, 248 {0x60, "CarrierSenseErrors"}, 249 {0x64, "TxOctets"}, 250 {0x68, "RxTx64OctetFrames"}, 251 {0x6c, "RxTx65to127OctetFrames"}, 252 {0x70, "RxTx128to255OctetFrames"}, 253 {0x74, "RxTx256to511OctetFrames"}, 254 {0x78, "RxTx512to1024OctetFrames"}, 255 {0x7c, "RxTx1024upOctetFrames"}, 256 {0x80, "NetOctets"}, 257 {0x84, "RxStartOfFrameOverruns"}, 258 {0x88, "RxMiddleOfFrameOverruns"}, 259 {0x8c, "RxDmaOverruns"} 260}; 261 262/* 263 * Basic debug support. 264 */ 265 266#define IF_DEBUG(_sc) if ((_sc)->if_flags & IFF_DEBUG) 267 268static void 269cpsw_debugf_head(const char *funcname) 270{ 271 int t = (int)(time_second % (24 * 60 * 60)); 272 273 printf("%02d:%02d:%02d %s ", t / (60 * 60), (t / 60) % 60, t % 60, funcname); 274} 275 276#include <machine/stdarg.h> 277static void 278cpsw_debugf(const char *fmt, ...) 279{ 280 va_list ap; 281 282 va_start(ap, fmt); 283 vprintf(fmt, ap); 284 va_end(ap); 285 printf("\n"); 286 287} 288 289#define CPSW_DEBUGF(_sc, a) do { \ 290 if (sc->debug) { \ 291 cpsw_debugf_head(__func__); \ 292 cpsw_debugf a; \ 293 } \ 294} while (0) 295 296#define CPSWP_DEBUGF(_sc, a) do { \ 297 IF_DEBUG((_sc)) { \ 298 cpsw_debugf_head(__func__); \ 299 cpsw_debugf a; \ 300 } \ 301} while (0) 302 303 304/* 305 * Locking macros 306 */ 307#define CPSW_TX_LOCK(sc) do { \ 308 mtx_assert(&(sc)->rx.lock, MA_NOTOWNED); \ 309 mtx_lock(&(sc)->tx.lock); \ 310} while (0) 311 312#define CPSW_TX_UNLOCK(sc) mtx_unlock(&(sc)->tx.lock) 313#define CPSW_TX_LOCK_ASSERT(sc) mtx_assert(&(sc)->tx.lock, MA_OWNED) 314 315#define CPSW_RX_LOCK(sc) do { \ 316 mtx_assert(&(sc)->tx.lock, MA_NOTOWNED); \ 317 mtx_lock(&(sc)->rx.lock); \ 318} while (0) 319 320#define CPSW_RX_UNLOCK(sc) mtx_unlock(&(sc)->rx.lock) 321#define CPSW_RX_LOCK_ASSERT(sc) mtx_assert(&(sc)->rx.lock, MA_OWNED) 322 323#define CPSW_GLOBAL_LOCK(sc) do { \ 324 if ((mtx_owned(&(sc)->tx.lock) ? 1 : 0) != \ 325 (mtx_owned(&(sc)->rx.lock) ? 1 : 0)) { \ 326 panic("cpsw deadlock possibility detection!"); \ 327 } \ 328 mtx_lock(&(sc)->tx.lock); \ 329 mtx_lock(&(sc)->rx.lock); \ 330} while (0) 331 332#define CPSW_GLOBAL_UNLOCK(sc) do { \ 333 CPSW_RX_UNLOCK(sc); \ 334 CPSW_TX_UNLOCK(sc); \ 335} while (0) 336 337#define CPSW_GLOBAL_LOCK_ASSERT(sc) do { \ 338 CPSW_TX_LOCK_ASSERT(sc); \ 339 CPSW_RX_LOCK_ASSERT(sc); \ 340} while (0) 341 342#define CPSW_PORT_LOCK(_sc) do { \ 343 mtx_assert(&(_sc)->lock, MA_NOTOWNED); \ 344 mtx_lock(&(_sc)->lock); \ 345} while (0) 346 347#define CPSW_PORT_UNLOCK(_sc) mtx_unlock(&(_sc)->lock) 348#define CPSW_PORT_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->lock, MA_OWNED) 349 350/* 351 * Read/Write macros 352 */ 353#define cpsw_read_4(_sc, _reg) bus_read_4((_sc)->mem_res, (_reg)) 354#define cpsw_write_4(_sc, _reg, _val) \ 355 bus_write_4((_sc)->mem_res, (_reg), (_val)) 356 357#define cpsw_cpdma_bd_offset(i) (CPSW_CPPI_RAM_OFFSET + ((i)*16)) 358 359#define cpsw_cpdma_bd_paddr(sc, slot) \ 360 BUS_SPACE_PHYSADDR(sc->mem_res, slot->bd_offset) 361#define cpsw_cpdma_read_bd(sc, slot, val) \ 362 bus_read_region_4(sc->mem_res, slot->bd_offset, (uint32_t *) val, 4) 363#define cpsw_cpdma_write_bd(sc, slot, val) \ 364 bus_write_region_4(sc->mem_res, slot->bd_offset, (uint32_t *) val, 4) 365#define cpsw_cpdma_write_bd_next(sc, slot, next_slot) \ 366 cpsw_write_4(sc, slot->bd_offset, cpsw_cpdma_bd_paddr(sc, next_slot)) 367#define cpsw_cpdma_read_bd_flags(sc, slot) \ 368 bus_read_2(sc->mem_res, slot->bd_offset + 14) 369#define cpsw_write_hdp_slot(sc, queue, slot) \ 370 cpsw_write_4(sc, (queue)->hdp_offset, cpsw_cpdma_bd_paddr(sc, slot)) 371#define CP_OFFSET (CPSW_CPDMA_TX_CP(0) - CPSW_CPDMA_TX_HDP(0)) 372#define cpsw_read_cp(sc, queue) \ 373 cpsw_read_4(sc, (queue)->hdp_offset + CP_OFFSET) 374#define cpsw_write_cp(sc, queue, val) \ 375 cpsw_write_4(sc, (queue)->hdp_offset + CP_OFFSET, (val)) 376#define cpsw_write_cp_slot(sc, queue, slot) \ 377 cpsw_write_cp(sc, queue, cpsw_cpdma_bd_paddr(sc, slot)) 378 379#if 0 380/* XXX temporary function versions for debugging. */ 381static void 382cpsw_write_hdp_slotX(struct cpsw_softc *sc, struct cpsw_queue *queue, struct cpsw_slot *slot) 383{ 384 uint32_t reg = queue->hdp_offset; 385 uint32_t v = cpsw_cpdma_bd_paddr(sc, slot); 386 CPSW_DEBUGF(("HDP <=== 0x%08x (was 0x%08x)", v, cpsw_read_4(sc, reg))); 387 cpsw_write_4(sc, reg, v); 388} 389 390static void 391cpsw_write_cp_slotX(struct cpsw_softc *sc, struct cpsw_queue *queue, struct cpsw_slot *slot) 392{ 393 uint32_t v = cpsw_cpdma_bd_paddr(sc, slot); 394 CPSW_DEBUGF(("CP <=== 0x%08x (expecting 0x%08x)", v, cpsw_read_cp(sc, queue))); 395 cpsw_write_cp(sc, queue, v); 396} 397#endif 398 399/* 400 * Expanded dump routines for verbose debugging. 401 */ 402static void 403cpsw_dump_slot(struct cpsw_softc *sc, struct cpsw_slot *slot) 404{ 405 static const char *flags[] = {"SOP", "EOP", "Owner", "EOQ", 406 "TDownCmplt", "PassCRC", "Long", "Short", "MacCtl", "Overrun", 407 "PktErr1", "PortEn/PktErr0", "RxVlanEncap", "Port2", "Port1", 408 "Port0"}; 409 struct cpsw_cpdma_bd bd; 410 const char *sep; 411 int i; 412 413 cpsw_cpdma_read_bd(sc, slot, &bd); 414 printf("BD Addr: 0x%08x Next: 0x%08x\n", cpsw_cpdma_bd_paddr(sc, slot), bd.next); 415 printf(" BufPtr: 0x%08x BufLen: 0x%08x\n", bd.bufptr, bd.buflen); 416 printf(" BufOff: 0x%08x PktLen: 0x%08x\n", bd.bufoff, bd.pktlen); 417 printf(" Flags: "); 418 sep = ""; 419 for (i = 0; i < 16; ++i) { 420 if (bd.flags & (1 << (15 - i))) { 421 printf("%s%s", sep, flags[i]); 422 sep = ","; 423 } 424 } 425 printf("\n"); 426 if (slot->mbuf) { 427 printf(" Ether: %14D\n", 428 (char *)(slot->mbuf->m_data), " "); 429 printf(" Packet: %16D\n", 430 (char *)(slot->mbuf->m_data) + 14, " "); 431 } 432} 433 434#define CPSW_DUMP_SLOT(cs, slot) do { \ 435 IF_DEBUG(sc) { \ 436 cpsw_dump_slot(sc, slot); \ 437 } \ 438} while (0) 439 440static void 441cpsw_dump_queue(struct cpsw_softc *sc, struct cpsw_slots *q) 442{ 443 struct cpsw_slot *slot; 444 int i = 0; 445 int others = 0; 446 447 STAILQ_FOREACH(slot, q, next) { 448 if (i > 4) 449 ++others; 450 else 451 cpsw_dump_slot(sc, slot); 452 ++i; 453 } 454 if (others) 455 printf(" ... and %d more.\n", others); 456 printf("\n"); 457} 458 459#define CPSW_DUMP_QUEUE(sc, q) do { \ 460 IF_DEBUG(sc) { \ 461 cpsw_dump_queue(sc, q); \ 462 } \ 463} while (0) 464 465static void 466cpsw_init_slots(struct cpsw_softc *sc) 467{ 468 struct cpsw_slot *slot; 469 int i; 470 471 STAILQ_INIT(&sc->avail); 472 473 /* Put the slot descriptors onto the global avail list. */ 474 for (i = 0; i < nitems(sc->_slots); i++) { 475 slot = &sc->_slots[i]; 476 slot->bd_offset = cpsw_cpdma_bd_offset(i); 477 STAILQ_INSERT_TAIL(&sc->avail, slot, next); 478 } 479} 480 481static int 482cpsw_add_slots(struct cpsw_softc *sc, struct cpsw_queue *queue, int requested) 483{ 484 const int max_slots = nitems(sc->_slots); 485 struct cpsw_slot *slot; 486 int i; 487 488 if (requested < 0) 489 requested = max_slots; 490 491 for (i = 0; i < requested; ++i) { 492 slot = STAILQ_FIRST(&sc->avail); 493 if (slot == NULL) 494 return (0); 495 if (bus_dmamap_create(sc->mbuf_dtag, 0, &slot->dmamap)) { 496 device_printf(sc->dev, "failed to create dmamap\n"); 497 return (ENOMEM); 498 } 499 STAILQ_REMOVE_HEAD(&sc->avail, next); 500 STAILQ_INSERT_TAIL(&queue->avail, slot, next); 501 ++queue->avail_queue_len; 502 ++queue->queue_slots; 503 } 504 return (0); 505} 506 507static void 508cpsw_free_slot(struct cpsw_softc *sc, struct cpsw_slot *slot) 509{ 510 int error; 511 512 if (slot->dmamap) { 513 if (slot->mbuf) 514 bus_dmamap_unload(sc->mbuf_dtag, slot->dmamap); 515 error = bus_dmamap_destroy(sc->mbuf_dtag, slot->dmamap); 516 KASSERT(error == 0, ("Mapping still active")); 517 slot->dmamap = NULL; 518 } 519 if (slot->mbuf) { 520 m_freem(slot->mbuf); 521 slot->mbuf = NULL; 522 } 523} 524 525static void 526cpsw_reset(struct cpsw_softc *sc) 527{ 528 int i; 529 530 callout_stop(&sc->watchdog.callout); 531 532 /* Reset RMII/RGMII wrapper. */ 533 cpsw_write_4(sc, CPSW_WR_SOFT_RESET, 1); 534 while (cpsw_read_4(sc, CPSW_WR_SOFT_RESET) & 1) 535 ; 536 537 /* Disable TX and RX interrupts for all cores. */ 538 for (i = 0; i < 3; ++i) { 539 cpsw_write_4(sc, CPSW_WR_C_RX_THRESH_EN(i), 0x00); 540 cpsw_write_4(sc, CPSW_WR_C_TX_EN(i), 0x00); 541 cpsw_write_4(sc, CPSW_WR_C_RX_EN(i), 0x00); 542 cpsw_write_4(sc, CPSW_WR_C_MISC_EN(i), 0x00); 543 } 544 545 /* Reset CPSW subsystem. */ 546 cpsw_write_4(sc, CPSW_SS_SOFT_RESET, 1); 547 while (cpsw_read_4(sc, CPSW_SS_SOFT_RESET) & 1) 548 ; 549 550 /* Reset Sliver port 1 and 2 */ 551 for (i = 0; i < 2; i++) { 552 /* Reset */ 553 cpsw_write_4(sc, CPSW_SL_SOFT_RESET(i), 1); 554 while (cpsw_read_4(sc, CPSW_SL_SOFT_RESET(i)) & 1) 555 ; 556 } 557 558 /* Reset DMA controller. */ 559 cpsw_write_4(sc, CPSW_CPDMA_SOFT_RESET, 1); 560 while (cpsw_read_4(sc, CPSW_CPDMA_SOFT_RESET) & 1) 561 ; 562 563 /* Disable TX & RX DMA */ 564 cpsw_write_4(sc, CPSW_CPDMA_TX_CONTROL, 0); 565 cpsw_write_4(sc, CPSW_CPDMA_RX_CONTROL, 0); 566 567 /* Clear all queues. */ 568 for (i = 0; i < 8; i++) { 569 cpsw_write_4(sc, CPSW_CPDMA_TX_HDP(i), 0); 570 cpsw_write_4(sc, CPSW_CPDMA_RX_HDP(i), 0); 571 cpsw_write_4(sc, CPSW_CPDMA_TX_CP(i), 0); 572 cpsw_write_4(sc, CPSW_CPDMA_RX_CP(i), 0); 573 } 574 575 /* Clear all interrupt Masks */ 576 cpsw_write_4(sc, CPSW_CPDMA_RX_INTMASK_CLEAR, 0xFFFFFFFF); 577 cpsw_write_4(sc, CPSW_CPDMA_TX_INTMASK_CLEAR, 0xFFFFFFFF); 578} 579 580static void 581cpsw_init(struct cpsw_softc *sc) 582{ 583 struct cpsw_slot *slot; 584 uint32_t reg; 585 586 /* Clear ALE */ 587 cpsw_write_4(sc, CPSW_ALE_CONTROL, CPSW_ALE_CTL_CLEAR_TBL); 588 589 /* Enable ALE */ 590 reg = CPSW_ALE_CTL_ENABLE; 591 if (sc->dualemac) 592 reg |= CPSW_ALE_CTL_VLAN_AWARE; 593 cpsw_write_4(sc, CPSW_ALE_CONTROL, reg); 594 595 /* Set Host Port Mapping. */ 596 cpsw_write_4(sc, CPSW_PORT_P0_CPDMA_TX_PRI_MAP, 0x76543210); 597 cpsw_write_4(sc, CPSW_PORT_P0_CPDMA_RX_CH_MAP, 0); 598 599 /* Initialize ALE: set host port to forwarding(3). */ 600 cpsw_write_4(sc, CPSW_ALE_PORTCTL(0), 3); 601 602 cpsw_write_4(sc, CPSW_SS_PTYPE, 0); 603 604 /* Enable statistics for ports 0, 1 and 2 */ 605 cpsw_write_4(sc, CPSW_SS_STAT_PORT_EN, 7); 606 607 /* Experiment: Turn off flow control */ 608 /* This seems to fix the watchdog resets that have plagued 609 earlier versions of this driver; I'm not yet sure if there 610 are negative effects yet. */ 611 cpsw_write_4(sc, CPSW_SS_FLOW_CONTROL, 0); 612 613 /* Make IP hdr aligned with 4 */ 614 cpsw_write_4(sc, CPSW_CPDMA_RX_BUFFER_OFFSET, 2); 615 616 /* Initialize RX Buffer Descriptors */ 617 cpsw_write_4(sc, CPSW_CPDMA_RX_FREEBUFFER(0), 0); 618 619 /* Enable TX & RX DMA */ 620 cpsw_write_4(sc, CPSW_CPDMA_TX_CONTROL, 1); 621 cpsw_write_4(sc, CPSW_CPDMA_RX_CONTROL, 1); 622 623 /* Enable Interrupts for core 0 */ 624 cpsw_write_4(sc, CPSW_WR_C_RX_THRESH_EN(0), 0xFF); 625 cpsw_write_4(sc, CPSW_WR_C_RX_EN(0), 0xFF); 626 cpsw_write_4(sc, CPSW_WR_C_MISC_EN(0), 0x1F); 627 628 /* Enable host Error Interrupt */ 629 cpsw_write_4(sc, CPSW_CPDMA_DMA_INTMASK_SET, 3); 630 631 /* Enable interrupts for RX Channel 0 */ 632 cpsw_write_4(sc, CPSW_CPDMA_RX_INTMASK_SET, 1); 633 634 /* Initialze MDIO - ENABLE, PREAMBLE=0, FAULTENB, CLKDIV=0xFF */ 635 /* TODO Calculate MDCLK=CLK/(CLKDIV+1) */ 636 cpsw_write_4(sc, MDIOCONTROL, MDIOCTL_ENABLE | MDIOCTL_FAULTENB | 0xff); 637 638 /* Select MII in GMII_SEL, Internal Delay mode */ 639 //ti_scm_reg_write_4(0x650, 0); 640 641 /* Initialize active queues. */ 642 slot = STAILQ_FIRST(&sc->tx.active); 643 if (slot != NULL) 644 cpsw_write_hdp_slot(sc, &sc->tx, slot); 645 slot = STAILQ_FIRST(&sc->rx.active); 646 if (slot != NULL) 647 cpsw_write_hdp_slot(sc, &sc->rx, slot); 648 cpsw_rx_enqueue(sc); 649 650 /* Activate network interface. */ 651 sc->rx.running = 1; 652 sc->tx.running = 1; 653 sc->watchdog.timer = 0; 654 callout_init(&sc->watchdog.callout, 0); 655 callout_reset(&sc->watchdog.callout, hz, cpsw_tx_watchdog, sc); 656} 657 658/* 659 * 660 * Device Probe, Attach, Detach. 661 * 662 */ 663 664static int 665cpsw_probe(device_t dev) 666{ 667 668 if (!ofw_bus_status_okay(dev)) 669 return (ENXIO); 670 671 if (!ofw_bus_is_compatible(dev, "ti,cpsw")) 672 return (ENXIO); 673 674 device_set_desc(dev, "3-port Switch Ethernet Subsystem"); 675 return (BUS_PROBE_DEFAULT); 676} 677 678static int 679cpsw_intr_attach(struct cpsw_softc *sc) 680{ 681 682 /* Note: We don't use sc->irq_res[2] (TX interrupt) */ 683 if (bus_setup_intr(sc->dev, sc->irq_res[0], 684 INTR_TYPE_NET | INTR_MPSAFE, NULL, cpsw_intr_rx_thresh, 685 sc, &sc->ih_cookie[0]) != 0) { 686 return (-1); 687 } 688 if (bus_setup_intr(sc->dev, sc->irq_res[1], 689 INTR_TYPE_NET | INTR_MPSAFE, NULL, cpsw_intr_rx, 690 sc, &sc->ih_cookie[1]) != 0) { 691 return (-1); 692 } 693 if (bus_setup_intr(sc->dev, sc->irq_res[3], 694 INTR_TYPE_NET | INTR_MPSAFE, NULL, cpsw_intr_misc, 695 sc, &sc->ih_cookie[3]) != 0) { 696 return (-1); 697 } 698 699 return (0); 700} 701 702static void 703cpsw_intr_detach(struct cpsw_softc *sc) 704{ 705 int i; 706 707 for (i = 0; i < CPSW_INTR_COUNT; i++) { 708 if (sc->ih_cookie[i]) { 709 bus_teardown_intr(sc->dev, sc->irq_res[i], 710 sc->ih_cookie[i]); 711 } 712 } 713} 714 715static int 716cpsw_get_fdt_data(struct cpsw_softc *sc, int port) 717{ 718 char *name; 719 int len, phy, vlan; 720 pcell_t phy_id[3], vlan_id; 721 phandle_t child; 722 unsigned long mdio_child_addr; 723 724 /* Find any slave with phy_id */ 725 phy = -1; 726 vlan = -1; 727 for (child = OF_child(sc->node); child != 0; child = OF_peer(child)) { 728 if (OF_getprop_alloc(child, "name", 1, (void **)&name) < 0) 729 continue; 730 if (sscanf(name, "slave@%x", &mdio_child_addr) != 1) { 731 OF_prop_free(name); 732 continue; 733 } 734 OF_prop_free(name); 735 if (mdio_child_addr != slave_mdio_addr[port]) 736 continue; 737 738 len = OF_getproplen(child, "phy_id"); 739 if (len / sizeof(pcell_t) == 2) { 740 /* Get phy address from fdt */ 741 if (OF_getencprop(child, "phy_id", phy_id, len) > 0) 742 phy = phy_id[1]; 743 } 744 745 len = OF_getproplen(child, "dual_emac_res_vlan"); 746 if (len / sizeof(pcell_t) == 1) { 747 /* Get phy address from fdt */ 748 if (OF_getencprop(child, "dual_emac_res_vlan", 749 &vlan_id, len) > 0) { 750 vlan = vlan_id; 751 } 752 } 753 754 break; 755 } 756 if (phy == -1) 757 return (ENXIO); 758 sc->port[port].phy = phy; 759 sc->port[port].vlan = vlan; 760 761 return (0); 762} 763 764static int 765cpsw_attach(device_t dev) 766{ 767 bus_dma_segment_t segs[1]; 768 int error, i, nsegs; 769 struct cpsw_softc *sc; 770 uint32_t reg; 771 772 sc = device_get_softc(dev); 773 sc->dev = dev; 774 sc->node = ofw_bus_get_node(dev); 775 getbinuptime(&sc->attach_uptime); 776 777 if (OF_getencprop(sc->node, "active_slave", &sc->active_slave, 778 sizeof(sc->active_slave)) <= 0) { 779 sc->active_slave = 0; 780 } 781 if (sc->active_slave > 1) 782 sc->active_slave = 1; 783 784 if (OF_hasprop(sc->node, "dual_emac")) 785 sc->dualemac = 1; 786 787 for (i = 0; i < CPSW_PORTS; i++) { 788 if (!sc->dualemac && i != sc->active_slave) 789 continue; 790 if (cpsw_get_fdt_data(sc, i) != 0) { 791 device_printf(dev, 792 "failed to get PHY address from FDT\n"); 793 return (ENXIO); 794 } 795 } 796 797 /* Initialize mutexes */ 798 mtx_init(&sc->tx.lock, device_get_nameunit(dev), 799 "cpsw TX lock", MTX_DEF); 800 mtx_init(&sc->rx.lock, device_get_nameunit(dev), 801 "cpsw RX lock", MTX_DEF); 802 803 /* Allocate IRQ resources */ 804 error = bus_alloc_resources(dev, irq_res_spec, sc->irq_res); 805 if (error) { 806 device_printf(dev, "could not allocate IRQ resources\n"); 807 cpsw_detach(dev); 808 return (ENXIO); 809 } 810 811 sc->mem_rid = 0; 812 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 813 &sc->mem_rid, RF_ACTIVE); 814 if (sc->mem_res == NULL) { 815 device_printf(sc->dev, "failed to allocate memory resource\n"); 816 cpsw_detach(dev); 817 return (ENXIO); 818 } 819 820 reg = cpsw_read_4(sc, CPSW_SS_IDVER); 821 device_printf(dev, "CPSW SS Version %d.%d (%d)\n", (reg >> 8 & 0x7), 822 reg & 0xFF, (reg >> 11) & 0x1F); 823 824 cpsw_add_sysctls(sc); 825 826 /* Allocate a busdma tag and DMA safe memory for mbufs. */ 827 error = bus_dma_tag_create( 828 bus_get_dma_tag(sc->dev), /* parent */ 829 1, 0, /* alignment, boundary */ 830 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 831 BUS_SPACE_MAXADDR, /* highaddr */ 832 NULL, NULL, /* filtfunc, filtfuncarg */ 833 MCLBYTES, CPSW_TXFRAGS, /* maxsize, nsegments */ 834 MCLBYTES, 0, /* maxsegsz, flags */ 835 NULL, NULL, /* lockfunc, lockfuncarg */ 836 &sc->mbuf_dtag); /* dmatag */ 837 if (error) { 838 device_printf(dev, "bus_dma_tag_create failed\n"); 839 cpsw_detach(dev); 840 return (error); 841 } 842 843 /* Allocate the null mbuf and pre-sync it. */ 844 sc->null_mbuf = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 845 memset(sc->null_mbuf->m_data, 0, sc->null_mbuf->m_ext.ext_size); 846 bus_dmamap_create(sc->mbuf_dtag, 0, &sc->null_mbuf_dmamap); 847 bus_dmamap_load_mbuf_sg(sc->mbuf_dtag, sc->null_mbuf_dmamap, 848 sc->null_mbuf, segs, &nsegs, BUS_DMA_NOWAIT); 849 bus_dmamap_sync(sc->mbuf_dtag, sc->null_mbuf_dmamap, 850 BUS_DMASYNC_PREWRITE); 851 sc->null_mbuf_paddr = segs[0].ds_addr; 852 853 cpsw_init_slots(sc); 854 855 /* Allocate slots to TX and RX queues. */ 856 STAILQ_INIT(&sc->rx.avail); 857 STAILQ_INIT(&sc->rx.active); 858 STAILQ_INIT(&sc->tx.avail); 859 STAILQ_INIT(&sc->tx.active); 860 // For now: 128 slots to TX, rest to RX. 861 // XXX TODO: start with 32/64 and grow dynamically based on demand. 862 if (cpsw_add_slots(sc, &sc->tx, 128) || 863 cpsw_add_slots(sc, &sc->rx, -1)) { 864 device_printf(dev, "failed to allocate dmamaps\n"); 865 cpsw_detach(dev); 866 return (ENOMEM); 867 } 868 device_printf(dev, "Initial queue size TX=%d RX=%d\n", 869 sc->tx.queue_slots, sc->rx.queue_slots); 870 871 sc->tx.hdp_offset = CPSW_CPDMA_TX_HDP(0); 872 sc->rx.hdp_offset = CPSW_CPDMA_RX_HDP(0); 873 874 if (cpsw_intr_attach(sc) == -1) { 875 device_printf(dev, "failed to setup interrupts\n"); 876 cpsw_detach(dev); 877 return (ENXIO); 878 } 879 880 /* Reset the controller. */ 881 cpsw_reset(sc); 882 cpsw_init(sc); 883 884 for (i = 0; i < CPSW_PORTS; i++) { 885 if (!sc->dualemac && i != sc->active_slave) 886 continue; 887 sc->port[i].dev = device_add_child(dev, "cpsw", i); 888 if (sc->port[i].dev == NULL) { 889 cpsw_detach(dev); 890 return (ENXIO); 891 } 892 } 893 bus_generic_attach(dev); 894 895 return (0); 896} 897 898static int 899cpsw_detach(device_t dev) 900{ 901 struct cpsw_softc *sc; 902 int error, i; 903 904 bus_generic_detach(dev); 905 sc = device_get_softc(dev); 906 907 for (i = 0; i < CPSW_PORTS; i++) { 908 if (sc->port[i].dev) 909 device_delete_child(dev, sc->port[i].dev); 910 } 911 912 if (device_is_attached(dev)) { 913 callout_stop(&sc->watchdog.callout); 914 callout_drain(&sc->watchdog.callout); 915 } 916 917 /* Stop and release all interrupts */ 918 cpsw_intr_detach(sc); 919 920 /* Free dmamaps and mbufs */ 921 for (i = 0; i < nitems(sc->_slots); ++i) 922 cpsw_free_slot(sc, &sc->_slots[i]); 923 924 /* Free null mbuf. */ 925 if (sc->null_mbuf_dmamap) { 926 bus_dmamap_unload(sc->mbuf_dtag, sc->null_mbuf_dmamap); 927 error = bus_dmamap_destroy(sc->mbuf_dtag, sc->null_mbuf_dmamap); 928 KASSERT(error == 0, ("Mapping still active")); 929 m_freem(sc->null_mbuf); 930 } 931 932 /* Free DMA tag */ 933 if (sc->mbuf_dtag) { 934 error = bus_dma_tag_destroy(sc->mbuf_dtag); 935 KASSERT(error == 0, ("Unable to destroy DMA tag")); 936 } 937 938 /* Free IO memory handler */ 939 if (sc->mem_res != NULL) 940 bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid, sc->mem_res); 941 bus_release_resources(dev, irq_res_spec, sc->irq_res); 942 943 /* Destroy mutexes */ 944 mtx_destroy(&sc->rx.lock); 945 mtx_destroy(&sc->tx.lock); 946 947 return (0); 948} 949 950static phandle_t 951cpsw_get_node(device_t bus, device_t dev) 952{ 953 954 /* Share controller node with port device. */ 955 return (ofw_bus_get_node(bus)); 956} 957 958static int 959cpswp_probe(device_t dev) 960{ 961 962 if (device_get_unit(dev) > 1) { 963 device_printf(dev, "Only two ports are supported.\n"); 964 return (ENXIO); 965 } 966 device_set_desc(dev, "Ethernet Switch Port"); 967 968 return (BUS_PROBE_DEFAULT); 969} 970 971static int 972cpswp_attach(device_t dev) 973{ 974 int error; 975 struct ifnet *ifp; 976 struct cpswp_softc *sc; 977 uint32_t reg; 978 uint8_t mac_addr[ETHER_ADDR_LEN]; 979 980 sc = device_get_softc(dev); 981 sc->dev = dev; 982 sc->pdev = device_get_parent(dev); 983 sc->swsc = device_get_softc(sc->pdev); 984 sc->unit = device_get_unit(dev); 985 sc->phy = sc->swsc->port[sc->unit].phy; 986 sc->vlan = sc->swsc->port[sc->unit].vlan; 987 if (sc->swsc->dualemac && sc->vlan == -1) 988 sc->vlan = sc->unit + 1; 989 990 if (sc->unit == 0) { 991 sc->physel = MDIOUSERPHYSEL0; 992 sc->phyaccess = MDIOUSERACCESS0; 993 } else { 994 sc->physel = MDIOUSERPHYSEL1; 995 sc->phyaccess = MDIOUSERACCESS1; 996 } 997 998 mtx_init(&sc->lock, device_get_nameunit(dev), "cpsw port lock", 999 MTX_DEF); 1000 1001 /* Allocate network interface */ 1002 ifp = sc->ifp = if_alloc(IFT_ETHER); 1003 if (ifp == NULL) { 1004 cpswp_detach(dev); 1005 return (ENXIO); 1006 } 1007 1008 if_initname(ifp, device_get_name(sc->dev), sc->unit); 1009 ifp->if_softc = sc; 1010 ifp->if_flags = IFF_SIMPLEX | IFF_MULTICAST | IFF_BROADCAST; 1011 ifp->if_capabilities = IFCAP_VLAN_MTU | IFCAP_HWCSUM; //FIXME VLAN? 1012 ifp->if_capenable = ifp->if_capabilities; 1013 1014 ifp->if_init = cpswp_init; 1015 ifp->if_start = cpswp_start; 1016 ifp->if_ioctl = cpswp_ioctl; 1017 1018 ifp->if_snd.ifq_drv_maxlen = sc->swsc->tx.queue_slots; 1019 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 1020 IFQ_SET_READY(&ifp->if_snd); 1021 1022 /* Get high part of MAC address from control module (mac_id[0|1]_hi) */ 1023 ti_scm_reg_read_4(SCM_MAC_ID0_HI + sc->unit * 8, ®); 1024 mac_addr[0] = reg & 0xFF; 1025 mac_addr[1] = (reg >> 8) & 0xFF; 1026 mac_addr[2] = (reg >> 16) & 0xFF; 1027 mac_addr[3] = (reg >> 24) & 0xFF; 1028 1029 /* Get low part of MAC address from control module (mac_id[0|1]_lo) */ 1030 ti_scm_reg_read_4(SCM_MAC_ID0_LO + sc->unit * 8, ®); 1031 mac_addr[4] = reg & 0xFF; 1032 mac_addr[5] = (reg >> 8) & 0xFF; 1033 1034 error = mii_attach(dev, &sc->miibus, ifp, cpswp_ifmedia_upd, 1035 cpswp_ifmedia_sts, BMSR_DEFCAPMASK, sc->phy, MII_OFFSET_ANY, 0); 1036 if (error) { 1037 device_printf(dev, "attaching PHYs failed\n"); 1038 cpswp_detach(dev); 1039 return (error); 1040 } 1041 sc->mii = device_get_softc(sc->miibus); 1042 1043 /* Select PHY and enable interrupts */ 1044 cpsw_write_4(sc->swsc, sc->physel, 1045 MDIO_PHYSEL_LINKINTENB | (sc->phy & 0x1F)); 1046 1047 ether_ifattach(sc->ifp, mac_addr); 1048 callout_init(&sc->mii_callout, 0); 1049 1050 return (0); 1051} 1052 1053static int 1054cpswp_detach(device_t dev) 1055{ 1056 struct cpswp_softc *sc; 1057 1058 sc = device_get_softc(dev); 1059 CPSWP_DEBUGF(sc, ("")); 1060 if (device_is_attached(dev)) { 1061 ether_ifdetach(sc->ifp); 1062 CPSW_PORT_LOCK(sc); 1063 cpswp_stop_locked(sc); 1064 CPSW_PORT_UNLOCK(sc); 1065 callout_drain(&sc->mii_callout); 1066 } 1067 1068 bus_generic_detach(dev); 1069 1070 if_free(sc->ifp); 1071 mtx_destroy(&sc->lock); 1072 1073 return (0); 1074} 1075 1076/* 1077 * 1078 * Init/Shutdown. 1079 * 1080 */ 1081 1082static int 1083cpsw_ports_down(struct cpsw_softc *sc) 1084{ 1085 struct cpswp_softc *psc; 1086 struct ifnet *ifp1, *ifp2; 1087 1088 if (!sc->dualemac) 1089 return (1); 1090 psc = device_get_softc(sc->port[0].dev); 1091 ifp1 = psc->ifp; 1092 psc = device_get_softc(sc->port[1].dev); 1093 ifp2 = psc->ifp; 1094 if ((ifp1->if_flags & IFF_UP) == 0 && (ifp2->if_flags & IFF_UP) == 0) 1095 return (1); 1096 1097 return (0); 1098} 1099 1100static void 1101cpswp_init(void *arg) 1102{ 1103 struct cpswp_softc *sc = arg; 1104 1105 CPSWP_DEBUGF(sc, ("")); 1106 CPSW_PORT_LOCK(sc); 1107 cpswp_init_locked(arg); 1108 CPSW_PORT_UNLOCK(sc); 1109} 1110 1111static void 1112cpswp_init_locked(void *arg) 1113{ 1114 struct cpswp_softc *sc = arg; 1115 struct ifnet *ifp; 1116 uint32_t reg; 1117 1118 CPSWP_DEBUGF(sc, ("")); 1119 CPSW_PORT_LOCK_ASSERT(sc); 1120 ifp = sc->ifp; 1121 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1122 return; 1123 1124 getbinuptime(&sc->init_uptime); 1125 1126 if (!sc->swsc->rx.running && !sc->swsc->tx.running) { 1127 /* Reset the controller. */ 1128 cpsw_reset(sc->swsc); 1129 cpsw_init(sc->swsc); 1130 } 1131 1132 /* Set Slave Mapping. */ 1133 cpsw_write_4(sc->swsc, CPSW_SL_RX_PRI_MAP(sc->unit), 0x76543210); 1134 cpsw_write_4(sc->swsc, CPSW_PORT_P_TX_PRI_MAP(sc->unit + 1), 1135 0x33221100); 1136 cpsw_write_4(sc->swsc, CPSW_SL_RX_MAXLEN(sc->unit), 0x5f2); 1137 /* Enable MAC RX/TX modules. */ 1138 /* TODO: Docs claim that IFCTL_B and IFCTL_A do the same thing? */ 1139 /* Huh? Docs call bit 0 "Loopback" some places, "FullDuplex" others. */ 1140 reg = cpsw_read_4(sc->swsc, CPSW_SL_MACCONTROL(sc->unit)); 1141 reg |= CPSW_SL_MACTL_GMII_ENABLE; 1142 cpsw_write_4(sc->swsc, CPSW_SL_MACCONTROL(sc->unit), reg); 1143 1144 /* Initialize ALE: set port to forwarding(3), initialize addrs */ 1145 cpsw_write_4(sc->swsc, CPSW_ALE_PORTCTL(sc->unit + 1), 3); 1146 cpswp_ale_update_addresses(sc, 1); 1147 1148 if (sc->swsc->dualemac) { 1149 /* Set Port VID. */ 1150 cpsw_write_4(sc->swsc, CPSW_PORT_P_VLAN(sc->unit + 1), 1151 sc->vlan & 0xfff); 1152 cpsw_ale_update_vlan_table(sc->swsc, sc->vlan, 1153 (1 << (sc->unit + 1)) | (1 << 0), /* Member list */ 1154 (1 << (sc->unit + 1)) | (1 << 0), /* Untagged egress */ 1155 (1 << (sc->unit + 1)) | (1 << 0), 0); /* mcast reg flood */ 1156 } 1157 1158 mii_mediachg(sc->mii); 1159 callout_reset(&sc->mii_callout, hz, cpswp_tick, sc); 1160 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1161 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1162} 1163 1164static int 1165cpsw_shutdown(device_t dev) 1166{ 1167 struct cpsw_softc *sc; 1168 struct cpswp_softc *psc; 1169 int i; 1170 1171 sc = device_get_softc(dev); 1172 CPSW_DEBUGF(sc, ("")); 1173 for (i = 0; i < CPSW_PORTS; i++) { 1174 if (!sc->dualemac && i != sc->active_slave) 1175 continue; 1176 psc = device_get_softc(sc->port[i].dev); 1177 CPSW_PORT_LOCK(psc); 1178 cpswp_stop_locked(psc); 1179 CPSW_PORT_UNLOCK(psc); 1180 } 1181 1182 return (0); 1183} 1184 1185static void 1186cpsw_rx_teardown_locked(struct cpsw_softc *sc) 1187{ 1188 struct ifnet *ifp; 1189 struct mbuf *received, *next; 1190 int i = 0; 1191 1192 CPSW_DEBUGF(sc, ("starting RX teardown")); 1193 cpsw_write_4(sc, CPSW_CPDMA_RX_TEARDOWN, 0); 1194 for (;;) { 1195 received = cpsw_rx_dequeue(sc); 1196 CPSW_GLOBAL_UNLOCK(sc); 1197 while (received != NULL) { 1198 next = received->m_nextpkt; 1199 received->m_nextpkt = NULL; 1200 ifp = received->m_pkthdr.rcvif; 1201 (*ifp->if_input)(ifp, received); 1202 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 1203 received = next; 1204 } 1205 CPSW_GLOBAL_LOCK(sc); 1206 if (!sc->rx.running) { 1207 CPSW_DEBUGF(sc, 1208 ("finished RX teardown (%d retries)", i)); 1209 return; 1210 } 1211 if (++i > 10) { 1212 device_printf(sc->dev, 1213 "Unable to cleanly shutdown receiver\n"); 1214 return; 1215 } 1216 DELAY(10); 1217 } 1218} 1219 1220static void 1221cpsw_tx_teardown_locked(struct cpsw_softc *sc) 1222{ 1223 int i = 0; 1224 1225 CPSW_DEBUGF(sc, ("starting TX teardown")); 1226 cpsw_write_4(sc, CPSW_CPDMA_TX_TEARDOWN, 0); 1227 cpsw_tx_dequeue(sc); 1228 while (sc->tx.running && ++i < 10) { 1229 DELAY(10); 1230 cpsw_tx_dequeue(sc); 1231 } 1232 if (sc->tx.running) { 1233 device_printf(sc->dev, 1234 "Unable to cleanly shutdown transmitter\n"); 1235 } 1236 CPSW_DEBUGF(sc, ("finished TX teardown (%d retries, %d idle buffers)", 1237 i, sc->tx.active_queue_len)); 1238} 1239 1240static void 1241cpswp_stop_locked(struct cpswp_softc *sc) 1242{ 1243 struct ifnet *ifp; 1244 uint32_t reg; 1245 1246 ifp = sc->ifp; 1247 CPSWP_DEBUGF(sc, ("")); 1248 CPSW_PORT_LOCK_ASSERT(sc); 1249 1250 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 1251 return; 1252 1253 /* Disable interface */ 1254 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1255 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1256 1257 /* Stop ticker */ 1258 callout_stop(&sc->mii_callout); 1259 1260 /* Tear down the RX/TX queues. */ 1261 if (cpsw_ports_down(sc->swsc)) { 1262 CPSW_GLOBAL_LOCK(sc->swsc); 1263 cpsw_rx_teardown_locked(sc->swsc); 1264 cpsw_tx_teardown_locked(sc->swsc); 1265 CPSW_GLOBAL_UNLOCK(sc->swsc); 1266 } 1267 1268 /* Stop MAC RX/TX modules. */ 1269 reg = cpsw_read_4(sc->swsc, CPSW_SL_MACCONTROL(sc->unit)); 1270 reg &= ~CPSW_SL_MACTL_GMII_ENABLE; 1271 cpsw_write_4(sc->swsc, CPSW_SL_MACCONTROL(sc->unit), reg); 1272 1273 if (cpsw_ports_down(sc->swsc)) { 1274 /* Capture stats before we reset controller. */ 1275 cpsw_stats_collect(sc->swsc); 1276 1277 cpsw_reset(sc->swsc); 1278 cpsw_init(sc->swsc); 1279 } 1280} 1281 1282/* 1283 * Suspend/Resume. 1284 */ 1285 1286static int 1287cpsw_suspend(device_t dev) 1288{ 1289 struct cpsw_softc *sc; 1290 struct cpswp_softc *psc; 1291 int i; 1292 1293 sc = device_get_softc(dev); 1294 CPSW_DEBUGF(sc, ("")); 1295 for (i = 0; i < CPSW_PORTS; i++) { 1296 if (!sc->dualemac && i != sc->active_slave) 1297 continue; 1298 psc = device_get_softc(sc->port[i].dev); 1299 CPSW_PORT_LOCK(psc); 1300 cpswp_stop_locked(psc); 1301 CPSW_PORT_UNLOCK(psc); 1302 } 1303 1304 return (0); 1305} 1306 1307static int 1308cpsw_resume(device_t dev) 1309{ 1310 struct cpsw_softc *sc; 1311 1312 sc = device_get_softc(dev); 1313 CPSW_DEBUGF(sc, ("UNIMPLEMENTED")); 1314 1315 return (0); 1316} 1317 1318/* 1319 * 1320 * IOCTL 1321 * 1322 */ 1323 1324static void 1325cpsw_set_promisc(struct cpswp_softc *sc, int set) 1326{ 1327 uint32_t reg; 1328 1329 /* 1330 * Enabling promiscuous mode requires ALE_BYPASS to be enabled. 1331 * That disables the ALE forwarding logic and causes every 1332 * packet to be sent only to the host port. In bypass mode, 1333 * the ALE processes host port transmit packets the same as in 1334 * normal mode. 1335 */ 1336 reg = cpsw_read_4(sc->swsc, CPSW_ALE_CONTROL); 1337 reg &= ~CPSW_ALE_CTL_BYPASS; 1338 if (set) 1339 reg |= CPSW_ALE_CTL_BYPASS; 1340 cpsw_write_4(sc->swsc, CPSW_ALE_CONTROL, reg); 1341} 1342 1343static void 1344cpsw_set_allmulti(struct cpswp_softc *sc, int set) 1345{ 1346 if (set) { 1347 printf("All-multicast mode unimplemented\n"); 1348 } 1349} 1350 1351static int 1352cpswp_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1353{ 1354 struct cpswp_softc *sc; 1355 struct ifreq *ifr; 1356 int error; 1357 uint32_t changed; 1358 1359 error = 0; 1360 sc = ifp->if_softc; 1361 ifr = (struct ifreq *)data; 1362 1363 switch (command) { 1364 case SIOCSIFFLAGS: 1365 CPSW_PORT_LOCK(sc); 1366 if (ifp->if_flags & IFF_UP) { 1367 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1368 changed = ifp->if_flags ^ sc->if_flags; 1369 CPSWP_DEBUGF(sc, 1370 ("SIOCSIFFLAGS: UP & RUNNING (changed=0x%x)", 1371 changed)); 1372 if (changed & IFF_PROMISC) 1373 cpsw_set_promisc(sc, 1374 ifp->if_flags & IFF_PROMISC); 1375 if (changed & IFF_ALLMULTI) 1376 cpsw_set_allmulti(sc, 1377 ifp->if_flags & IFF_ALLMULTI); 1378 } else { 1379 CPSWP_DEBUGF(sc, 1380 ("SIOCSIFFLAGS: UP but not RUNNING; starting up")); 1381 cpswp_init_locked(sc); 1382 } 1383 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1384 CPSWP_DEBUGF(sc, 1385 ("SIOCSIFFLAGS: not UP but RUNNING; shutting down")); 1386 cpswp_stop_locked(sc); 1387 } 1388 1389 sc->if_flags = ifp->if_flags; 1390 CPSW_PORT_UNLOCK(sc); 1391 break; 1392 case SIOCADDMULTI: 1393 cpswp_ale_update_addresses(sc, 0); 1394 break; 1395 case SIOCDELMULTI: 1396 /* Ugh. DELMULTI doesn't provide the specific address 1397 being removed, so the best we can do is remove 1398 everything and rebuild it all. */ 1399 cpswp_ale_update_addresses(sc, 1); 1400 break; 1401 case SIOCGIFMEDIA: 1402 case SIOCSIFMEDIA: 1403 error = ifmedia_ioctl(ifp, ifr, &sc->mii->mii_media, command); 1404 break; 1405 default: 1406 error = ether_ioctl(ifp, command, data); 1407 } 1408 return (error); 1409} 1410 1411/* 1412 * 1413 * MIIBUS 1414 * 1415 */ 1416static int 1417cpswp_miibus_ready(struct cpsw_softc *sc, uint32_t reg) 1418{ 1419 uint32_t r, retries = CPSW_MIIBUS_RETRIES; 1420 1421 while (--retries) { 1422 r = cpsw_read_4(sc, reg); 1423 if ((r & MDIO_PHYACCESS_GO) == 0) 1424 return (1); 1425 DELAY(CPSW_MIIBUS_DELAY); 1426 } 1427 1428 return (0); 1429} 1430 1431static int 1432cpswp_miibus_readreg(device_t dev, int phy, int reg) 1433{ 1434 struct cpswp_softc *sc; 1435 uint32_t cmd, r; 1436 1437 sc = device_get_softc(dev); 1438 if (!cpswp_miibus_ready(sc->swsc, sc->phyaccess)) { 1439 device_printf(dev, "MDIO not ready to read\n"); 1440 return (0); 1441 } 1442 1443 /* Set GO, reg, phy */ 1444 cmd = MDIO_PHYACCESS_GO | (reg & 0x1F) << 21 | (phy & 0x1F) << 16; 1445 cpsw_write_4(sc->swsc, sc->phyaccess, cmd); 1446 1447 if (!cpswp_miibus_ready(sc->swsc, sc->phyaccess)) { 1448 device_printf(dev, "MDIO timed out during read\n"); 1449 return (0); 1450 } 1451 1452 r = cpsw_read_4(sc->swsc, sc->phyaccess); 1453 if ((r & MDIO_PHYACCESS_ACK) == 0) { 1454 device_printf(dev, "Failed to read from PHY.\n"); 1455 r = 0; 1456 } 1457 return (r & 0xFFFF); 1458} 1459 1460static int 1461cpswp_miibus_writereg(device_t dev, int phy, int reg, int value) 1462{ 1463 struct cpswp_softc *sc; 1464 uint32_t cmd; 1465 1466 sc = device_get_softc(dev); 1467 if (!cpswp_miibus_ready(sc->swsc, sc->phyaccess)) { 1468 device_printf(dev, "MDIO not ready to write\n"); 1469 return (0); 1470 } 1471 1472 /* Set GO, WRITE, reg, phy, and value */ 1473 cmd = MDIO_PHYACCESS_GO | MDIO_PHYACCESS_WRITE | 1474 (reg & 0x1F) << 21 | (phy & 0x1F) << 16 | (value & 0xFFFF); 1475 cpsw_write_4(sc->swsc, sc->phyaccess, cmd); 1476 1477 if (!cpswp_miibus_ready(sc->swsc, sc->phyaccess)) { 1478 device_printf(dev, "MDIO timed out during write\n"); 1479 return (0); 1480 } 1481 1482 if ((cpsw_read_4(sc->swsc, sc->phyaccess) & MDIO_PHYACCESS_ACK) == 0) 1483 device_printf(dev, "Failed to write to PHY.\n"); 1484 1485 return (0); 1486} 1487 1488static void 1489cpswp_miibus_statchg(device_t dev) 1490{ 1491 struct cpswp_softc *sc; 1492 uint32_t mac_control, reg; 1493 1494 sc = device_get_softc(dev); 1495 CPSWP_DEBUGF(sc, ("")); 1496 1497 reg = CPSW_SL_MACCONTROL(sc->unit); 1498 mac_control = cpsw_read_4(sc->swsc, reg); 1499 mac_control &= ~(CPSW_SL_MACTL_GIG | CPSW_SL_MACTL_IFCTL_A | 1500 CPSW_SL_MACTL_IFCTL_B | CPSW_SL_MACTL_FULLDUPLEX); 1501 1502 switch(IFM_SUBTYPE(sc->mii->mii_media_active)) { 1503 case IFM_1000_SX: 1504 case IFM_1000_LX: 1505 case IFM_1000_CX: 1506 case IFM_1000_T: 1507 mac_control |= CPSW_SL_MACTL_GIG; 1508 break; 1509 1510 case IFM_100_TX: 1511 mac_control |= CPSW_SL_MACTL_IFCTL_A; 1512 break; 1513 } 1514 if (sc->mii->mii_media_active & IFM_FDX) 1515 mac_control |= CPSW_SL_MACTL_FULLDUPLEX; 1516 1517 cpsw_write_4(sc->swsc, reg, mac_control); 1518} 1519 1520/* 1521 * 1522 * Transmit/Receive Packets. 1523 * 1524 */ 1525static void 1526cpsw_intr_rx(void *arg) 1527{ 1528 struct cpsw_softc *sc = arg; 1529 struct ifnet *ifp; 1530 struct mbuf *received, *next; 1531 1532 CPSW_RX_LOCK(sc); 1533 received = cpsw_rx_dequeue(sc); 1534 cpsw_rx_enqueue(sc); 1535 cpsw_write_4(sc, CPSW_CPDMA_CPDMA_EOI_VECTOR, 1); 1536 CPSW_RX_UNLOCK(sc); 1537 1538 while (received != NULL) { 1539 next = received->m_nextpkt; 1540 received->m_nextpkt = NULL; 1541 ifp = received->m_pkthdr.rcvif; 1542 (*ifp->if_input)(ifp, received); 1543 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 1544 received = next; 1545 } 1546} 1547 1548static struct mbuf * 1549cpsw_rx_dequeue(struct cpsw_softc *sc) 1550{ 1551 struct cpsw_cpdma_bd bd; 1552 struct cpsw_slot *slot; 1553 struct cpswp_softc *psc; 1554 struct mbuf *mb_head, *mb_tail; 1555 int port, removed = 0; 1556 1557 mb_head = mb_tail = NULL; 1558 1559 /* Pull completed packets off hardware RX queue. */ 1560 while ((slot = STAILQ_FIRST(&sc->rx.active)) != NULL) { 1561 cpsw_cpdma_read_bd(sc, slot, &bd); 1562 if (bd.flags & CPDMA_BD_OWNER) 1563 break; /* Still in use by hardware */ 1564 1565 CPSW_DEBUGF(sc, ("Removing received packet from RX queue")); 1566 ++removed; 1567 STAILQ_REMOVE_HEAD(&sc->rx.active, next); 1568 STAILQ_INSERT_TAIL(&sc->rx.avail, slot, next); 1569 1570 bus_dmamap_sync(sc->mbuf_dtag, slot->dmamap, BUS_DMASYNC_POSTREAD); 1571 bus_dmamap_unload(sc->mbuf_dtag, slot->dmamap); 1572 1573 if (bd.flags & CPDMA_BD_TDOWNCMPLT) { 1574 CPSW_DEBUGF(sc, ("RX teardown in progress")); 1575 m_freem(slot->mbuf); 1576 slot->mbuf = NULL; 1577 cpsw_write_cp(sc, &sc->rx, 0xfffffffc); 1578 sc->rx.running = 0; 1579 break; 1580 } 1581 1582 cpsw_write_cp_slot(sc, &sc->rx, slot); 1583 1584 port = (bd.flags & CPDMA_BD_PORT_MASK) - 1; 1585 KASSERT(port >= 0 && port <= 1, 1586 ("patcket received with invalid port: %d", port)); 1587 psc = device_get_softc(sc->port[port].dev); 1588 1589 /* Set up mbuf */ 1590 /* TODO: track SOP/EOP bits to assemble a full mbuf 1591 out of received fragments. */ 1592 slot->mbuf->m_data += bd.bufoff; 1593 slot->mbuf->m_len = bd.pktlen - 4; 1594 slot->mbuf->m_pkthdr.len = bd.pktlen - 4; 1595 slot->mbuf->m_flags |= M_PKTHDR; 1596 slot->mbuf->m_pkthdr.rcvif = psc->ifp; 1597 slot->mbuf->m_nextpkt = NULL; 1598 1599 if ((psc->ifp->if_capenable & IFCAP_RXCSUM) != 0) { 1600 /* check for valid CRC by looking into pkt_err[5:4] */ 1601 if ((bd.flags & CPDMA_BD_PKT_ERR_MASK) == 0) { 1602 slot->mbuf->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1603 slot->mbuf->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1604 slot->mbuf->m_pkthdr.csum_data = 0xffff; 1605 } 1606 } 1607 1608 /* Add mbuf to packet list to be returned. */ 1609 if (mb_tail) { 1610 mb_tail->m_nextpkt = slot->mbuf; 1611 } else { 1612 mb_head = slot->mbuf; 1613 } 1614 mb_tail = slot->mbuf; 1615 slot->mbuf = NULL; 1616 } 1617 1618 if (removed != 0) { 1619 sc->rx.queue_removes += removed; 1620 sc->rx.active_queue_len -= removed; 1621 sc->rx.avail_queue_len += removed; 1622 if (sc->rx.avail_queue_len > sc->rx.max_avail_queue_len) 1623 sc->rx.max_avail_queue_len = sc->rx.avail_queue_len; 1624 } 1625 return (mb_head); 1626} 1627 1628static void 1629cpsw_rx_enqueue(struct cpsw_softc *sc) 1630{ 1631 bus_dma_segment_t seg[1]; 1632 struct cpsw_cpdma_bd bd; 1633 struct cpsw_slots tmpqueue = STAILQ_HEAD_INITIALIZER(tmpqueue); 1634 struct cpsw_slot *slot, *prev_slot = NULL; 1635 struct cpsw_slot *last_old_slot, *first_new_slot; 1636 int error, nsegs, added = 0; 1637 1638 /* Register new mbufs with hardware. */ 1639 while ((slot = STAILQ_FIRST(&sc->rx.avail)) != NULL) { 1640 if (slot->mbuf == NULL) { 1641 slot->mbuf = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1642 if (slot->mbuf == NULL) { 1643 device_printf(sc->dev, 1644 "Unable to fill RX queue\n"); 1645 break; 1646 } 1647 slot->mbuf->m_len = 1648 slot->mbuf->m_pkthdr.len = 1649 slot->mbuf->m_ext.ext_size; 1650 } 1651 1652 error = bus_dmamap_load_mbuf_sg(sc->mbuf_dtag, slot->dmamap, 1653 slot->mbuf, seg, &nsegs, BUS_DMA_NOWAIT); 1654 1655 KASSERT(nsegs == 1, ("More than one segment (nsegs=%d)", nsegs)); 1656 KASSERT(error == 0, ("DMA error (error=%d)", error)); 1657 if (error != 0 || nsegs != 1) { 1658 device_printf(sc->dev, 1659 "%s: Can't prep RX buf for DMA (nsegs=%d, error=%d)\n", 1660 __func__, nsegs, error); 1661 bus_dmamap_unload(sc->mbuf_dtag, slot->dmamap); 1662 m_freem(slot->mbuf); 1663 slot->mbuf = NULL; 1664 break; 1665 } 1666 1667 bus_dmamap_sync(sc->mbuf_dtag, slot->dmamap, BUS_DMASYNC_PREREAD); 1668 1669 /* Create and submit new rx descriptor*/ 1670 bd.next = 0; 1671 bd.bufptr = seg->ds_addr; 1672 bd.bufoff = 0; 1673 bd.buflen = MCLBYTES - 1; 1674 bd.pktlen = bd.buflen; 1675 bd.flags = CPDMA_BD_OWNER; 1676 cpsw_cpdma_write_bd(sc, slot, &bd); 1677 ++added; 1678 1679 if (prev_slot != NULL) 1680 cpsw_cpdma_write_bd_next(sc, prev_slot, slot); 1681 prev_slot = slot; 1682 STAILQ_REMOVE_HEAD(&sc->rx.avail, next); 1683 sc->rx.avail_queue_len--; 1684 STAILQ_INSERT_TAIL(&tmpqueue, slot, next); 1685 } 1686 1687 if (added == 0) 1688 return; 1689 1690 CPSW_DEBUGF(sc, ("Adding %d buffers to RX queue", added)); 1691 1692 /* Link new entries to hardware RX queue. */ 1693 last_old_slot = STAILQ_LAST(&sc->rx.active, cpsw_slot, next); 1694 first_new_slot = STAILQ_FIRST(&tmpqueue); 1695 STAILQ_CONCAT(&sc->rx.active, &tmpqueue); 1696 if (first_new_slot == NULL) { 1697 return; 1698 } else if (last_old_slot == NULL) { 1699 /* Start a fresh queue. */ 1700 cpsw_write_hdp_slot(sc, &sc->rx, first_new_slot); 1701 } else { 1702 /* Add buffers to end of current queue. */ 1703 cpsw_cpdma_write_bd_next(sc, last_old_slot, first_new_slot); 1704 /* If underrun, restart queue. */ 1705 if (cpsw_cpdma_read_bd_flags(sc, last_old_slot) & CPDMA_BD_EOQ) { 1706 cpsw_write_hdp_slot(sc, &sc->rx, first_new_slot); 1707 } 1708 } 1709 sc->rx.queue_adds += added; 1710 sc->rx.active_queue_len += added; 1711 if (sc->rx.active_queue_len > sc->rx.max_active_queue_len) { 1712 sc->rx.max_active_queue_len = sc->rx.active_queue_len; 1713 } 1714} 1715 1716static void 1717cpswp_start(struct ifnet *ifp) 1718{ 1719 struct cpswp_softc *sc = ifp->if_softc; 1720 1721 CPSW_TX_LOCK(sc->swsc); 1722 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) && sc->swsc->tx.running) { 1723 cpswp_tx_enqueue(sc); 1724 cpsw_tx_dequeue(sc->swsc); 1725 } 1726 CPSW_TX_UNLOCK(sc->swsc); 1727} 1728 1729static void 1730cpswp_tx_enqueue(struct cpswp_softc *sc) 1731{ 1732 bus_dma_segment_t segs[CPSW_TXFRAGS]; 1733 struct cpsw_cpdma_bd bd; 1734 struct cpsw_slots tmpqueue = STAILQ_HEAD_INITIALIZER(tmpqueue); 1735 struct cpsw_slot *slot, *prev_slot = NULL; 1736 struct cpsw_slot *last_old_slot, *first_new_slot; 1737 struct mbuf *m0; 1738 int error, flags, nsegs, seg, added = 0, padlen; 1739 1740 flags = 0; 1741 if (sc->swsc->dualemac) { 1742 flags = CPDMA_BD_TO_PORT | 1743 ((sc->unit + 1) & CPDMA_BD_PORT_MASK); 1744 } 1745 /* Pull pending packets from IF queue and prep them for DMA. */ 1746 while ((slot = STAILQ_FIRST(&sc->swsc->tx.avail)) != NULL) { 1747 IF_DEQUEUE(&sc->ifp->if_snd, m0); 1748 if (m0 == NULL) 1749 break; 1750 1751 slot->mbuf = m0; 1752 padlen = ETHER_MIN_LEN - slot->mbuf->m_pkthdr.len; 1753 if (padlen < 0) 1754 padlen = 0; 1755 1756 /* Create mapping in DMA memory */ 1757 error = bus_dmamap_load_mbuf_sg(sc->swsc->mbuf_dtag, 1758 slot->dmamap, slot->mbuf, segs, &nsegs, BUS_DMA_NOWAIT); 1759 /* If the packet is too fragmented, try to simplify. */ 1760 if (error == EFBIG || 1761 (error == 0 && 1762 nsegs + (padlen > 0 ? 1 : 0) > sc->swsc->tx.avail_queue_len)) { 1763 bus_dmamap_unload(sc->swsc->mbuf_dtag, slot->dmamap); 1764 if (padlen > 0) /* May as well add padding. */ 1765 m_append(slot->mbuf, padlen, 1766 sc->swsc->null_mbuf->m_data); 1767 m0 = m_defrag(slot->mbuf, M_NOWAIT); 1768 if (m0 == NULL) { 1769 device_printf(sc->dev, 1770 "Can't defragment packet; dropping\n"); 1771 m_freem(slot->mbuf); 1772 } else { 1773 CPSWP_DEBUGF(sc, 1774 ("Requeueing defragmented packet")); 1775 IF_PREPEND(&sc->ifp->if_snd, m0); 1776 } 1777 slot->mbuf = NULL; 1778 continue; 1779 } 1780 if (error != 0) { 1781 device_printf(sc->dev, 1782 "%s: Can't setup DMA (error=%d), dropping packet\n", 1783 __func__, error); 1784 bus_dmamap_unload(sc->swsc->mbuf_dtag, slot->dmamap); 1785 m_freem(slot->mbuf); 1786 slot->mbuf = NULL; 1787 break; 1788 } 1789 1790 bus_dmamap_sync(sc->swsc->mbuf_dtag, slot->dmamap, 1791 BUS_DMASYNC_PREWRITE); 1792 1793 CPSWP_DEBUGF(sc, 1794 ("Queueing TX packet: %d segments + %d pad bytes", 1795 nsegs, padlen)); 1796 1797 slot->ifp = sc->ifp; 1798 /* If there is only one segment, the for() loop 1799 * gets skipped and the single buffer gets set up 1800 * as both SOP and EOP. */ 1801 /* Start by setting up the first buffer */ 1802 bd.next = 0; 1803 bd.bufptr = segs[0].ds_addr; 1804 bd.bufoff = 0; 1805 bd.buflen = segs[0].ds_len; 1806 bd.pktlen = m_length(slot->mbuf, NULL) + padlen; 1807 bd.flags = CPDMA_BD_SOP | CPDMA_BD_OWNER | flags; 1808 for (seg = 1; seg < nsegs; ++seg) { 1809 /* Save the previous buffer (which isn't EOP) */ 1810 cpsw_cpdma_write_bd(sc->swsc, slot, &bd); 1811 if (prev_slot != NULL) { 1812 cpsw_cpdma_write_bd_next(sc->swsc, prev_slot, 1813 slot); 1814 } 1815 prev_slot = slot; 1816 STAILQ_REMOVE_HEAD(&sc->swsc->tx.avail, next); 1817 sc->swsc->tx.avail_queue_len--; 1818 STAILQ_INSERT_TAIL(&tmpqueue, slot, next); 1819 ++added; 1820 slot = STAILQ_FIRST(&sc->swsc->tx.avail); 1821 1822 /* Setup next buffer (which isn't SOP) */ 1823 bd.next = 0; 1824 bd.bufptr = segs[seg].ds_addr; 1825 bd.bufoff = 0; 1826 bd.buflen = segs[seg].ds_len; 1827 bd.pktlen = 0; 1828 bd.flags = CPDMA_BD_OWNER | flags; 1829 } 1830 /* Save the final buffer. */ 1831 if (padlen <= 0) 1832 bd.flags |= CPDMA_BD_EOP; 1833 cpsw_cpdma_write_bd(sc->swsc, slot, &bd); 1834 if (prev_slot != NULL) 1835 cpsw_cpdma_write_bd_next(sc->swsc, prev_slot, slot); 1836 prev_slot = slot; 1837 STAILQ_REMOVE_HEAD(&sc->swsc->tx.avail, next); 1838 sc->swsc->tx.avail_queue_len--; 1839 STAILQ_INSERT_TAIL(&tmpqueue, slot, next); 1840 ++added; 1841 1842 if (padlen > 0) { 1843 slot = STAILQ_FIRST(&sc->swsc->tx.avail); 1844 STAILQ_REMOVE_HEAD(&sc->swsc->tx.avail, next); 1845 sc->swsc->tx.avail_queue_len--; 1846 STAILQ_INSERT_TAIL(&tmpqueue, slot, next); 1847 ++added; 1848 1849 /* Setup buffer of null pad bytes (definitely EOP) */ 1850 cpsw_cpdma_write_bd_next(sc->swsc, prev_slot, slot); 1851 prev_slot = slot; 1852 bd.next = 0; 1853 bd.bufptr = sc->swsc->null_mbuf_paddr; 1854 bd.bufoff = 0; 1855 bd.buflen = padlen; 1856 bd.pktlen = 0; 1857 bd.flags = CPDMA_BD_EOP | CPDMA_BD_OWNER | flags; 1858 cpsw_cpdma_write_bd(sc->swsc, slot, &bd); 1859 ++nsegs; 1860 } 1861 1862 if (nsegs > sc->swsc->tx.longest_chain) 1863 sc->swsc->tx.longest_chain = nsegs; 1864 1865 // TODO: Should we defer the BPF tap until 1866 // after all packets are queued? 1867 BPF_MTAP(sc->ifp, m0); 1868 } 1869 1870 /* Attach the list of new buffers to the hardware TX queue. */ 1871 last_old_slot = STAILQ_LAST(&sc->swsc->tx.active, cpsw_slot, next); 1872 first_new_slot = STAILQ_FIRST(&tmpqueue); 1873 STAILQ_CONCAT(&sc->swsc->tx.active, &tmpqueue); 1874 if (first_new_slot == NULL) { 1875 return; 1876 } else if (last_old_slot == NULL) { 1877 /* Start a fresh queue. */ 1878 sc->swsc->last_hdp = cpsw_cpdma_bd_paddr(sc->swsc, first_new_slot); 1879 cpsw_write_hdp_slot(sc->swsc, &sc->swsc->tx, first_new_slot); 1880 } else { 1881 /* Add buffers to end of current queue. */ 1882 cpsw_cpdma_write_bd_next(sc->swsc, last_old_slot, 1883 first_new_slot); 1884 /* If underrun, restart queue. */ 1885 if (cpsw_cpdma_read_bd_flags(sc->swsc, last_old_slot) & 1886 CPDMA_BD_EOQ) { 1887 sc->swsc->last_hdp = cpsw_cpdma_bd_paddr(sc->swsc, first_new_slot); 1888 cpsw_write_hdp_slot(sc->swsc, &sc->swsc->tx, 1889 first_new_slot); 1890 } 1891 } 1892 sc->swsc->tx.queue_adds += added; 1893 sc->swsc->tx.active_queue_len += added; 1894 if (sc->swsc->tx.active_queue_len > sc->swsc->tx.max_active_queue_len) { 1895 sc->swsc->tx.max_active_queue_len = sc->swsc->tx.active_queue_len; 1896 } 1897} 1898 1899static int 1900cpsw_tx_dequeue(struct cpsw_softc *sc) 1901{ 1902 struct cpsw_slot *slot, *last_removed_slot = NULL; 1903 struct cpsw_cpdma_bd bd; 1904 uint32_t flags, removed = 0; 1905 1906 slot = STAILQ_FIRST(&sc->tx.active); 1907 if (slot == NULL && cpsw_read_cp(sc, &sc->tx) == 0xfffffffc) { 1908 CPSW_DEBUGF(sc, ("TX teardown of an empty queue")); 1909 cpsw_write_cp(sc, &sc->tx, 0xfffffffc); 1910 sc->tx.running = 0; 1911 return (0); 1912 } 1913 1914 /* Pull completed buffers off the hardware TX queue. */ 1915 while (slot != NULL) { 1916 flags = cpsw_cpdma_read_bd_flags(sc, slot); 1917 if (flags & CPDMA_BD_OWNER) 1918 break; /* Hardware is still using this packet. */ 1919 1920 CPSW_DEBUGF(sc, ("TX removing completed packet")); 1921 bus_dmamap_sync(sc->mbuf_dtag, slot->dmamap, BUS_DMASYNC_POSTWRITE); 1922 bus_dmamap_unload(sc->mbuf_dtag, slot->dmamap); 1923 m_freem(slot->mbuf); 1924 slot->mbuf = NULL; 1925 if (slot->ifp) 1926 if_inc_counter(slot->ifp, IFCOUNTER_OPACKETS, 1); 1927 1928 /* Dequeue any additional buffers used by this packet. */ 1929 while (slot != NULL && slot->mbuf == NULL) { 1930 STAILQ_REMOVE_HEAD(&sc->tx.active, next); 1931 STAILQ_INSERT_TAIL(&sc->tx.avail, slot, next); 1932 ++removed; 1933 last_removed_slot = slot; 1934 slot = STAILQ_FIRST(&sc->tx.active); 1935 } 1936 1937 /* TearDown complete is only marked on the SOP for the packet. */ 1938 if ((flags & (CPDMA_BD_SOP | CPDMA_BD_TDOWNCMPLT)) == 1939 (CPDMA_BD_EOP | CPDMA_BD_TDOWNCMPLT)) { 1940 CPSW_DEBUGF(sc, ("TX teardown in progress")); 1941 cpsw_write_cp(sc, &sc->tx, 0xfffffffc); 1942 // TODO: Increment a count of dropped TX packets 1943 sc->tx.running = 0; 1944 break; 1945 } 1946 1947 if ((flags & CPDMA_BD_EOP) == 0) 1948 flags = cpsw_cpdma_read_bd_flags(sc, last_removed_slot); 1949 if ((flags & (CPDMA_BD_EOP | CPDMA_BD_EOQ)) == 1950 (CPDMA_BD_EOP | CPDMA_BD_EOQ)) { 1951 cpsw_cpdma_read_bd(sc, last_removed_slot, &bd); 1952 if (bd.next != 0 && bd.next != sc->last_hdp) { 1953 /* Restart the queue. */ 1954 sc->last_hdp = bd.next; 1955 cpsw_write_4(sc, sc->tx.hdp_offset, bd.next); 1956 } 1957 } 1958 } 1959 1960 if (removed != 0) { 1961 cpsw_write_cp_slot(sc, &sc->tx, last_removed_slot); 1962 sc->tx.queue_removes += removed; 1963 sc->tx.active_queue_len -= removed; 1964 sc->tx.avail_queue_len += removed; 1965 if (sc->tx.avail_queue_len > sc->tx.max_avail_queue_len) 1966 sc->tx.max_avail_queue_len = sc->tx.avail_queue_len; 1967 } 1968 return (removed); 1969} 1970 1971/* 1972 * 1973 * Miscellaneous interrupts. 1974 * 1975 */ 1976 1977static void 1978cpsw_intr_rx_thresh(void *arg) 1979{ 1980 struct cpsw_softc *sc = arg; 1981 uint32_t stat = cpsw_read_4(sc, CPSW_WR_C_RX_THRESH_STAT(0)); 1982 1983 CPSW_DEBUGF(sc, ("stat=%x", stat)); 1984 cpsw_write_4(sc, CPSW_CPDMA_CPDMA_EOI_VECTOR, 0); 1985} 1986 1987static void 1988cpsw_intr_misc_host_error(struct cpsw_softc *sc) 1989{ 1990 uint32_t intstat; 1991 uint32_t dmastat; 1992 int txerr, rxerr, txchan, rxchan; 1993 1994 printf("\n\n"); 1995 device_printf(sc->dev, 1996 "HOST ERROR: PROGRAMMING ERROR DETECTED BY HARDWARE\n"); 1997 printf("\n\n"); 1998 intstat = cpsw_read_4(sc, CPSW_CPDMA_DMA_INTSTAT_MASKED); 1999 device_printf(sc->dev, "CPSW_CPDMA_DMA_INTSTAT_MASKED=0x%x\n", intstat); 2000 dmastat = cpsw_read_4(sc, CPSW_CPDMA_DMASTATUS); 2001 device_printf(sc->dev, "CPSW_CPDMA_DMASTATUS=0x%x\n", dmastat); 2002 2003 txerr = (dmastat >> 20) & 15; 2004 txchan = (dmastat >> 16) & 7; 2005 rxerr = (dmastat >> 12) & 15; 2006 rxchan = (dmastat >> 8) & 7; 2007 2008 switch (txerr) { 2009 case 0: break; 2010 case 1: printf("SOP error on TX channel %d\n", txchan); 2011 break; 2012 case 2: printf("Ownership bit not set on SOP buffer on TX channel %d\n", txchan); 2013 break; 2014 case 3: printf("Zero Next Buffer but not EOP on TX channel %d\n", txchan); 2015 break; 2016 case 4: printf("Zero Buffer Pointer on TX channel %d\n", txchan); 2017 break; 2018 case 5: printf("Zero Buffer Length on TX channel %d\n", txchan); 2019 break; 2020 case 6: printf("Packet length error on TX channel %d\n", txchan); 2021 break; 2022 default: printf("Unknown error on TX channel %d\n", txchan); 2023 break; 2024 } 2025 2026 if (txerr != 0) { 2027 printf("CPSW_CPDMA_TX%d_HDP=0x%x\n", 2028 txchan, cpsw_read_4(sc, CPSW_CPDMA_TX_HDP(txchan))); 2029 printf("CPSW_CPDMA_TX%d_CP=0x%x\n", 2030 txchan, cpsw_read_4(sc, CPSW_CPDMA_TX_CP(txchan))); 2031 cpsw_dump_queue(sc, &sc->tx.active); 2032 } 2033 2034 switch (rxerr) { 2035 case 0: break; 2036 case 2: printf("Ownership bit not set on RX channel %d\n", rxchan); 2037 break; 2038 case 4: printf("Zero Buffer Pointer on RX channel %d\n", rxchan); 2039 break; 2040 case 5: printf("Zero Buffer Length on RX channel %d\n", rxchan); 2041 break; 2042 case 6: printf("Buffer offset too big on RX channel %d\n", rxchan); 2043 break; 2044 default: printf("Unknown RX error on RX channel %d\n", rxchan); 2045 break; 2046 } 2047 2048 if (rxerr != 0) { 2049 printf("CPSW_CPDMA_RX%d_HDP=0x%x\n", 2050 rxchan, cpsw_read_4(sc,CPSW_CPDMA_RX_HDP(rxchan))); 2051 printf("CPSW_CPDMA_RX%d_CP=0x%x\n", 2052 rxchan, cpsw_read_4(sc, CPSW_CPDMA_RX_CP(rxchan))); 2053 cpsw_dump_queue(sc, &sc->rx.active); 2054 } 2055 2056 printf("\nALE Table\n"); 2057 cpsw_ale_dump_table(sc); 2058 2059 // XXX do something useful here?? 2060 panic("CPSW HOST ERROR INTERRUPT"); 2061 2062 // Suppress this interrupt in the future. 2063 cpsw_write_4(sc, CPSW_CPDMA_DMA_INTMASK_CLEAR, intstat); 2064 printf("XXX HOST ERROR INTERRUPT SUPPRESSED\n"); 2065 // The watchdog will probably reset the controller 2066 // in a little while. It will probably fail again. 2067} 2068 2069static void 2070cpsw_intr_misc(void *arg) 2071{ 2072 struct cpsw_softc *sc = arg; 2073 uint32_t stat = cpsw_read_4(sc, CPSW_WR_C_MISC_STAT(0)); 2074 2075 if (stat & CPSW_WR_C_MISC_EVNT_PEND) 2076 CPSW_DEBUGF(sc, ("Time sync event interrupt unimplemented")); 2077 if (stat & CPSW_WR_C_MISC_STAT_PEND) 2078 cpsw_stats_collect(sc); 2079 if (stat & CPSW_WR_C_MISC_HOST_PEND) 2080 cpsw_intr_misc_host_error(sc); 2081 if (stat & CPSW_WR_C_MISC_MDIOLINK) { 2082 cpsw_write_4(sc, MDIOLINKINTMASKED, 2083 cpsw_read_4(sc, MDIOLINKINTMASKED)); 2084 } 2085 if (stat & CPSW_WR_C_MISC_MDIOUSER) { 2086 CPSW_DEBUGF(sc, 2087 ("MDIO operation completed interrupt unimplemented")); 2088 } 2089 cpsw_write_4(sc, CPSW_CPDMA_CPDMA_EOI_VECTOR, 3); 2090} 2091 2092/* 2093 * 2094 * Periodic Checks and Watchdog. 2095 * 2096 */ 2097 2098static void 2099cpswp_tick(void *msc) 2100{ 2101 struct cpswp_softc *sc = msc; 2102 2103 /* Check for media type change */ 2104 mii_tick(sc->mii); 2105 if (sc->media_status != sc->mii->mii_media.ifm_media) { 2106 printf("%s: media type changed (ifm_media=%x)\n", __func__, 2107 sc->mii->mii_media.ifm_media); 2108 cpswp_ifmedia_upd(sc->ifp); 2109 } 2110 2111 /* Schedule another timeout one second from now */ 2112 callout_reset(&sc->mii_callout, hz, cpswp_tick, sc); 2113} 2114 2115static void 2116cpswp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2117{ 2118 struct cpswp_softc *sc; 2119 struct mii_data *mii; 2120 2121 sc = ifp->if_softc; 2122 CPSWP_DEBUGF(sc, ("")); 2123 CPSW_PORT_LOCK(sc); 2124 2125 mii = sc->mii; 2126 mii_pollstat(mii); 2127 2128 ifmr->ifm_active = mii->mii_media_active; 2129 ifmr->ifm_status = mii->mii_media_status; 2130 CPSW_PORT_UNLOCK(sc); 2131} 2132 2133static int 2134cpswp_ifmedia_upd(struct ifnet *ifp) 2135{ 2136 struct cpswp_softc *sc; 2137 2138 sc = ifp->if_softc; 2139 CPSWP_DEBUGF(sc, ("")); 2140 CPSW_PORT_LOCK(sc); 2141 mii_mediachg(sc->mii); 2142 sc->media_status = sc->mii->mii_media.ifm_media; 2143 CPSW_PORT_UNLOCK(sc); 2144 2145 return (0); 2146} 2147 2148static void 2149cpsw_tx_watchdog_full_reset(struct cpsw_softc *sc) 2150{ 2151 struct cpswp_softc *psc; 2152 int i; 2153 2154 cpsw_debugf_head("CPSW watchdog"); 2155 device_printf(sc->dev, "watchdog timeout\n"); 2156 for (i = 0; i < CPSW_PORTS; i++) { 2157 if (!sc->dualemac && i != sc->active_slave) 2158 continue; 2159 psc = device_get_softc(sc->port[i].dev); 2160 CPSW_PORT_LOCK(psc); 2161 cpswp_stop_locked(psc); 2162 CPSW_PORT_UNLOCK(psc); 2163 } 2164} 2165 2166static void 2167cpsw_tx_watchdog(void *msc) 2168{ 2169 struct cpsw_softc *sc; 2170 2171 sc = msc; 2172 CPSW_GLOBAL_LOCK(sc); 2173 if (sc->tx.active_queue_len == 0 || !sc->tx.running) { 2174 sc->watchdog.timer = 0; /* Nothing to do. */ 2175 } else if (sc->tx.queue_removes > sc->tx.queue_removes_at_last_tick) { 2176 sc->watchdog.timer = 0; /* Stuff done while we weren't looking. */ 2177 } else if (cpsw_tx_dequeue(sc) > 0) { 2178 sc->watchdog.timer = 0; /* We just did something. */ 2179 } else { 2180 /* There was something to do but it didn't get done. */ 2181 ++sc->watchdog.timer; 2182 if (sc->watchdog.timer > 5) { 2183 sc->watchdog.timer = 0; 2184 ++sc->watchdog.resets; 2185 cpsw_tx_watchdog_full_reset(sc); 2186 } 2187 } 2188 sc->tx.queue_removes_at_last_tick = sc->tx.queue_removes; 2189 CPSW_GLOBAL_UNLOCK(sc); 2190 2191 /* Schedule another timeout one second from now */ 2192 callout_reset(&sc->watchdog.callout, hz, cpsw_tx_watchdog, sc); 2193} 2194 2195/* 2196 * 2197 * ALE support routines. 2198 * 2199 */ 2200 2201static void 2202cpsw_ale_read_entry(struct cpsw_softc *sc, uint16_t idx, uint32_t *ale_entry) 2203{ 2204 cpsw_write_4(sc, CPSW_ALE_TBLCTL, idx & 1023); 2205 ale_entry[0] = cpsw_read_4(sc, CPSW_ALE_TBLW0); 2206 ale_entry[1] = cpsw_read_4(sc, CPSW_ALE_TBLW1); 2207 ale_entry[2] = cpsw_read_4(sc, CPSW_ALE_TBLW2); 2208} 2209 2210static void 2211cpsw_ale_write_entry(struct cpsw_softc *sc, uint16_t idx, uint32_t *ale_entry) 2212{ 2213 cpsw_write_4(sc, CPSW_ALE_TBLW0, ale_entry[0]); 2214 cpsw_write_4(sc, CPSW_ALE_TBLW1, ale_entry[1]); 2215 cpsw_write_4(sc, CPSW_ALE_TBLW2, ale_entry[2]); 2216 cpsw_write_4(sc, CPSW_ALE_TBLCTL, 1 << 31 | (idx & 1023)); 2217} 2218 2219static void 2220cpsw_ale_remove_all_mc_entries(struct cpsw_softc *sc) 2221{ 2222 int i; 2223 uint32_t ale_entry[3]; 2224 2225 /* First four entries are link address and broadcast. */ 2226 for (i = 10; i < CPSW_MAX_ALE_ENTRIES; i++) { 2227 cpsw_ale_read_entry(sc, i, ale_entry); 2228 if ((ALE_TYPE(ale_entry) == ALE_TYPE_ADDR || 2229 ALE_TYPE(ale_entry) == ALE_TYPE_VLAN_ADDR) && 2230 ALE_MCAST(ale_entry) == 1) { /* MCast link addr */ 2231 ale_entry[0] = ale_entry[1] = ale_entry[2] = 0; 2232 cpsw_ale_write_entry(sc, i, ale_entry); 2233 } 2234 } 2235} 2236 2237static int 2238cpsw_ale_mc_entry_set(struct cpsw_softc *sc, uint8_t portmap, int vlan, 2239 uint8_t *mac) 2240{ 2241 int free_index = -1, matching_index = -1, i; 2242 uint32_t ale_entry[3], ale_type; 2243 2244 /* Find a matching entry or a free entry. */ 2245 for (i = 10; i < CPSW_MAX_ALE_ENTRIES; i++) { 2246 cpsw_ale_read_entry(sc, i, ale_entry); 2247 2248 /* Entry Type[61:60] is 0 for free entry */ 2249 if (free_index < 0 && ALE_TYPE(ale_entry) == 0) 2250 free_index = i; 2251 2252 if ((((ale_entry[1] >> 8) & 0xFF) == mac[0]) && 2253 (((ale_entry[1] >> 0) & 0xFF) == mac[1]) && 2254 (((ale_entry[0] >>24) & 0xFF) == mac[2]) && 2255 (((ale_entry[0] >>16) & 0xFF) == mac[3]) && 2256 (((ale_entry[0] >> 8) & 0xFF) == mac[4]) && 2257 (((ale_entry[0] >> 0) & 0xFF) == mac[5])) { 2258 matching_index = i; 2259 break; 2260 } 2261 } 2262 2263 if (matching_index < 0) { 2264 if (free_index < 0) 2265 return (ENOMEM); 2266 i = free_index; 2267 } 2268 2269 if (vlan != -1) 2270 ale_type = ALE_TYPE_VLAN_ADDR << 28 | vlan << 16; 2271 else 2272 ale_type = ALE_TYPE_ADDR << 28; 2273 2274 /* Set MAC address */ 2275 ale_entry[0] = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5]; 2276 ale_entry[1] = mac[0] << 8 | mac[1]; 2277 2278 /* Entry type[61:60] and Mcast fwd state[63:62] is fw(3). */ 2279 ale_entry[1] |= ALE_MCAST_FWD | ale_type; 2280 2281 /* Set portmask [68:66] */ 2282 ale_entry[2] = (portmap & 7) << 2; 2283 2284 cpsw_ale_write_entry(sc, i, ale_entry); 2285 2286 return 0; 2287} 2288 2289static void 2290cpsw_ale_dump_table(struct cpsw_softc *sc) { 2291 int i; 2292 uint32_t ale_entry[3]; 2293 for (i = 0; i < CPSW_MAX_ALE_ENTRIES; i++) { 2294 cpsw_ale_read_entry(sc, i, ale_entry); 2295 switch (ALE_TYPE(ale_entry)) { 2296 case ALE_TYPE_VLAN: 2297 printf("ALE[%4u] %08x %08x %08x ", i, ale_entry[2], 2298 ale_entry[1], ale_entry[0]); 2299 printf("type: %u ", ALE_TYPE(ale_entry)); 2300 printf("vlan: %u ", ALE_VLAN(ale_entry)); 2301 printf("untag: %u ", ALE_VLAN_UNTAG(ale_entry)); 2302 printf("reg flood: %u ", ALE_VLAN_REGFLOOD(ale_entry)); 2303 printf("unreg flood: %u ", ALE_VLAN_UNREGFLOOD(ale_entry)); 2304 printf("members: %u ", ALE_VLAN_MEMBERS(ale_entry)); 2305 printf("\n"); 2306 break; 2307 case ALE_TYPE_ADDR: 2308 case ALE_TYPE_VLAN_ADDR: 2309 printf("ALE[%4u] %08x %08x %08x ", i, ale_entry[2], 2310 ale_entry[1], ale_entry[0]); 2311 printf("type: %u ", ALE_TYPE(ale_entry)); 2312 printf("mac: %02x:%02x:%02x:%02x:%02x:%02x ", 2313 (ale_entry[1] >> 8) & 0xFF, 2314 (ale_entry[1] >> 0) & 0xFF, 2315 (ale_entry[0] >>24) & 0xFF, 2316 (ale_entry[0] >>16) & 0xFF, 2317 (ale_entry[0] >> 8) & 0xFF, 2318 (ale_entry[0] >> 0) & 0xFF); 2319 printf(ALE_MCAST(ale_entry) ? "mcast " : "ucast "); 2320 if (ALE_TYPE(ale_entry) == ALE_TYPE_VLAN_ADDR) 2321 printf("vlan: %u ", ALE_VLAN(ale_entry)); 2322 printf("port: %u ", ALE_PORTS(ale_entry)); 2323 printf("\n"); 2324 break; 2325 } 2326 } 2327 printf("\n"); 2328} 2329 2330static int 2331cpswp_ale_update_addresses(struct cpswp_softc *sc, int purge) 2332{ 2333 uint8_t *mac; 2334 uint32_t ale_entry[3], ale_type, portmask; 2335 struct ifmultiaddr *ifma; 2336 2337 if (sc->swsc->dualemac) { 2338 ale_type = ALE_TYPE_VLAN_ADDR << 28 | sc->vlan << 16; 2339 portmask = 1 << (sc->unit + 1) | 1 << 0; 2340 } else { 2341 ale_type = ALE_TYPE_ADDR << 28; 2342 portmask = 7; 2343 } 2344 2345 /* 2346 * Route incoming packets for our MAC address to Port 0 (host). 2347 * For simplicity, keep this entry at table index 0 for port 1 and 2348 * at index 2 for port 2 in the ALE. 2349 */ 2350 if_addr_rlock(sc->ifp); 2351 mac = LLADDR((struct sockaddr_dl *)sc->ifp->if_addr->ifa_addr); 2352 ale_entry[0] = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5]; 2353 ale_entry[1] = ale_type | mac[0] << 8 | mac[1]; /* addr entry + mac */ 2354 ale_entry[2] = 0; /* port = 0 */ 2355 cpsw_ale_write_entry(sc->swsc, 0 + 2 * sc->unit, ale_entry); 2356 2357 /* Set outgoing MAC Address for slave port. */ 2358 cpsw_write_4(sc->swsc, CPSW_PORT_P_SA_HI(sc->unit + 1), 2359 mac[3] << 24 | mac[2] << 16 | mac[1] << 8 | mac[0]); 2360 cpsw_write_4(sc->swsc, CPSW_PORT_P_SA_LO(sc->unit + 1), 2361 mac[5] << 8 | mac[4]); 2362 if_addr_runlock(sc->ifp); 2363 2364 /* Keep the broadcast address at table entry 1 (or 3). */ 2365 ale_entry[0] = 0xffffffff; /* Lower 32 bits of MAC */ 2366 /* ALE_MCAST_FWD, Addr type, upper 16 bits of Mac */ 2367 ale_entry[1] = ALE_MCAST_FWD | ale_type | 0xffff; 2368 ale_entry[2] = portmask << 2; 2369 cpsw_ale_write_entry(sc->swsc, 1 + 2 * sc->unit, ale_entry); 2370 2371 /* SIOCDELMULTI doesn't specify the particular address 2372 being removed, so we have to remove all and rebuild. */ 2373 if (purge) 2374 cpsw_ale_remove_all_mc_entries(sc->swsc); 2375 2376 /* Set other multicast addrs desired. */ 2377 if_maddr_rlock(sc->ifp); 2378 TAILQ_FOREACH(ifma, &sc->ifp->if_multiaddrs, ifma_link) { 2379 if (ifma->ifma_addr->sa_family != AF_LINK) 2380 continue; 2381 cpsw_ale_mc_entry_set(sc->swsc, portmask, sc->vlan, 2382 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 2383 } 2384 if_maddr_runlock(sc->ifp); 2385 2386 return (0); 2387} 2388 2389static int 2390cpsw_ale_update_vlan_table(struct cpsw_softc *sc, int vlan, int ports, 2391 int untag, int mcregflood, int mcunregflood) 2392{ 2393 int free_index, i, matching_index; 2394 uint32_t ale_entry[3]; 2395 2396 free_index = matching_index = -1; 2397 /* Find a matching entry or a free entry. */ 2398 for (i = 5; i < CPSW_MAX_ALE_ENTRIES; i++) { 2399 cpsw_ale_read_entry(sc, i, ale_entry); 2400 2401 /* Entry Type[61:60] is 0 for free entry */ 2402 if (free_index < 0 && ALE_TYPE(ale_entry) == 0) 2403 free_index = i; 2404 2405 if (ALE_VLAN(ale_entry) == vlan) { 2406 matching_index = i; 2407 break; 2408 } 2409 } 2410 2411 if (matching_index < 0) { 2412 if (free_index < 0) 2413 return (-1); 2414 i = free_index; 2415 } 2416 2417 ale_entry[0] = (untag & 7) << 24 | (mcregflood & 7) << 16 | 2418 (mcunregflood & 7) << 8 | (ports & 7); 2419 ale_entry[1] = ALE_TYPE_VLAN << 28 | vlan << 16; 2420 ale_entry[2] = 0; 2421 cpsw_ale_write_entry(sc, i, ale_entry); 2422 2423 return (0); 2424} 2425 2426/* 2427 * 2428 * Statistics and Sysctls. 2429 * 2430 */ 2431 2432#if 0 2433static void 2434cpsw_stats_dump(struct cpsw_softc *sc) 2435{ 2436 int i; 2437 uint32_t r; 2438 2439 for (i = 0; i < CPSW_SYSCTL_COUNT; ++i) { 2440 r = cpsw_read_4(sc, CPSW_STATS_OFFSET + 2441 cpsw_stat_sysctls[i].reg); 2442 CPSW_DEBUGF(sc, ("%s: %ju + %u = %ju", cpsw_stat_sysctls[i].oid, 2443 (intmax_t)sc->shadow_stats[i], r, 2444 (intmax_t)sc->shadow_stats[i] + r)); 2445 } 2446} 2447#endif 2448 2449static void 2450cpsw_stats_collect(struct cpsw_softc *sc) 2451{ 2452 int i; 2453 uint32_t r; 2454 2455 CPSW_DEBUGF(sc, ("Controller shadow statistics updated.")); 2456 2457 for (i = 0; i < CPSW_SYSCTL_COUNT; ++i) { 2458 r = cpsw_read_4(sc, CPSW_STATS_OFFSET + 2459 cpsw_stat_sysctls[i].reg); 2460 sc->shadow_stats[i] += r; 2461 cpsw_write_4(sc, CPSW_STATS_OFFSET + cpsw_stat_sysctls[i].reg, 2462 r); 2463 } 2464} 2465 2466static int 2467cpsw_stats_sysctl(SYSCTL_HANDLER_ARGS) 2468{ 2469 struct cpsw_softc *sc; 2470 struct cpsw_stat *stat; 2471 uint64_t result; 2472 2473 sc = (struct cpsw_softc *)arg1; 2474 stat = &cpsw_stat_sysctls[oidp->oid_number]; 2475 result = sc->shadow_stats[oidp->oid_number]; 2476 result += cpsw_read_4(sc, CPSW_STATS_OFFSET + stat->reg); 2477 return (sysctl_handle_64(oidp, &result, 0, req)); 2478} 2479 2480static int 2481cpsw_stat_attached(SYSCTL_HANDLER_ARGS) 2482{ 2483 struct cpsw_softc *sc; 2484 struct bintime t; 2485 unsigned result; 2486 2487 sc = (struct cpsw_softc *)arg1; 2488 getbinuptime(&t); 2489 bintime_sub(&t, &sc->attach_uptime); 2490 result = t.sec; 2491 return (sysctl_handle_int(oidp, &result, 0, req)); 2492} 2493 2494static int 2495cpsw_stat_uptime(SYSCTL_HANDLER_ARGS) 2496{ 2497 struct cpsw_softc *swsc; 2498 struct cpswp_softc *sc; 2499 struct bintime t; 2500 unsigned result; 2501 2502 swsc = arg1; 2503 sc = device_get_softc(swsc->port[arg2].dev); 2504 if (sc->ifp->if_drv_flags & IFF_DRV_RUNNING) { 2505 getbinuptime(&t); 2506 bintime_sub(&t, &sc->init_uptime); 2507 result = t.sec; 2508 } else 2509 result = 0; 2510 return (sysctl_handle_int(oidp, &result, 0, req)); 2511} 2512 2513static void 2514cpsw_add_queue_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *node, 2515 struct cpsw_queue *queue) 2516{ 2517 struct sysctl_oid_list *parent; 2518 2519 parent = SYSCTL_CHILDREN(node); 2520 SYSCTL_ADD_INT(ctx, parent, OID_AUTO, "totalBuffers", 2521 CTLFLAG_RD, &queue->queue_slots, 0, 2522 "Total buffers currently assigned to this queue"); 2523 SYSCTL_ADD_INT(ctx, parent, OID_AUTO, "activeBuffers", 2524 CTLFLAG_RD, &queue->active_queue_len, 0, 2525 "Buffers currently registered with hardware controller"); 2526 SYSCTL_ADD_INT(ctx, parent, OID_AUTO, "maxActiveBuffers", 2527 CTLFLAG_RD, &queue->max_active_queue_len, 0, 2528 "Max value of activeBuffers since last driver reset"); 2529 SYSCTL_ADD_INT(ctx, parent, OID_AUTO, "availBuffers", 2530 CTLFLAG_RD, &queue->avail_queue_len, 0, 2531 "Buffers allocated to this queue but not currently " 2532 "registered with hardware controller"); 2533 SYSCTL_ADD_INT(ctx, parent, OID_AUTO, "maxAvailBuffers", 2534 CTLFLAG_RD, &queue->max_avail_queue_len, 0, 2535 "Max value of availBuffers since last driver reset"); 2536 SYSCTL_ADD_UINT(ctx, parent, OID_AUTO, "totalEnqueued", 2537 CTLFLAG_RD, &queue->queue_adds, 0, 2538 "Total buffers added to queue"); 2539 SYSCTL_ADD_UINT(ctx, parent, OID_AUTO, "totalDequeued", 2540 CTLFLAG_RD, &queue->queue_removes, 0, 2541 "Total buffers removed from queue"); 2542 SYSCTL_ADD_UINT(ctx, parent, OID_AUTO, "longestChain", 2543 CTLFLAG_RD, &queue->longest_chain, 0, 2544 "Max buffers used for a single packet"); 2545} 2546 2547static void 2548cpsw_add_watchdog_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *node, 2549 struct cpsw_softc *sc) 2550{ 2551 struct sysctl_oid_list *parent; 2552 2553 parent = SYSCTL_CHILDREN(node); 2554 SYSCTL_ADD_INT(ctx, parent, OID_AUTO, "resets", 2555 CTLFLAG_RD, &sc->watchdog.resets, 0, 2556 "Total number of watchdog resets"); 2557} 2558 2559static void 2560cpsw_add_sysctls(struct cpsw_softc *sc) 2561{ 2562 struct sysctl_ctx_list *ctx; 2563 struct sysctl_oid *stats_node, *queue_node, *node; 2564 struct sysctl_oid_list *parent, *stats_parent, *queue_parent; 2565 struct sysctl_oid_list *ports_parent, *port_parent; 2566 char port[16]; 2567 int i; 2568 2569 ctx = device_get_sysctl_ctx(sc->dev); 2570 parent = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)); 2571 2572 SYSCTL_ADD_INT(ctx, parent, OID_AUTO, "debug", 2573 CTLFLAG_RW, &sc->debug, 0, "Enable switch debug messages"); 2574 2575 SYSCTL_ADD_PROC(ctx, parent, OID_AUTO, "attachedSecs", 2576 CTLTYPE_UINT | CTLFLAG_RD, sc, 0, cpsw_stat_attached, "IU", 2577 "Time since driver attach"); 2578 2579 node = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "ports", 2580 CTLFLAG_RD, NULL, "CPSW Ports Statistics"); 2581 ports_parent = SYSCTL_CHILDREN(node); 2582 for (i = 0; i < CPSW_PORTS; i++) { 2583 if (!sc->dualemac && i != sc->active_slave) 2584 continue; 2585 port[0] = '0' + i; 2586 port[1] = '\0'; 2587 node = SYSCTL_ADD_NODE(ctx, ports_parent, OID_AUTO, 2588 port, CTLFLAG_RD, NULL, "CPSW Port Statistics"); 2589 port_parent = SYSCTL_CHILDREN(node); 2590 SYSCTL_ADD_PROC(ctx, port_parent, OID_AUTO, "uptime", 2591 CTLTYPE_UINT | CTLFLAG_RD, sc, i, 2592 cpsw_stat_uptime, "IU", "Seconds since driver init"); 2593 } 2594 2595 stats_node = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "stats", 2596 CTLFLAG_RD, NULL, "CPSW Statistics"); 2597 stats_parent = SYSCTL_CHILDREN(stats_node); 2598 for (i = 0; i < CPSW_SYSCTL_COUNT; ++i) { 2599 SYSCTL_ADD_PROC(ctx, stats_parent, i, 2600 cpsw_stat_sysctls[i].oid, 2601 CTLTYPE_U64 | CTLFLAG_RD, sc, 0, 2602 cpsw_stats_sysctl, "IU", 2603 cpsw_stat_sysctls[i].oid); 2604 } 2605 2606 queue_node = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "queue", 2607 CTLFLAG_RD, NULL, "CPSW Queue Statistics"); 2608 queue_parent = SYSCTL_CHILDREN(queue_node); 2609 2610 node = SYSCTL_ADD_NODE(ctx, queue_parent, OID_AUTO, "tx", 2611 CTLFLAG_RD, NULL, "TX Queue Statistics"); 2612 cpsw_add_queue_sysctls(ctx, node, &sc->tx); 2613 2614 node = SYSCTL_ADD_NODE(ctx, queue_parent, OID_AUTO, "rx", 2615 CTLFLAG_RD, NULL, "RX Queue Statistics"); 2616 cpsw_add_queue_sysctls(ctx, node, &sc->rx); 2617 2618 node = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "watchdog", 2619 CTLFLAG_RD, NULL, "Watchdog Statistics"); 2620 cpsw_add_watchdog_sysctls(ctx, node, sc); 2621} 2622