tegra_pcie.c revision 332010
1/*- 2 * Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD: stable/11/sys/arm/nvidia/tegra_pcie.c 332010 2018-04-04 11:30:20Z mmel $"); 29 30/* 31 * Nvidia Integrated PCI/PCI-Express controller driver. 32 */ 33 34#include <sys/param.h> 35#include <sys/systm.h> 36#include <sys/bus.h> 37#include <sys/devmap.h> 38#include <sys/proc.h> 39#include <sys/kernel.h> 40#include <sys/malloc.h> 41#include <sys/module.h> 42#include <sys/mutex.h> 43#include <sys/rman.h> 44 45#include <machine/intr.h> 46 47#include <vm/vm.h> 48#include <vm/vm_extern.h> 49#include <vm/vm_kern.h> 50#include <vm/pmap.h> 51 52#include <dev/extres/clk/clk.h> 53#include <dev/extres/hwreset/hwreset.h> 54#include <dev/extres/phy/phy.h> 55#include <dev/extres/regulator/regulator.h> 56#include <dev/fdt/fdt_common.h> 57#include <dev/ofw/ofw_bus.h> 58#include <dev/ofw/ofw_bus_subr.h> 59#include <dev/ofw/ofw_pci.h> 60#include <dev/ofw/ofwpci.h> 61#include <dev/pci/pcivar.h> 62#include <dev/pci/pcireg.h> 63#include <dev/pci/pcib_private.h> 64 65#include <machine/resource.h> 66#include <machine/bus.h> 67 68#include <arm/nvidia/tegra_pmc.h> 69 70#include "ofw_bus_if.h" 71#include "msi_if.h" 72#include "pcib_if.h" 73#include "pic_if.h" 74 75 76#define AFI_AXI_BAR0_SZ 0x000 77#define AFI_AXI_BAR1_SZ 0x004 78#define AFI_AXI_BAR2_SZ 0x008 79#define AFI_AXI_BAR3_SZ 0x00c 80#define AFI_AXI_BAR4_SZ 0x010 81#define AFI_AXI_BAR5_SZ 0x014 82#define AFI_AXI_BAR0_START 0x018 83#define AFI_AXI_BAR1_START 0x01c 84#define AFI_AXI_BAR2_START 0x020 85#define AFI_AXI_BAR3_START 0x024 86#define AFI_AXI_BAR4_START 0x028 87#define AFI_AXI_BAR5_START 0x02c 88#define AFI_FPCI_BAR0 0x030 89#define AFI_FPCI_BAR1 0x034 90#define AFI_FPCI_BAR2 0x038 91#define AFI_FPCI_BAR3 0x03c 92#define AFI_FPCI_BAR4 0x040 93#define AFI_FPCI_BAR5 0x044 94#define AFI_MSI_BAR_SZ 0x060 95#define AFI_MSI_FPCI_BAR_ST 0x064 96#define AFI_MSI_AXI_BAR_ST 0x068 97#define AFI_MSI_VEC(x) (0x06c + 4 * (x)) 98#define AFI_MSI_EN_VEC(x) (0x08c + 4 * (x)) 99#define AFI_MSI_INTR_IN_REG 32 100#define AFI_MSI_REGS 8 101 102#define AFI_CONFIGURATION 0x0ac 103#define AFI_CONFIGURATION_EN_FPCI (1 << 0) 104 105#define AFI_FPCI_ERROR_MASKS 0x0b0 106#define AFI_INTR_MASK 0x0b4 107#define AFI_INTR_MASK_MSI_MASK (1 << 8) 108#define AFI_INTR_MASK_INT_MASK (1 << 0) 109 110#define AFI_INTR_CODE 0x0b8 111#define AFI_INTR_CODE_MASK 0xf 112#define AFI_INTR_CODE_INT_CODE_INI_SLVERR 1 113#define AFI_INTR_CODE_INT_CODE_INI_DECERR 2 114#define AFI_INTR_CODE_INT_CODE_TGT_SLVERR 3 115#define AFI_INTR_CODE_INT_CODE_TGT_DECERR 4 116#define AFI_INTR_CODE_INT_CODE_TGT_WRERR 5 117#define AFI_INTR_CODE_INT_CODE_SM_MSG 6 118#define AFI_INTR_CODE_INT_CODE_DFPCI_DECERR 7 119#define AFI_INTR_CODE_INT_CODE_AXI_DECERR 8 120#define AFI_INTR_CODE_INT_CODE_FPCI_TIMEOUT 9 121#define AFI_INTR_CODE_INT_CODE_PE_PRSNT_SENSE 10 122#define AFI_INTR_CODE_INT_CODE_PE_CLKREQ_SENSE 11 123#define AFI_INTR_CODE_INT_CODE_CLKCLAMP_SENSE 12 124#define AFI_INTR_CODE_INT_CODE_RDY4PD_SENSE 13 125#define AFI_INTR_CODE_INT_CODE_P2P_ERROR 14 126 127 128#define AFI_INTR_SIGNATURE 0x0bc 129#define AFI_UPPER_FPCI_ADDRESS 0x0c0 130#define AFI_SM_INTR_ENABLE 0x0c4 131#define AFI_SM_INTR_RP_DEASSERT (1 << 14) 132#define AFI_SM_INTR_RP_ASSERT (1 << 13) 133#define AFI_SM_INTR_HOTPLUG (1 << 12) 134#define AFI_SM_INTR_PME (1 << 11) 135#define AFI_SM_INTR_FATAL_ERROR (1 << 10) 136#define AFI_SM_INTR_UNCORR_ERROR (1 << 9) 137#define AFI_SM_INTR_CORR_ERROR (1 << 8) 138#define AFI_SM_INTR_INTD_DEASSERT (1 << 7) 139#define AFI_SM_INTR_INTC_DEASSERT (1 << 6) 140#define AFI_SM_INTR_INTB_DEASSERT (1 << 5) 141#define AFI_SM_INTR_INTA_DEASSERT (1 << 4) 142#define AFI_SM_INTR_INTD_ASSERT (1 << 3) 143#define AFI_SM_INTR_INTC_ASSERT (1 << 2) 144#define AFI_SM_INTR_INTB_ASSERT (1 << 1) 145#define AFI_SM_INTR_INTA_ASSERT (1 << 0) 146 147#define AFI_AFI_INTR_ENABLE 0x0c8 148#define AFI_AFI_INTR_ENABLE_CODE(code) (1 << (code)) 149 150#define AFI_PCIE_CONFIG 0x0f8 151#define AFI_PCIE_CONFIG_PCIE_DISABLE(x) (1 << ((x) + 1)) 152#define AFI_PCIE_CONFIG_PCIE_DISABLE_ALL 0x6 153#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK (0xf << 20) 154#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_XBAR2_1 (0x0 << 20) 155#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_XBAR4_1 (0x1 << 20) 156 157#define AFI_FUSE 0x104 158#define AFI_FUSE_PCIE_T0_GEN2_DIS (1 << 2) 159 160#define AFI_PEX0_CTRL 0x110 161#define AFI_PEX1_CTRL 0x118 162#define AFI_PEX2_CTRL 0x128 163#define AFI_PEX_CTRL_OVERRIDE_EN (1 << 4) 164#define AFI_PEX_CTRL_REFCLK_EN (1 << 3) 165#define AFI_PEX_CTRL_CLKREQ_EN (1 << 1) 166#define AFI_PEX_CTRL_RST_L (1 << 0) 167 168#define AFI_AXI_BAR6_SZ 0x134 169#define AFI_AXI_BAR7_SZ 0x138 170#define AFI_AXI_BAR8_SZ 0x13c 171#define AFI_AXI_BAR6_START 0x140 172#define AFI_AXI_BAR7_START 0x144 173#define AFI_AXI_BAR8_START 0x148 174#define AFI_FPCI_BAR6 0x14c 175#define AFI_FPCI_BAR7 0x150 176#define AFI_FPCI_BAR8 0x154 177#define AFI_PLLE_CONTROL 0x160 178#define AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL (1 << 9) 179#define AFI_PLLE_CONTROL_BYPASS_PCIE2PLLE_CONTROL (1 << 8) 180#define AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN (1 << 1) 181#define AFI_PLLE_CONTROL_PCIE2PLLE_CONTROL_EN (1 << 0) 182 183#define AFI_PEXBIAS_CTRL 0x168 184 185/* FPCI Address space */ 186#define FPCI_MAP_IO 0xfdfc000000ULL 187#define FPCI_MAP_TYPE0_CONFIG 0xfdfc000000ULL 188#define FPCI_MAP_TYPE1_CONFIG 0xfdff000000ULL 189#define FPCI_MAP_EXT_TYPE0_CONFIG 0xfe00000000ULL 190#define FPCI_MAP_EXT_TYPE1_CONFIG 0xfe10000000ULL 191 192/* Configuration space */ 193#define RP_VEND_XP 0x00000F00 194#define RP_VEND_XP_DL_UP (1 << 30) 195 196#define RP_PRIV_MISC 0x00000FE0 197#define RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT (0xE << 0) 198#define RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT (0xF << 0) 199 200#define RP_LINK_CONTROL_STATUS 0x00000090 201#define RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE 0x20000000 202#define RP_LINK_CONTROL_STATUS_LINKSTAT_MASK 0x3fff0000 203 204/* Wait 50 ms (per port) for link. */ 205#define TEGRA_PCIE_LINKUP_TIMEOUT 50000 206 207#define TEGRA_PCIB_MSI_ENABLE 208 209#define DEBUG 210#ifdef DEBUG 211#define debugf(fmt, args...) do { printf(fmt,##args); } while (0) 212#else 213#define debugf(fmt, args...) 214#endif 215 216/* 217 * Configuration space format: 218 * [27:24] extended register 219 * [23:16] bus 220 * [15:11] slot (device) 221 * [10: 8] function 222 * [ 7: 0] register 223 */ 224#define PCI_CFG_EXT_REG(reg) ((((reg) >> 8) & 0x0f) << 24) 225#define PCI_CFG_BUS(bus) (((bus) & 0xff) << 16) 226#define PCI_CFG_DEV(dev) (((dev) & 0x1f) << 11) 227#define PCI_CFG_FUN(fun) (((fun) & 0x07) << 8) 228#define PCI_CFG_BASE_REG(reg) ((reg) & 0xff) 229 230#define PADS_WR4(_sc, _r, _v) bus_write_4((_sc)-pads_mem_res, (_r), (_v)) 231#define PADS_RD4(_sc, _r) bus_read_4((_sc)->pads_mem_res, (_r)) 232#define AFI_WR4(_sc, _r, _v) bus_write_4((_sc)->afi_mem_res, (_r), (_v)) 233#define AFI_RD4(_sc, _r) bus_read_4((_sc)->afi_mem_res, (_r)) 234 235static struct { 236 bus_size_t axi_start; 237 bus_size_t fpci_start; 238 bus_size_t size; 239} bars[] = { 240 {AFI_AXI_BAR0_START, AFI_FPCI_BAR0, AFI_AXI_BAR0_SZ}, /* BAR 0 */ 241 {AFI_AXI_BAR1_START, AFI_FPCI_BAR1, AFI_AXI_BAR1_SZ}, /* BAR 1 */ 242 {AFI_AXI_BAR2_START, AFI_FPCI_BAR2, AFI_AXI_BAR2_SZ}, /* BAR 2 */ 243 {AFI_AXI_BAR3_START, AFI_FPCI_BAR3, AFI_AXI_BAR3_SZ}, /* BAR 3 */ 244 {AFI_AXI_BAR4_START, AFI_FPCI_BAR4, AFI_AXI_BAR4_SZ}, /* BAR 4 */ 245 {AFI_AXI_BAR5_START, AFI_FPCI_BAR5, AFI_AXI_BAR5_SZ}, /* BAR 5 */ 246 {AFI_AXI_BAR6_START, AFI_FPCI_BAR6, AFI_AXI_BAR6_SZ}, /* BAR 6 */ 247 {AFI_AXI_BAR7_START, AFI_FPCI_BAR7, AFI_AXI_BAR7_SZ}, /* BAR 7 */ 248 {AFI_AXI_BAR8_START, AFI_FPCI_BAR8, AFI_AXI_BAR8_SZ}, /* BAR 8 */ 249 {AFI_MSI_AXI_BAR_ST, AFI_MSI_FPCI_BAR_ST, AFI_MSI_BAR_SZ}, /* MSI 9 */ 250}; 251 252/* Compatible devices. */ 253static struct ofw_compat_data compat_data[] = { 254 {"nvidia,tegra124-pcie", 1}, 255 {NULL, 0}, 256}; 257 258#define TEGRA_FLAG_MSI_USED 0x0001 259struct tegra_pcib_irqsrc { 260 struct intr_irqsrc isrc; 261 u_int irq; 262 u_int flags; 263}; 264 265struct tegra_pcib_port { 266 int enabled; 267 int port_idx; /* chip port index */ 268 int num_lanes; /* number of lanes */ 269 bus_size_t afi_pex_ctrl; /* offset of afi_pex_ctrl */ 270 phy_t phy; /* port phy */ 271 272 /* Config space properties. */ 273 bus_addr_t rp_base_addr; /* PA of config window */ 274 bus_size_t rp_size; /* size of config window */ 275 bus_space_handle_t cfg_handle; /* handle of config window */ 276}; 277 278#define TEGRA_PCIB_MAX_PORTS 3 279#define TEGRA_PCIB_MAX_MSI AFI_MSI_INTR_IN_REG * AFI_MSI_REGS 280struct tegra_pcib_softc { 281 struct ofw_pci_softc ofw_pci; 282 device_t dev; 283 struct mtx mtx; 284 struct resource *pads_mem_res; 285 struct resource *afi_mem_res; 286 struct resource *cfg_mem_res; 287 struct resource *irq_res; 288 struct resource *msi_irq_res; 289 void *intr_cookie; 290 void *msi_intr_cookie; 291 292 struct ofw_pci_range mem_range; 293 struct ofw_pci_range pref_mem_range; 294 struct ofw_pci_range io_range; 295 296 clk_t clk_pex; 297 clk_t clk_afi; 298 clk_t clk_pll_e; 299 clk_t clk_cml; 300 hwreset_t hwreset_pex; 301 hwreset_t hwreset_afi; 302 hwreset_t hwreset_pcie_x; 303 regulator_t supply_avddio_pex; 304 regulator_t supply_dvddio_pex; 305 regulator_t supply_avdd_pex_pll; 306 regulator_t supply_hvdd_pex; 307 regulator_t supply_hvdd_pex_pll_e; 308 regulator_t supply_vddio_pex_ctl; 309 regulator_t supply_avdd_pll_erefe; 310 311 vm_offset_t msi_page; /* VA of MSI page */ 312 bus_addr_t cfg_base_addr; /* base address of config */ 313 bus_size_t cfg_cur_offs; /* currently mapped window */ 314 bus_space_handle_t cfg_handle; /* handle of config window */ 315 bus_space_tag_t bus_tag; /* tag of config window */ 316 int lanes_cfg; 317 int num_ports; 318 struct tegra_pcib_port *ports[TEGRA_PCIB_MAX_PORTS]; 319 struct tegra_pcib_irqsrc *isrcs; 320}; 321 322static int 323tegra_pcib_maxslots(device_t dev) 324{ 325 return (16); 326} 327 328static int 329tegra_pcib_route_interrupt(device_t bus, device_t dev, int pin) 330{ 331 struct tegra_pcib_softc *sc; 332 u_int irq; 333 334 sc = device_get_softc(bus); 335 irq = intr_map_clone_irq(rman_get_start(sc->irq_res)); 336 device_printf(bus, "route pin %d for device %d.%d to %u\n", 337 pin, pci_get_slot(dev), pci_get_function(dev), 338 irq); 339 340 return (irq); 341} 342 343static int 344tegra_pcbib_map_cfg(struct tegra_pcib_softc *sc, u_int bus, u_int slot, 345 u_int func, u_int reg) 346{ 347 bus_size_t offs; 348 int rv; 349 350 offs = sc->cfg_base_addr; 351 offs |= PCI_CFG_BUS(bus) | PCI_CFG_DEV(slot) | PCI_CFG_FUN(func) | 352 PCI_CFG_EXT_REG(reg); 353 if ((sc->cfg_handle != 0) && (sc->cfg_cur_offs == offs)) 354 return (0); 355 if (sc->cfg_handle != 0) 356 bus_space_unmap(sc->bus_tag, sc->cfg_handle, 0x800); 357 358 rv = bus_space_map(sc->bus_tag, offs, 0x800, 0, &sc->cfg_handle); 359 if (rv != 0) 360 device_printf(sc->dev, "Cannot map config space\n"); 361 else 362 sc->cfg_cur_offs = offs; 363 return (rv); 364} 365 366static uint32_t 367tegra_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func, 368 u_int reg, int bytes) 369{ 370 struct tegra_pcib_softc *sc; 371 bus_space_handle_t hndl; 372 uint32_t off; 373 uint32_t val; 374 int rv, i; 375 376 sc = device_get_softc(dev); 377 if (bus == 0) { 378 if (func != 0) 379 return (0xFFFFFFFF); 380 for (i = 0; i < TEGRA_PCIB_MAX_PORTS; i++) { 381 if ((sc->ports[i] != NULL) && 382 (sc->ports[i]->port_idx == slot)) { 383 hndl = sc->ports[i]->cfg_handle; 384 off = reg & 0xFFF; 385 break; 386 } 387 } 388 if (i >= TEGRA_PCIB_MAX_PORTS) 389 return (0xFFFFFFFF); 390 } else { 391 rv = tegra_pcbib_map_cfg(sc, bus, slot, func, reg); 392 if (rv != 0) 393 return (0xFFFFFFFF); 394 hndl = sc->cfg_handle; 395 off = PCI_CFG_BASE_REG(reg); 396 } 397 398 val = bus_space_read_4(sc->bus_tag, hndl, off & ~3); 399 switch (bytes) { 400 case 4: 401 break; 402 case 2: 403 if (off & 3) 404 val >>= 16; 405 val &= 0xffff; 406 break; 407 case 1: 408 val >>= ((off & 3) << 3); 409 val &= 0xff; 410 break; 411 } 412 return val; 413} 414 415static void 416tegra_pcib_write_config(device_t dev, u_int bus, u_int slot, u_int func, 417 u_int reg, uint32_t val, int bytes) 418{ 419 struct tegra_pcib_softc *sc; 420 bus_space_handle_t hndl; 421 uint32_t off; 422 uint32_t val2; 423 int rv, i; 424 425 sc = device_get_softc(dev); 426 if (bus == 0) { 427 if (func != 0) 428 return; 429 for (i = 0; i < TEGRA_PCIB_MAX_PORTS; i++) { 430 if ((sc->ports[i] != NULL) && 431 (sc->ports[i]->port_idx == slot)) { 432 hndl = sc->ports[i]->cfg_handle; 433 off = reg & 0xFFF; 434 break; 435 } 436 } 437 if (i >= TEGRA_PCIB_MAX_PORTS) 438 return; 439 } else { 440 rv = tegra_pcbib_map_cfg(sc, bus, slot, func, reg); 441 if (rv != 0) 442 return; 443 hndl = sc->cfg_handle; 444 off = PCI_CFG_BASE_REG(reg); 445 } 446 447 switch (bytes) { 448 case 4: 449 bus_space_write_4(sc->bus_tag, hndl, off, val); 450 break; 451 case 2: 452 val2 = bus_space_read_4(sc->bus_tag, hndl, off & ~3); 453 val2 &= ~(0xffff << ((off & 3) << 3)); 454 val2 |= ((val & 0xffff) << ((off & 3) << 3)); 455 bus_space_write_4(sc->bus_tag, hndl, off & ~3, val2); 456 break; 457 case 1: 458 val2 = bus_space_read_4(sc->bus_tag, hndl, off & ~3); 459 val2 &= ~(0xff << ((off & 3) << 3)); 460 val2 |= ((val & 0xff) << ((off & 3) << 3)); 461 bus_space_write_4(sc->bus_tag, hndl, off & ~3, val2); 462 break; 463 } 464} 465 466static int tegra_pci_intr(void *arg) 467{ 468 struct tegra_pcib_softc *sc = arg; 469 uint32_t code, signature; 470 471 code = bus_read_4(sc->afi_mem_res, AFI_INTR_CODE) & AFI_INTR_CODE_MASK; 472 signature = bus_read_4(sc->afi_mem_res, AFI_INTR_SIGNATURE); 473 bus_write_4(sc->afi_mem_res, AFI_INTR_CODE, 0); 474 if (code == AFI_INTR_CODE_INT_CODE_SM_MSG) 475 return(FILTER_STRAY); 476 477 printf("tegra_pci_intr: code %x sig %x\n", code, signature); 478 return (FILTER_HANDLED); 479} 480 481/* ----------------------------------------------------------------------- 482 * 483 * PCI MSI interface 484 */ 485static int 486tegra_pcib_alloc_msi(device_t pci, device_t child, int count, int maxcount, 487 int *irqs) 488{ 489 phandle_t msi_parent; 490 491 /* XXXX ofw_bus_msimap() don't works for Tegra DT. 492 ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), &msi_parent, 493 NULL); 494 */ 495 msi_parent = OF_xref_from_node(ofw_bus_get_node(pci)); 496 return (intr_alloc_msi(pci, child, msi_parent, count, maxcount, 497 irqs)); 498} 499 500static int 501tegra_pcib_release_msi(device_t pci, device_t child, int count, int *irqs) 502{ 503 phandle_t msi_parent; 504 505 /* XXXX ofw_bus_msimap() don't works for Tegra DT. 506 ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), &msi_parent, 507 NULL); 508 */ 509 msi_parent = OF_xref_from_node(ofw_bus_get_node(pci)); 510 return (intr_release_msi(pci, child, msi_parent, count, irqs)); 511} 512 513static int 514tegra_pcib_map_msi(device_t pci, device_t child, int irq, uint64_t *addr, 515 uint32_t *data) 516{ 517 phandle_t msi_parent; 518 519 /* XXXX ofw_bus_msimap() don't works for Tegra DT. 520 ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), &msi_parent, 521 NULL); 522 */ 523 msi_parent = OF_xref_from_node(ofw_bus_get_node(pci)); 524 return (intr_map_msi(pci, child, msi_parent, irq, addr, data)); 525} 526 527#ifdef TEGRA_PCIB_MSI_ENABLE 528 529/* -------------------------------------------------------------------------- 530 * 531 * Interrupts 532 * 533 */ 534 535static inline void 536tegra_pcib_isrc_mask(struct tegra_pcib_softc *sc, 537 struct tegra_pcib_irqsrc *tgi, uint32_t val) 538{ 539 uint32_t reg; 540 int offs, bit; 541 542 offs = tgi->irq / AFI_MSI_INTR_IN_REG; 543 bit = 1 << (tgi->irq % AFI_MSI_INTR_IN_REG); 544 545 if (val != 0) 546 AFI_WR4(sc, AFI_MSI_VEC(offs), bit); 547 reg = AFI_RD4(sc, AFI_MSI_EN_VEC(offs)); 548 if (val != 0) 549 reg |= bit; 550 else 551 reg &= ~bit; 552 AFI_WR4(sc, AFI_MSI_EN_VEC(offs), reg); 553} 554 555static int 556tegra_pcib_msi_intr(void *arg) 557{ 558 u_int irq, i, bit, reg; 559 struct tegra_pcib_softc *sc; 560 struct trapframe *tf; 561 struct tegra_pcib_irqsrc *tgi; 562 563 sc = (struct tegra_pcib_softc *)arg; 564 tf = curthread->td_intr_frame; 565 566 for (i = 0; i < AFI_MSI_REGS; i++) { 567 reg = AFI_RD4(sc, AFI_MSI_VEC(i)); 568 /* Handle one vector. */ 569 while (reg != 0) { 570 bit = ffs(reg) - 1; 571 /* Send EOI */ 572 AFI_WR4(sc, AFI_MSI_VEC(i), 1 << bit); 573 irq = i * AFI_MSI_INTR_IN_REG + bit; 574 tgi = &sc->isrcs[irq]; 575 if (intr_isrc_dispatch(&tgi->isrc, tf) != 0) { 576 /* Disable stray. */ 577 tegra_pcib_isrc_mask(sc, tgi, 0); 578 device_printf(sc->dev, 579 "Stray irq %u disabled\n", irq); 580 } 581 reg = AFI_RD4(sc, AFI_MSI_VEC(i)); 582 } 583 } 584 return (FILTER_HANDLED); 585} 586 587static int 588tegra_pcib_msi_attach(struct tegra_pcib_softc *sc) 589{ 590 int error; 591 uint32_t irq; 592 const char *name; 593 594 sc->isrcs = malloc(sizeof(*sc->isrcs) * TEGRA_PCIB_MAX_MSI, M_DEVBUF, 595 M_WAITOK | M_ZERO); 596 597 name = device_get_nameunit(sc->dev); 598 for (irq = 0; irq < TEGRA_PCIB_MAX_MSI; irq++) { 599 sc->isrcs[irq].irq = irq; 600 error = intr_isrc_register(&sc->isrcs[irq].isrc, 601 sc->dev, 0, "%s,%u", name, irq); 602 if (error != 0) 603 return (error); /* XXX deregister ISRCs */ 604 } 605 if (intr_msi_register(sc->dev, 606 OF_xref_from_node(ofw_bus_get_node(sc->dev))) != 0) 607 return (ENXIO); 608 609 return (0); 610} 611 612static int 613tegra_pcib_msi_detach(struct tegra_pcib_softc *sc) 614{ 615 616 /* 617 * There has not been established any procedure yet 618 * how to detach PIC from living system correctly. 619 */ 620 device_printf(sc->dev, "%s: not implemented yet\n", __func__); 621 return (EBUSY); 622} 623 624 625static void 626tegra_pcib_msi_disable_intr(device_t dev, struct intr_irqsrc *isrc) 627{ 628 struct tegra_pcib_softc *sc; 629 struct tegra_pcib_irqsrc *tgi; 630 631 sc = device_get_softc(dev); 632 tgi = (struct tegra_pcib_irqsrc *)isrc; 633 tegra_pcib_isrc_mask(sc, tgi, 0); 634} 635 636static void 637tegra_pcib_msi_enable_intr(device_t dev, struct intr_irqsrc *isrc) 638{ 639 struct tegra_pcib_softc *sc; 640 struct tegra_pcib_irqsrc *tgi; 641 642 sc = device_get_softc(dev); 643 tgi = (struct tegra_pcib_irqsrc *)isrc; 644 tegra_pcib_isrc_mask(sc, tgi, 1); 645} 646 647/* MSI interrupts are edge trigered -> do nothing */ 648static void 649tegra_pcib_msi_post_filter(device_t dev, struct intr_irqsrc *isrc) 650{ 651} 652 653static void 654tegra_pcib_msi_post_ithread(device_t dev, struct intr_irqsrc *isrc) 655{ 656} 657 658static void 659tegra_pcib_msi_pre_ithread(device_t dev, struct intr_irqsrc *isrc) 660{ 661} 662 663static int 664tegra_pcib_msi_setup_intr(device_t dev, struct intr_irqsrc *isrc, 665 struct resource *res, struct intr_map_data *data) 666{ 667 struct tegra_pcib_softc *sc; 668 struct tegra_pcib_irqsrc *tgi; 669 670 sc = device_get_softc(dev); 671 tgi = (struct tegra_pcib_irqsrc *)isrc; 672 673 if (data == NULL || data->type != INTR_MAP_DATA_MSI) 674 return (ENOTSUP); 675 676 if (isrc->isrc_handlers == 0) 677 tegra_pcib_msi_enable_intr(dev, isrc); 678 679 return (0); 680} 681 682static int 683tegra_pcib_msi_teardown_intr(device_t dev, struct intr_irqsrc *isrc, 684 struct resource *res, struct intr_map_data *data) 685{ 686 struct tegra_pcib_softc *sc; 687 struct tegra_pcib_irqsrc *tgi; 688 689 sc = device_get_softc(dev); 690 tgi = (struct tegra_pcib_irqsrc *)isrc; 691 692 if (isrc->isrc_handlers == 0) 693 tegra_pcib_isrc_mask(sc, tgi, 0); 694 return (0); 695} 696 697 698static int 699tegra_pcib_msi_alloc_msi(device_t dev, device_t child, int count, int maxcount, 700 device_t *pic, struct intr_irqsrc **srcs) 701{ 702 struct tegra_pcib_softc *sc; 703 int i, irq, end_irq; 704 bool found; 705 706 KASSERT(powerof2(count), ("%s: bad count", __func__)); 707 KASSERT(powerof2(maxcount), ("%s: bad maxcount", __func__)); 708 709 sc = device_get_softc(dev); 710 mtx_lock(&sc->mtx); 711 712 found = false; 713 for (irq = 0; (irq + count - 1) < TEGRA_PCIB_MAX_MSI; irq++) { 714 /* Start on an aligned interrupt */ 715 if ((irq & (maxcount - 1)) != 0) 716 continue; 717 718 /* Assume we found a valid range until shown otherwise */ 719 found = true; 720 721 /* Check this range is valid */ 722 for (end_irq = irq; end_irq < irq + count; end_irq++) { 723 /* This is already used */ 724 if ((sc->isrcs[end_irq].flags & TEGRA_FLAG_MSI_USED) == 725 TEGRA_FLAG_MSI_USED) { 726 found = false; 727 break; 728 } 729 } 730 731 if (found) 732 break; 733 } 734 735 /* Not enough interrupts were found */ 736 if (!found || irq == (TEGRA_PCIB_MAX_MSI - 1)) { 737 mtx_unlock(&sc->mtx); 738 return (ENXIO); 739 } 740 741 for (i = 0; i < count; i++) { 742 /* Mark the interrupt as used */ 743 sc->isrcs[irq + i].flags |= TEGRA_FLAG_MSI_USED; 744 745 } 746 mtx_unlock(&sc->mtx); 747 748 for (i = 0; i < count; i++) 749 srcs[i] = (struct intr_irqsrc *)&sc->isrcs[irq + i]; 750 *pic = device_get_parent(dev); 751 return (0); 752} 753 754static int 755tegra_pcib_msi_release_msi(device_t dev, device_t child, int count, 756 struct intr_irqsrc **isrc) 757{ 758 struct tegra_pcib_softc *sc; 759 struct tegra_pcib_irqsrc *ti; 760 int i; 761 762 sc = device_get_softc(dev); 763 mtx_lock(&sc->mtx); 764 for (i = 0; i < count; i++) { 765 ti = (struct tegra_pcib_irqsrc *)isrc[i]; 766 767 KASSERT((ti->flags & TEGRA_FLAG_MSI_USED) == TEGRA_FLAG_MSI_USED, 768 ("%s: Trying to release an unused MSI-X interrupt", 769 __func__)); 770 771 ti->flags &= ~TEGRA_FLAG_MSI_USED; 772 } 773 mtx_unlock(&sc->mtx); 774 return (0); 775} 776 777static int 778tegra_pcib_msi_map_msi(device_t dev, device_t child, struct intr_irqsrc *isrc, 779 uint64_t *addr, uint32_t *data) 780{ 781 struct tegra_pcib_softc *sc = device_get_softc(dev); 782 struct tegra_pcib_irqsrc *ti = (struct tegra_pcib_irqsrc *)isrc; 783 784 *addr = vtophys(sc->msi_page); 785 *data = ti->irq; 786 return (0); 787} 788#endif 789 790/* ------------------------------------------------------------------- */ 791static bus_size_t 792tegra_pcib_pex_ctrl(struct tegra_pcib_softc *sc, int port) 793{ 794 if (port >= TEGRA_PCIB_MAX_PORTS) 795 panic("invalid port number: %d\n", port); 796 797 if (port == 0) 798 return (AFI_PEX0_CTRL); 799 else if (port == 1) 800 return (AFI_PEX1_CTRL); 801 else if (port == 2) 802 return (AFI_PEX2_CTRL); 803 else 804 panic("invalid port number: %d\n", port); 805} 806 807static int 808tegra_pcib_enable_fdt_resources(struct tegra_pcib_softc *sc) 809{ 810 int rv; 811 812 rv = hwreset_assert(sc->hwreset_pcie_x); 813 if (rv != 0) { 814 device_printf(sc->dev, "Cannot assert 'pcie_x' reset\n"); 815 return (rv); 816 } 817 rv = hwreset_assert(sc->hwreset_afi); 818 if (rv != 0) { 819 device_printf(sc->dev, "Cannot assert 'afi' reset\n"); 820 return (rv); 821 } 822 rv = hwreset_assert(sc->hwreset_pex); 823 if (rv != 0) { 824 device_printf(sc->dev, "Cannot assert 'pex' reset\n"); 825 return (rv); 826 } 827 828 tegra_powergate_power_off(TEGRA_POWERGATE_PCX); 829 830 /* Power supplies. */ 831 rv = regulator_enable(sc->supply_avddio_pex); 832 if (rv != 0) { 833 device_printf(sc->dev, 834 "Cannot enable 'avddio_pex' regulator\n"); 835 return (rv); 836 } 837 rv = regulator_enable(sc->supply_dvddio_pex); 838 if (rv != 0) { 839 device_printf(sc->dev, 840 "Cannot enable 'dvddio_pex' regulator\n"); 841 return (rv); 842 } 843 rv = regulator_enable(sc->supply_avdd_pex_pll); 844 if (rv != 0) { 845 device_printf(sc->dev, 846 "Cannot enable 'avdd-pex-pll' regulator\n"); 847 return (rv); 848 } 849 rv = regulator_enable(sc->supply_hvdd_pex); 850 if (rv != 0) { 851 device_printf(sc->dev, 852 "Cannot enable 'hvdd-pex-supply' regulator\n"); 853 return (rv); 854 } 855 rv = regulator_enable(sc->supply_hvdd_pex_pll_e); 856 if (rv != 0) { 857 device_printf(sc->dev, 858 "Cannot enable 'hvdd-pex-pll-e-supply' regulator\n"); 859 return (rv); 860 } 861 rv = regulator_enable(sc->supply_vddio_pex_ctl); 862 if (rv != 0) { 863 device_printf(sc->dev, 864 "Cannot enable 'vddio-pex-ctl' regulator\n"); 865 return (rv); 866 } 867 rv = regulator_enable(sc->supply_avdd_pll_erefe); 868 if (rv != 0) { 869 device_printf(sc->dev, 870 "Cannot enable 'avdd-pll-erefe-supply' regulator\n"); 871 return (rv); 872 } 873 874 rv = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_PCX, 875 sc->clk_pex, sc->hwreset_pex); 876 if (rv != 0) { 877 device_printf(sc->dev, "Cannot enable 'PCX' powergate\n"); 878 return (rv); 879 } 880 881 rv = hwreset_deassert(sc->hwreset_afi); 882 if (rv != 0) { 883 device_printf(sc->dev, "Cannot unreset 'afi' reset\n"); 884 return (rv); 885 } 886 887 rv = clk_enable(sc->clk_afi); 888 if (rv != 0) { 889 device_printf(sc->dev, "Cannot enable 'afi' clock\n"); 890 return (rv); 891 } 892 rv = clk_enable(sc->clk_cml); 893 if (rv != 0) { 894 device_printf(sc->dev, "Cannot enable 'cml' clock\n"); 895 return (rv); 896 } 897 rv = clk_enable(sc->clk_pll_e); 898 if (rv != 0) { 899 device_printf(sc->dev, "Cannot enable 'pll_e' clock\n"); 900 return (rv); 901 } 902 return (0); 903} 904 905static struct tegra_pcib_port * 906tegra_pcib_parse_port(struct tegra_pcib_softc *sc, phandle_t node) 907{ 908 struct tegra_pcib_port *port; 909 uint32_t tmp[5]; 910 char tmpstr[6]; 911 int rv; 912 913 port = malloc(sizeof(struct tegra_pcib_port), M_DEVBUF, M_WAITOK); 914 915 rv = OF_getprop(node, "status", tmpstr, sizeof(tmpstr)); 916 if (rv <= 0 || strcmp(tmpstr, "okay") == 0 || 917 strcmp(tmpstr, "ok") == 0) 918 port->enabled = 1; 919 else 920 port->enabled = 0; 921 922 rv = OF_getencprop(node, "assigned-addresses", tmp, sizeof(tmp)); 923 if (rv != sizeof(tmp)) { 924 device_printf(sc->dev, "Cannot parse assigned-address: %d\n", 925 rv); 926 goto fail; 927 } 928 port->rp_base_addr = tmp[2]; 929 port->rp_size = tmp[4]; 930 port->port_idx = OFW_PCI_PHYS_HI_DEVICE(tmp[0]) - 1; 931 if (port->port_idx >= TEGRA_PCIB_MAX_PORTS) { 932 device_printf(sc->dev, "Invalid port index: %d\n", 933 port->port_idx); 934 goto fail; 935 } 936 /* XXX - TODO: 937 * Implement proper function for parsing pci "reg" property: 938 * - it have PCI bus format 939 * - its relative to matching "assigned-addresses" 940 */ 941 rv = OF_getencprop(node, "reg", tmp, sizeof(tmp)); 942 if (rv != sizeof(tmp)) { 943 device_printf(sc->dev, "Cannot parse reg: %d\n", rv); 944 goto fail; 945 } 946 port->rp_base_addr += tmp[2]; 947 948 rv = OF_getencprop(node, "nvidia,num-lanes", &port->num_lanes, 949 sizeof(port->num_lanes)); 950 if (rv != sizeof(port->num_lanes)) { 951 device_printf(sc->dev, "Cannot parse nvidia,num-lanes: %d\n", 952 rv); 953 goto fail; 954 } 955 if (port->num_lanes > 4) { 956 device_printf(sc->dev, "Invalid nvidia,num-lanes: %d\n", 957 port->num_lanes); 958 goto fail; 959 } 960 961 port->afi_pex_ctrl = tegra_pcib_pex_ctrl(sc, port->port_idx); 962 sc->lanes_cfg |= port->num_lanes << (4 * port->port_idx); 963 964 /* Phy. */ 965 rv = phy_get_by_ofw_name(sc->dev, node, "pcie-0", &port->phy); 966 if (rv != 0) { 967 device_printf(sc->dev, 968 "Cannot get 'pcie-0' phy for port %d\n", 969 port->port_idx); 970 goto fail; 971 } 972 973 return (port); 974fail: 975 free(port, M_DEVBUF); 976 return (NULL); 977} 978 979 980static int 981tegra_pcib_parse_fdt_resources(struct tegra_pcib_softc *sc, phandle_t node) 982{ 983 phandle_t child; 984 struct tegra_pcib_port *port; 985 int rv; 986 987 /* Power supplies. */ 988 rv = regulator_get_by_ofw_property(sc->dev, 0, "avddio-pex-supply", 989 &sc->supply_avddio_pex); 990 if (rv != 0) { 991 device_printf(sc->dev, 992 "Cannot get 'avddio-pex' regulator\n"); 993 return (ENXIO); 994 } 995 rv = regulator_get_by_ofw_property(sc->dev, 0, "dvddio-pex-supply", 996 &sc->supply_dvddio_pex); 997 if (rv != 0) { 998 device_printf(sc->dev, 999 "Cannot get 'dvddio-pex' regulator\n"); 1000 return (ENXIO); 1001 } 1002 rv = regulator_get_by_ofw_property(sc->dev, 0, "avdd-pex-pll-supply", 1003 &sc->supply_avdd_pex_pll); 1004 if (rv != 0) { 1005 device_printf(sc->dev, 1006 "Cannot get 'avdd-pex-pll' regulator\n"); 1007 return (ENXIO); 1008 } 1009 rv = regulator_get_by_ofw_property(sc->dev, 0, "hvdd-pex-supply", 1010 &sc->supply_hvdd_pex); 1011 if (rv != 0) { 1012 device_printf(sc->dev, 1013 "Cannot get 'hvdd-pex' regulator\n"); 1014 return (ENXIO); 1015 } 1016 rv = regulator_get_by_ofw_property(sc->dev, 0, "hvdd-pex-pll-e-supply", 1017 &sc->supply_hvdd_pex_pll_e); 1018 if (rv != 0) { 1019 device_printf(sc->dev, 1020 "Cannot get 'hvdd-pex-pll-e' regulator\n"); 1021 return (ENXIO); 1022 } 1023 rv = regulator_get_by_ofw_property(sc->dev, 0, "vddio-pex-ctl-supply", 1024 &sc->supply_vddio_pex_ctl); 1025 if (rv != 0) { 1026 device_printf(sc->dev, 1027 "Cannot get 'vddio-pex-ctl' regulator\n"); 1028 return (ENXIO); 1029 } 1030 rv = regulator_get_by_ofw_property(sc->dev, 0, "avdd-pll-erefe-supply", 1031 &sc->supply_avdd_pll_erefe); 1032 if (rv != 0) { 1033 device_printf(sc->dev, 1034 "Cannot get 'avdd-pll-erefe' regulator\n"); 1035 return (ENXIO); 1036 } 1037 1038 /* Resets. */ 1039 rv = hwreset_get_by_ofw_name(sc->dev, 0, "pex", &sc->hwreset_pex); 1040 if (rv != 0) { 1041 device_printf(sc->dev, "Cannot get 'pex' reset\n"); 1042 return (ENXIO); 1043 } 1044 rv = hwreset_get_by_ofw_name(sc->dev, 0, "afi", &sc->hwreset_afi); 1045 if (rv != 0) { 1046 device_printf(sc->dev, "Cannot get 'afi' reset\n"); 1047 return (ENXIO); 1048 } 1049 rv = hwreset_get_by_ofw_name(sc->dev, 0, "pcie_x", &sc->hwreset_pcie_x); 1050 if (rv != 0) { 1051 device_printf(sc->dev, "Cannot get 'pcie_x' reset\n"); 1052 return (ENXIO); 1053 } 1054 1055 /* Clocks. */ 1056 rv = clk_get_by_ofw_name(sc->dev, 0, "pex", &sc->clk_pex); 1057 if (rv != 0) { 1058 device_printf(sc->dev, "Cannot get 'pex' clock\n"); 1059 return (ENXIO); 1060 } 1061 rv = clk_get_by_ofw_name(sc->dev, 0, "afi", &sc->clk_afi); 1062 if (rv != 0) { 1063 device_printf(sc->dev, "Cannot get 'afi' clock\n"); 1064 return (ENXIO); 1065 } 1066 rv = clk_get_by_ofw_name(sc->dev, 0, "pll_e", &sc->clk_pll_e); 1067 if (rv != 0) { 1068 device_printf(sc->dev, "Cannot get 'pll_e' clock\n"); 1069 return (ENXIO); 1070 } 1071 rv = clk_get_by_ofw_name(sc->dev, 0, "cml", &sc->clk_cml); 1072 if (rv != 0) { 1073 device_printf(sc->dev, "Cannot get 'cml' clock\n"); 1074 return (ENXIO); 1075 } 1076 1077 /* Ports */ 1078 sc->num_ports = 0; 1079 for (child = OF_child(node); child != 0; child = OF_peer(child)) { 1080 port = tegra_pcib_parse_port(sc, child); 1081 if (port == NULL) { 1082 device_printf(sc->dev, "Cannot parse PCIe port node\n"); 1083 return (ENXIO); 1084 } 1085 sc->ports[sc->num_ports++] = port; 1086 } 1087 1088 return (0); 1089} 1090 1091static int 1092tegra_pcib_decode_ranges(struct tegra_pcib_softc *sc, 1093 struct ofw_pci_range *ranges, int nranges) 1094{ 1095 int i; 1096 1097 for (i = 2; i < nranges; i++) { 1098 if ((ranges[i].pci_hi & OFW_PCI_PHYS_HI_SPACEMASK) == 1099 OFW_PCI_PHYS_HI_SPACE_IO) { 1100 if (sc->io_range.size != 0) { 1101 device_printf(sc->dev, 1102 "Duplicated IO range found in DT\n"); 1103 return (ENXIO); 1104 } 1105 sc->io_range = ranges[i]; 1106 } 1107 if (((ranges[i].pci_hi & OFW_PCI_PHYS_HI_SPACEMASK) == 1108 OFW_PCI_PHYS_HI_SPACE_MEM32)) { 1109 if (ranges[i].pci_hi & OFW_PCI_PHYS_HI_PREFETCHABLE) { 1110 if (sc->pref_mem_range.size != 0) { 1111 device_printf(sc->dev, 1112 "Duplicated memory range found " 1113 "in DT\n"); 1114 return (ENXIO); 1115 } 1116 sc->pref_mem_range = ranges[i]; 1117 } else { 1118 if (sc->mem_range.size != 0) { 1119 device_printf(sc->dev, 1120 "Duplicated memory range found " 1121 "in DT\n"); 1122 return (ENXIO); 1123 } 1124 sc->mem_range = ranges[i]; 1125 } 1126 } 1127 } 1128 if ((sc->io_range.size == 0) || (sc->mem_range.size == 0) 1129 || (sc->pref_mem_range.size == 0)) { 1130 device_printf(sc->dev, 1131 " Not all required ranges are found in DT\n"); 1132 return (ENXIO); 1133 } 1134 return (0); 1135} 1136 1137/* 1138 * Hardware config. 1139 */ 1140static int 1141tegra_pcib_wait_for_link(struct tegra_pcib_softc *sc, 1142 struct tegra_pcib_port *port) 1143{ 1144 uint32_t reg; 1145 int i; 1146 1147 1148 /* Setup link detection. */ 1149 reg = tegra_pcib_read_config(sc->dev, 0, port->port_idx, 0, 1150 RP_PRIV_MISC, 4); 1151 reg &= ~RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT; 1152 reg |= RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT; 1153 tegra_pcib_write_config(sc->dev, 0, port->port_idx, 0, 1154 RP_PRIV_MISC, reg, 4); 1155 1156 for (i = TEGRA_PCIE_LINKUP_TIMEOUT; i > 0; i--) { 1157 reg = tegra_pcib_read_config(sc->dev, 0, port->port_idx, 0, 1158 RP_VEND_XP, 4); 1159 if (reg & RP_VEND_XP_DL_UP) 1160 break; 1161 DELAY(1); 1162 1163 } 1164 if (i <= 0) 1165 return (ETIMEDOUT); 1166 1167 for (i = TEGRA_PCIE_LINKUP_TIMEOUT; i > 0; i--) { 1168 reg = tegra_pcib_read_config(sc->dev, 0, port->port_idx, 0, 1169 RP_LINK_CONTROL_STATUS, 4); 1170 if (reg & RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE) 1171 break; 1172 1173 DELAY(1); 1174 } 1175 if (i <= 0) 1176 return (ETIMEDOUT); 1177 return (0); 1178} 1179 1180static void 1181tegra_pcib_port_enable(struct tegra_pcib_softc *sc, int port_num) 1182{ 1183 struct tegra_pcib_port *port; 1184 uint32_t reg; 1185 int rv; 1186 1187 port = sc->ports[port_num]; 1188 1189 /* Put port to reset. */ 1190 reg = AFI_RD4(sc, port->afi_pex_ctrl); 1191 reg &= ~AFI_PEX_CTRL_RST_L; 1192 AFI_WR4(sc, port->afi_pex_ctrl, reg); 1193 AFI_RD4(sc, port->afi_pex_ctrl); 1194 DELAY(10); 1195 1196 /* Enable clocks. */ 1197 reg |= AFI_PEX_CTRL_REFCLK_EN; 1198 reg |= AFI_PEX_CTRL_CLKREQ_EN; 1199 reg |= AFI_PEX_CTRL_OVERRIDE_EN; 1200 AFI_WR4(sc, port->afi_pex_ctrl, reg); 1201 AFI_RD4(sc, port->afi_pex_ctrl); 1202 DELAY(100); 1203 1204 /* Release reset. */ 1205 reg |= AFI_PEX_CTRL_RST_L; 1206 AFI_WR4(sc, port->afi_pex_ctrl, reg); 1207 1208 rv = tegra_pcib_wait_for_link(sc, port); 1209 if (bootverbose) 1210 device_printf(sc->dev, " port %d (%d lane%s): Link is %s\n", 1211 port->port_idx, port->num_lanes, 1212 port->num_lanes > 1 ? "s": "", 1213 rv == 0 ? "up": "down"); 1214} 1215 1216 1217static void 1218tegra_pcib_port_disable(struct tegra_pcib_softc *sc, uint32_t port_num) 1219{ 1220 struct tegra_pcib_port *port; 1221 uint32_t reg; 1222 1223 port = sc->ports[port_num]; 1224 1225 /* Put port to reset. */ 1226 reg = AFI_RD4(sc, port->afi_pex_ctrl); 1227 reg &= ~AFI_PEX_CTRL_RST_L; 1228 AFI_WR4(sc, port->afi_pex_ctrl, reg); 1229 AFI_RD4(sc, port->afi_pex_ctrl); 1230 DELAY(10); 1231 1232 /* Disable clocks. */ 1233 reg &= ~AFI_PEX_CTRL_CLKREQ_EN; 1234 reg &= ~AFI_PEX_CTRL_REFCLK_EN; 1235 AFI_WR4(sc, port->afi_pex_ctrl, reg); 1236 1237 if (bootverbose) 1238 device_printf(sc->dev, " port %d (%d lane%s): Disabled\n", 1239 port->port_idx, port->num_lanes, 1240 port->num_lanes > 1 ? "s": ""); 1241} 1242 1243static void 1244tegra_pcib_set_bar(struct tegra_pcib_softc *sc, int bar, uint32_t axi, 1245 uint64_t fpci, uint32_t size, int is_memory) 1246{ 1247 uint32_t fpci_reg; 1248 uint32_t axi_reg; 1249 uint32_t size_reg; 1250 1251 axi_reg = axi & ~0xFFF; 1252 size_reg = size >> 12; 1253 fpci_reg = (uint32_t)(fpci >> 8) & ~0xF; 1254 fpci_reg |= is_memory ? 0x1 : 0x0; 1255 AFI_WR4(sc, bars[bar].axi_start, axi_reg); 1256 AFI_WR4(sc, bars[bar].size, size_reg); 1257 AFI_WR4(sc, bars[bar].fpci_start, fpci_reg); 1258} 1259 1260static int 1261tegra_pcib_enable(struct tegra_pcib_softc *sc) 1262{ 1263 int rv; 1264 int i; 1265 uint32_t reg; 1266 1267 rv = tegra_pcib_enable_fdt_resources(sc); 1268 if (rv != 0) { 1269 device_printf(sc->dev, "Cannot enable FDT resources\n"); 1270 return (rv); 1271 } 1272 /* Enable PLLE control. */ 1273 reg = AFI_RD4(sc, AFI_PLLE_CONTROL); 1274 reg &= ~AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL; 1275 reg |= AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN; 1276 AFI_WR4(sc, AFI_PLLE_CONTROL, reg); 1277 1278 /* Set bias pad. */ 1279 AFI_WR4(sc, AFI_PEXBIAS_CTRL, 0); 1280 1281 /* Configure mode and ports. */ 1282 reg = AFI_RD4(sc, AFI_PCIE_CONFIG); 1283 reg &= ~AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK; 1284 if (sc->lanes_cfg == 0x14) { 1285 if (bootverbose) 1286 device_printf(sc->dev, 1287 "Using x1,x4 configuration\n"); 1288 reg |= AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_XBAR4_1; 1289 } else if (sc->lanes_cfg == 0x12) { 1290 if (bootverbose) 1291 device_printf(sc->dev, 1292 "Using x1,x2 configuration\n"); 1293 reg |= AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_XBAR2_1; 1294 } else { 1295 device_printf(sc->dev, 1296 "Unsupported lanes configuration: 0x%X\n", sc->lanes_cfg); 1297 } 1298 reg |= AFI_PCIE_CONFIG_PCIE_DISABLE_ALL; 1299 for (i = 0; i < TEGRA_PCIB_MAX_PORTS; i++) { 1300 if ((sc->ports[i] != NULL)) 1301 reg &= 1302 ~AFI_PCIE_CONFIG_PCIE_DISABLE(sc->ports[i]->port_idx); 1303 } 1304 AFI_WR4(sc, AFI_PCIE_CONFIG, reg); 1305 1306 /* Enable Gen2 support. */ 1307 reg = AFI_RD4(sc, AFI_FUSE); 1308 reg &= ~AFI_FUSE_PCIE_T0_GEN2_DIS; 1309 AFI_WR4(sc, AFI_FUSE, reg); 1310 1311 for (i = 0; i < TEGRA_PCIB_MAX_PORTS; i++) { 1312 if (sc->ports[i] != NULL) { 1313 rv = phy_enable(sc->dev, sc->ports[i]->phy); 1314 if (rv != 0) { 1315 device_printf(sc->dev, 1316 "Cannot enable phy for port %d\n", 1317 sc->ports[i]->port_idx); 1318 return (rv); 1319 } 1320 } 1321 } 1322 1323 1324 rv = hwreset_deassert(sc->hwreset_pcie_x); 1325 if (rv != 0) { 1326 device_printf(sc->dev, "Cannot unreset 'pci_x' reset\n"); 1327 return (rv); 1328 } 1329 1330 /* Enable config space. */ 1331 reg = AFI_RD4(sc, AFI_CONFIGURATION); 1332 reg |= AFI_CONFIGURATION_EN_FPCI; 1333 AFI_WR4(sc, AFI_CONFIGURATION, reg); 1334 1335 /* Enable AFI errors. */ 1336 reg = 0; 1337 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_INI_SLVERR); 1338 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_INI_DECERR); 1339 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_TGT_SLVERR); 1340 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_TGT_DECERR); 1341 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_TGT_WRERR); 1342 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_SM_MSG); 1343 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_DFPCI_DECERR); 1344 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_AXI_DECERR); 1345 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_FPCI_TIMEOUT); 1346 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_PE_PRSNT_SENSE); 1347 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_PE_CLKREQ_SENSE); 1348 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_CLKCLAMP_SENSE); 1349 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_RDY4PD_SENSE); 1350 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_P2P_ERROR); 1351 AFI_WR4(sc, AFI_AFI_INTR_ENABLE, reg); 1352 AFI_WR4(sc, AFI_SM_INTR_ENABLE, 0xffffffff); 1353 1354 /* Enable INT, disable MSI. */ 1355 AFI_WR4(sc, AFI_INTR_MASK, AFI_INTR_MASK_INT_MASK); 1356 1357 /* Mask all FPCI errors. */ 1358 AFI_WR4(sc, AFI_FPCI_ERROR_MASKS, 0); 1359 1360 /* Setup AFI translation windows. */ 1361 /* BAR 0 - type 1 extended configuration. */ 1362 tegra_pcib_set_bar(sc, 0, rman_get_start(sc->cfg_mem_res), 1363 FPCI_MAP_EXT_TYPE1_CONFIG, rman_get_size(sc->cfg_mem_res), 0); 1364 1365 /* BAR 1 - downstream I/O. */ 1366 tegra_pcib_set_bar(sc, 1, sc->io_range.host, FPCI_MAP_IO, 1367 sc->io_range.size, 0); 1368 1369 /* BAR 2 - downstream prefetchable memory 1:1. */ 1370 tegra_pcib_set_bar(sc, 2, sc->pref_mem_range.host, 1371 sc->pref_mem_range.host, sc->pref_mem_range.size, 1); 1372 1373 /* BAR 3 - downstream not prefetchable memory 1:1 .*/ 1374 tegra_pcib_set_bar(sc, 3, sc->mem_range.host, 1375 sc->mem_range.host, sc->mem_range.size, 1); 1376 1377 /* BAR 3-8 clear. */ 1378 tegra_pcib_set_bar(sc, 4, 0, 0, 0, 0); 1379 tegra_pcib_set_bar(sc, 5, 0, 0, 0, 0); 1380 tegra_pcib_set_bar(sc, 6, 0, 0, 0, 0); 1381 tegra_pcib_set_bar(sc, 7, 0, 0, 0, 0); 1382 tegra_pcib_set_bar(sc, 8, 0, 0, 0, 0); 1383 1384 /* MSI BAR - clear. */ 1385 tegra_pcib_set_bar(sc, 9, 0, 0, 0, 0); 1386 return(0); 1387} 1388 1389#ifdef TEGRA_PCIB_MSI_ENABLE 1390static int 1391tegra_pcib_attach_msi(device_t dev) 1392{ 1393 struct tegra_pcib_softc *sc; 1394 uint32_t reg; 1395 int i, rv; 1396 1397 sc = device_get_softc(dev); 1398 1399 sc->msi_page = kmem_alloc_contig(kernel_arena, PAGE_SIZE, M_WAITOK, 1400 0, BUS_SPACE_MAXADDR, PAGE_SIZE, 0, VM_MEMATTR_DEFAULT); 1401 1402 /* MSI BAR */ 1403 tegra_pcib_set_bar(sc, 9, vtophys(sc->msi_page), vtophys(sc->msi_page), 1404 PAGE_SIZE, 0); 1405 1406 /* Disble and clear all interrupts. */ 1407 for (i = 0; i < AFI_MSI_REGS; i++) { 1408 AFI_WR4(sc, AFI_MSI_EN_VEC(i), 0); 1409 AFI_WR4(sc, AFI_MSI_VEC(i), 0xFFFFFFFF); 1410 } 1411 rv = bus_setup_intr(dev, sc->msi_irq_res, INTR_TYPE_BIO | INTR_MPSAFE, 1412 tegra_pcib_msi_intr, NULL, sc, &sc->msi_intr_cookie); 1413 if (rv != 0) { 1414 device_printf(dev, "cannot setup MSI interrupt handler\n"); 1415 rv = ENXIO; 1416 goto out; 1417 } 1418 1419 if (tegra_pcib_msi_attach(sc) != 0) { 1420 device_printf(dev, "WARNING: unable to attach PIC\n"); 1421 tegra_pcib_msi_detach(sc); 1422 goto out; 1423 } 1424 1425 /* Unmask MSI interrupt. */ 1426 reg = AFI_RD4(sc, AFI_INTR_MASK); 1427 reg |= AFI_INTR_MASK_MSI_MASK; 1428 AFI_WR4(sc, AFI_INTR_MASK, reg); 1429 1430out: 1431 return (rv); 1432} 1433#endif 1434 1435static int 1436tegra_pcib_probe(device_t dev) 1437{ 1438 if (!ofw_bus_status_okay(dev)) 1439 return (ENXIO); 1440 1441 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data != 0) { 1442 device_set_desc(dev, "Nvidia Integrated PCI/PCI-E Controller"); 1443 return (BUS_PROBE_DEFAULT); 1444 } 1445 return (ENXIO); 1446} 1447 1448static int 1449tegra_pcib_attach(device_t dev) 1450{ 1451 struct tegra_pcib_softc *sc; 1452 phandle_t node; 1453 int rv; 1454 int rid; 1455 struct tegra_pcib_port *port; 1456 int i; 1457 1458 sc = device_get_softc(dev); 1459 sc->dev = dev; 1460 mtx_init(&sc->mtx, "msi_mtx", NULL, MTX_DEF); 1461 1462 node = ofw_bus_get_node(dev); 1463 1464 rv = tegra_pcib_parse_fdt_resources(sc, node); 1465 if (rv != 0) { 1466 device_printf(dev, "Cannot get FDT resources\n"); 1467 return (rv); 1468 } 1469 1470 /* Allocate bus_space resources. */ 1471 rid = 0; 1472 sc->pads_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1473 RF_ACTIVE); 1474 if (sc->pads_mem_res == NULL) { 1475 device_printf(dev, "Cannot allocate PADS register\n"); 1476 rv = ENXIO; 1477 goto out; 1478 } 1479 /* 1480 * XXX - FIXME 1481 * tag for config space is not filled when RF_ALLOCATED flag is used. 1482 */ 1483 sc->bus_tag = rman_get_bustag(sc->pads_mem_res); 1484 1485 rid = 1; 1486 sc->afi_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1487 RF_ACTIVE); 1488 if (sc->afi_mem_res == NULL) { 1489 device_printf(dev, "Cannot allocate AFI register\n"); 1490 rv = ENXIO; 1491 goto out; 1492 } 1493 1494 rid = 2; 1495 sc->cfg_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1496 RF_ALLOCATED); 1497 if (sc->cfg_mem_res == NULL) { 1498 device_printf(dev, "Cannot allocate config space memory\n"); 1499 rv = ENXIO; 1500 goto out; 1501 } 1502 sc->cfg_base_addr = rman_get_start(sc->cfg_mem_res); 1503 1504 1505 /* Map RP slots */ 1506 for (i = 0; i < TEGRA_PCIB_MAX_PORTS; i++) { 1507 if (sc->ports[i] == NULL) 1508 continue; 1509 port = sc->ports[i]; 1510 rv = bus_space_map(sc->bus_tag, port->rp_base_addr, 1511 port->rp_size, 0, &port->cfg_handle); 1512 if (rv != 0) { 1513 device_printf(sc->dev, "Cannot allocate memory for " 1514 "port: %d\n", i); 1515 rv = ENXIO; 1516 goto out; 1517 } 1518 } 1519 1520 /* 1521 * Get PCI interrupt 1522 */ 1523 rid = 0; 1524 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1525 RF_ACTIVE | RF_SHAREABLE); 1526 if (sc->irq_res == NULL) { 1527 device_printf(dev, "Cannot allocate IRQ resources\n"); 1528 rv = ENXIO; 1529 goto out; 1530 } 1531 1532 rid = 1; 1533 sc->msi_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1534 RF_ACTIVE); 1535 if (sc->irq_res == NULL) { 1536 device_printf(dev, "Cannot allocate MSI IRQ resources\n"); 1537 rv = ENXIO; 1538 goto out; 1539 } 1540 1541 sc->ofw_pci.sc_range_mask = 0x3; 1542 rv = ofw_pci_init(dev); 1543 if (rv != 0) 1544 goto out; 1545 1546 rv = tegra_pcib_decode_ranges(sc, sc->ofw_pci.sc_range, 1547 sc->ofw_pci.sc_nrange); 1548 if (rv != 0) 1549 goto out; 1550 1551 if (bus_setup_intr(dev, sc->irq_res, INTR_TYPE_BIO | INTR_MPSAFE, 1552 tegra_pci_intr, NULL, sc, &sc->intr_cookie)) { 1553 device_printf(dev, "cannot setup interrupt handler\n"); 1554 rv = ENXIO; 1555 goto out; 1556 } 1557 1558 /* 1559 * Enable PCIE device. 1560 */ 1561 rv = tegra_pcib_enable(sc); 1562 if (rv != 0) 1563 goto out; 1564 for (i = 0; i < TEGRA_PCIB_MAX_PORTS; i++) { 1565 if (sc->ports[i] == NULL) 1566 continue; 1567 if (sc->ports[i]->enabled) 1568 tegra_pcib_port_enable(sc, i); 1569 else 1570 tegra_pcib_port_disable(sc, i); 1571 } 1572 1573#ifdef TEGRA_PCIB_MSI_ENABLE 1574 rv = tegra_pcib_attach_msi(dev); 1575 if (rv != 0) 1576 goto out; 1577#endif 1578 device_add_child(dev, "pci", -1); 1579 1580 return (bus_generic_attach(dev)); 1581 1582out: 1583 1584 return (rv); 1585} 1586 1587 1588static device_method_t tegra_pcib_methods[] = { 1589 /* Device interface */ 1590 DEVMETHOD(device_probe, tegra_pcib_probe), 1591 DEVMETHOD(device_attach, tegra_pcib_attach), 1592 1593 /* Bus interface */ 1594 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 1595 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 1596 1597 /* pcib interface */ 1598 DEVMETHOD(pcib_maxslots, tegra_pcib_maxslots), 1599 DEVMETHOD(pcib_read_config, tegra_pcib_read_config), 1600 DEVMETHOD(pcib_write_config, tegra_pcib_write_config), 1601 DEVMETHOD(pcib_route_interrupt, tegra_pcib_route_interrupt), 1602 DEVMETHOD(pcib_alloc_msi, tegra_pcib_alloc_msi), 1603 DEVMETHOD(pcib_release_msi, tegra_pcib_release_msi), 1604 DEVMETHOD(pcib_map_msi, tegra_pcib_map_msi), 1605 1606#ifdef TEGRA_PCIB_MSI_ENABLE 1607 /* MSI/MSI-X */ 1608 DEVMETHOD(msi_alloc_msi, tegra_pcib_msi_alloc_msi), 1609 DEVMETHOD(msi_release_msi, tegra_pcib_msi_release_msi), 1610 DEVMETHOD(msi_map_msi, tegra_pcib_msi_map_msi), 1611 1612 /* Interrupt controller interface */ 1613 DEVMETHOD(pic_disable_intr, tegra_pcib_msi_disable_intr), 1614 DEVMETHOD(pic_enable_intr, tegra_pcib_msi_enable_intr), 1615 DEVMETHOD(pic_setup_intr, tegra_pcib_msi_setup_intr), 1616 DEVMETHOD(pic_teardown_intr, tegra_pcib_msi_teardown_intr), 1617 DEVMETHOD(pic_post_filter, tegra_pcib_msi_post_filter), 1618 DEVMETHOD(pic_post_ithread, tegra_pcib_msi_post_ithread), 1619 DEVMETHOD(pic_pre_ithread, tegra_pcib_msi_pre_ithread), 1620#endif 1621 1622 /* OFW bus interface */ 1623 DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat), 1624 DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model), 1625 DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name), 1626 DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node), 1627 DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type), 1628 1629 DEVMETHOD_END 1630}; 1631 1632static devclass_t pcib_devclass; 1633DEFINE_CLASS_1(pcib, tegra_pcib_driver, tegra_pcib_methods, 1634 sizeof(struct tegra_pcib_softc), ofw_pci_driver); 1635DRIVER_MODULE(pcib, simplebus, tegra_pcib_driver, pcib_devclass, 1636 NULL, NULL); 1637