tegra_pcie.c revision 308335
1/*- 2 * Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD: stable/11/sys/arm/nvidia/tegra_pcie.c 308335 2016-11-05 10:56:32Z mmel $"); 29 30/* 31 * Nvidia Integrated PCI/PCI-Express controller driver. 32 */ 33 34#include <sys/param.h> 35#include <sys/systm.h> 36#include <sys/bus.h> 37#include <sys/devmap.h> 38#include <sys/proc.h> 39#include <sys/kernel.h> 40#include <sys/malloc.h> 41#include <sys/module.h> 42#include <sys/mutex.h> 43#include <sys/rman.h> 44 45#include <machine/intr.h> 46 47#include <vm/vm.h> 48#include <vm/vm_extern.h> 49#include <vm/vm_kern.h> 50#include <vm/pmap.h> 51 52#include <dev/extres/clk/clk.h> 53#include <dev/extres/hwreset/hwreset.h> 54#include <dev/extres/phy/phy.h> 55#include <dev/extres/regulator/regulator.h> 56#include <dev/fdt/fdt_common.h> 57#include <dev/ofw/ofw_bus.h> 58#include <dev/ofw/ofw_bus_subr.h> 59#include <dev/ofw/ofw_pci.h> 60#include <dev/ofw/ofwpci.h> 61#include <dev/pci/pcivar.h> 62#include <dev/pci/pcireg.h> 63#include <dev/pci/pcib_private.h> 64 65#include <machine/resource.h> 66#include <machine/bus.h> 67 68#include <arm/nvidia/tegra_pmc.h> 69 70#include "ofw_bus_if.h" 71#include "msi_if.h" 72#include "pcib_if.h" 73#include "pic_if.h" 74 75 76#define AFI_AXI_BAR0_SZ 0x000 77#define AFI_AXI_BAR1_SZ 0x004 78#define AFI_AXI_BAR2_SZ 0x008 79#define AFI_AXI_BAR3_SZ 0x00c 80#define AFI_AXI_BAR4_SZ 0x010 81#define AFI_AXI_BAR5_SZ 0x014 82#define AFI_AXI_BAR0_START 0x018 83#define AFI_AXI_BAR1_START 0x01c 84#define AFI_AXI_BAR2_START 0x020 85#define AFI_AXI_BAR3_START 0x024 86#define AFI_AXI_BAR4_START 0x028 87#define AFI_AXI_BAR5_START 0x02c 88#define AFI_FPCI_BAR0 0x030 89#define AFI_FPCI_BAR1 0x034 90#define AFI_FPCI_BAR2 0x038 91#define AFI_FPCI_BAR3 0x03c 92#define AFI_FPCI_BAR4 0x040 93#define AFI_FPCI_BAR5 0x044 94#define AFI_MSI_BAR_SZ 0x060 95#define AFI_MSI_FPCI_BAR_ST 0x064 96#define AFI_MSI_AXI_BAR_ST 0x068 97#define AFI_MSI_VEC(x) (0x06c + 4 * (x)) 98#define AFI_MSI_EN_VEC(x) (0x08c + 4 * (x)) 99#define AFI_MSI_INTR_IN_REG 32 100#define AFI_MSI_REGS 8 101 102#define AFI_CONFIGURATION 0x0ac 103#define AFI_CONFIGURATION_EN_FPCI (1 << 0) 104 105#define AFI_FPCI_ERROR_MASKS 0x0b0 106#define AFI_INTR_MASK 0x0b4 107#define AFI_INTR_MASK_MSI_MASK (1 << 8) 108#define AFI_INTR_MASK_INT_MASK (1 << 0) 109 110#define AFI_INTR_CODE 0x0b8 111#define AFI_INTR_CODE_MASK 0xf 112#define AFI_INTR_CODE_INT_CODE_INI_SLVERR 1 113#define AFI_INTR_CODE_INT_CODE_INI_DECERR 2 114#define AFI_INTR_CODE_INT_CODE_TGT_SLVERR 3 115#define AFI_INTR_CODE_INT_CODE_TGT_DECERR 4 116#define AFI_INTR_CODE_INT_CODE_TGT_WRERR 5 117#define AFI_INTR_CODE_INT_CODE_SM_MSG 6 118#define AFI_INTR_CODE_INT_CODE_DFPCI_DECERR 7 119#define AFI_INTR_CODE_INT_CODE_AXI_DECERR 8 120#define AFI_INTR_CODE_INT_CODE_FPCI_TIMEOUT 9 121#define AFI_INTR_CODE_INT_CODE_PE_PRSNT_SENSE 10 122#define AFI_INTR_CODE_INT_CODE_PE_CLKREQ_SENSE 11 123#define AFI_INTR_CODE_INT_CODE_CLKCLAMP_SENSE 12 124#define AFI_INTR_CODE_INT_CODE_RDY4PD_SENSE 13 125#define AFI_INTR_CODE_INT_CODE_P2P_ERROR 14 126 127 128#define AFI_INTR_SIGNATURE 0x0bc 129#define AFI_UPPER_FPCI_ADDRESS 0x0c0 130#define AFI_SM_INTR_ENABLE 0x0c4 131#define AFI_SM_INTR_RP_DEASSERT (1 << 14) 132#define AFI_SM_INTR_RP_ASSERT (1 << 13) 133#define AFI_SM_INTR_HOTPLUG (1 << 12) 134#define AFI_SM_INTR_PME (1 << 11) 135#define AFI_SM_INTR_FATAL_ERROR (1 << 10) 136#define AFI_SM_INTR_UNCORR_ERROR (1 << 9) 137#define AFI_SM_INTR_CORR_ERROR (1 << 8) 138#define AFI_SM_INTR_INTD_DEASSERT (1 << 7) 139#define AFI_SM_INTR_INTC_DEASSERT (1 << 6) 140#define AFI_SM_INTR_INTB_DEASSERT (1 << 5) 141#define AFI_SM_INTR_INTA_DEASSERT (1 << 4) 142#define AFI_SM_INTR_INTD_ASSERT (1 << 3) 143#define AFI_SM_INTR_INTC_ASSERT (1 << 2) 144#define AFI_SM_INTR_INTB_ASSERT (1 << 1) 145#define AFI_SM_INTR_INTA_ASSERT (1 << 0) 146 147#define AFI_AFI_INTR_ENABLE 0x0c8 148#define AFI_AFI_INTR_ENABLE_CODE(code) (1 << (code)) 149 150#define AFI_PCIE_CONFIG 0x0f8 151#define AFI_PCIE_CONFIG_PCIE_DISABLE(x) (1 << ((x) + 1)) 152#define AFI_PCIE_CONFIG_PCIE_DISABLE_ALL 0x6 153#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK (0xf << 20) 154#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_XBAR2_1 (0x0 << 20) 155#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_XBAR4_1 (0x1 << 20) 156 157#define AFI_FUSE 0x104 158#define AFI_FUSE_PCIE_T0_GEN2_DIS (1 << 2) 159 160#define AFI_PEX0_CTRL 0x110 161#define AFI_PEX1_CTRL 0x118 162#define AFI_PEX2_CTRL 0x128 163#define AFI_PEX_CTRL_OVERRIDE_EN (1 << 4) 164#define AFI_PEX_CTRL_REFCLK_EN (1 << 3) 165#define AFI_PEX_CTRL_CLKREQ_EN (1 << 1) 166#define AFI_PEX_CTRL_RST_L (1 << 0) 167 168#define AFI_AXI_BAR6_SZ 0x134 169#define AFI_AXI_BAR7_SZ 0x138 170#define AFI_AXI_BAR8_SZ 0x13c 171#define AFI_AXI_BAR6_START 0x140 172#define AFI_AXI_BAR7_START 0x144 173#define AFI_AXI_BAR8_START 0x148 174#define AFI_FPCI_BAR6 0x14c 175#define AFI_FPCI_BAR7 0x150 176#define AFI_FPCI_BAR8 0x154 177#define AFI_PLLE_CONTROL 0x160 178#define AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL (1 << 9) 179#define AFI_PLLE_CONTROL_BYPASS_PCIE2PLLE_CONTROL (1 << 8) 180#define AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN (1 << 1) 181#define AFI_PLLE_CONTROL_PCIE2PLLE_CONTROL_EN (1 << 0) 182 183#define AFI_PEXBIAS_CTRL 0x168 184 185/* FPCI Address space */ 186#define FPCI_MAP_IO 0xfdfc000000ULL 187#define FPCI_MAP_TYPE0_CONFIG 0xfdfc000000ULL 188#define FPCI_MAP_TYPE1_CONFIG 0xfdff000000ULL 189#define FPCI_MAP_EXT_TYPE0_CONFIG 0xfe00000000ULL 190#define FPCI_MAP_EXT_TYPE1_CONFIG 0xfe10000000ULL 191 192/* Configuration space */ 193#define RP_VEND_XP 0x00000F00 194#define RP_VEND_XP_DL_UP (1 << 30) 195 196#define RP_PRIV_MISC 0x00000FE0 197#define RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT (0xE << 0) 198#define RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT (0xF << 0) 199 200#define RP_LINK_CONTROL_STATUS 0x00000090 201#define RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE 0x20000000 202#define RP_LINK_CONTROL_STATUS_LINKSTAT_MASK 0x3fff0000 203 204/* Wait 50 ms (per port) for link. */ 205#define TEGRA_PCIE_LINKUP_TIMEOUT 50000 206 207#define TEGRA_PCIB_MSI_ENABLE 208 209#define DEBUG 210#ifdef DEBUG 211#define debugf(fmt, args...) do { printf(fmt,##args); } while (0) 212#else 213#define debugf(fmt, args...) 214#endif 215 216/* 217 * Configuration space format: 218 * [27:24] extended register 219 * [23:16] bus 220 * [15:11] slot (device) 221 * [10: 8] function 222 * [ 7: 0] register 223 */ 224#define PCI_CFG_EXT_REG(reg) ((((reg) >> 8) & 0x0f) << 24) 225#define PCI_CFG_BUS(bus) (((bus) & 0xff) << 16) 226#define PCI_CFG_DEV(dev) (((dev) & 0x1f) << 11) 227#define PCI_CFG_FUN(fun) (((fun) & 0x07) << 8) 228#define PCI_CFG_BASE_REG(reg) ((reg) & 0xff) 229 230#define PADS_WR4(_sc, _r, _v) bus_write_4((_sc)-pads_mem_res, (_r), (_v)) 231#define PADS_RD4(_sc, _r) bus_read_4((_sc)->pads_mem_res, (_r)) 232#define AFI_WR4(_sc, _r, _v) bus_write_4((_sc)->afi_mem_res, (_r), (_v)) 233#define AFI_RD4(_sc, _r) bus_read_4((_sc)->afi_mem_res, (_r)) 234 235static struct { 236 bus_size_t axi_start; 237 bus_size_t fpci_start; 238 bus_size_t size; 239} bars[] = { 240 {AFI_AXI_BAR0_START, AFI_FPCI_BAR0, AFI_AXI_BAR0_SZ}, /* BAR 0 */ 241 {AFI_AXI_BAR1_START, AFI_FPCI_BAR1, AFI_AXI_BAR1_SZ}, /* BAR 1 */ 242 {AFI_AXI_BAR2_START, AFI_FPCI_BAR2, AFI_AXI_BAR2_SZ}, /* BAR 2 */ 243 {AFI_AXI_BAR3_START, AFI_FPCI_BAR3, AFI_AXI_BAR3_SZ}, /* BAR 3 */ 244 {AFI_AXI_BAR4_START, AFI_FPCI_BAR4, AFI_AXI_BAR4_SZ}, /* BAR 4 */ 245 {AFI_AXI_BAR5_START, AFI_FPCI_BAR5, AFI_AXI_BAR5_SZ}, /* BAR 5 */ 246 {AFI_AXI_BAR6_START, AFI_FPCI_BAR6, AFI_AXI_BAR6_SZ}, /* BAR 6 */ 247 {AFI_AXI_BAR7_START, AFI_FPCI_BAR7, AFI_AXI_BAR7_SZ}, /* BAR 7 */ 248 {AFI_AXI_BAR8_START, AFI_FPCI_BAR8, AFI_AXI_BAR8_SZ}, /* BAR 8 */ 249 {AFI_MSI_AXI_BAR_ST, AFI_MSI_FPCI_BAR_ST, AFI_MSI_BAR_SZ}, /* MSI 9 */ 250}; 251 252/* Compatible devices. */ 253static struct ofw_compat_data compat_data[] = { 254 {"nvidia,tegra124-pcie", 1}, 255 {NULL, 0}, 256}; 257 258#define TEGRA_FLAG_MSI_USED 0x0001 259struct tegra_pcib_irqsrc { 260 struct intr_irqsrc isrc; 261 u_int irq; 262 u_int flags; 263}; 264 265struct tegra_pcib_port { 266 int enabled; 267 int port_idx; /* chip port index */ 268 int num_lanes; /* number of lanes */ 269 bus_size_t afi_pex_ctrl; /* offset of afi_pex_ctrl */ 270 271 /* Config space properties. */ 272 bus_addr_t rp_base_addr; /* PA of config window */ 273 bus_size_t rp_size; /* size of config window */ 274 bus_space_handle_t cfg_handle; /* handle of config window */ 275}; 276 277#define TEGRA_PCIB_MAX_PORTS 3 278#define TEGRA_PCIB_MAX_MSI AFI_MSI_INTR_IN_REG * AFI_MSI_REGS 279struct tegra_pcib_softc { 280 struct ofw_pci_softc ofw_pci; 281 device_t dev; 282 struct mtx mtx; 283 struct resource *pads_mem_res; 284 struct resource *afi_mem_res; 285 struct resource *cfg_mem_res; 286 struct resource *irq_res; 287 struct resource *msi_irq_res; 288 void *intr_cookie; 289 void *msi_intr_cookie; 290 291 struct ofw_pci_range mem_range; 292 struct ofw_pci_range pref_mem_range; 293 struct ofw_pci_range io_range; 294 295 phy_t phy; 296 clk_t clk_pex; 297 clk_t clk_afi; 298 clk_t clk_pll_e; 299 clk_t clk_cml; 300 hwreset_t hwreset_pex; 301 hwreset_t hwreset_afi; 302 hwreset_t hwreset_pcie_x; 303 regulator_t supply_avddio_pex; 304 regulator_t supply_dvddio_pex; 305 regulator_t supply_avdd_pex_pll; 306 regulator_t supply_hvdd_pex; 307 regulator_t supply_hvdd_pex_pll_e; 308 regulator_t supply_vddio_pex_ctl; 309 regulator_t supply_avdd_pll_erefe; 310 311 vm_offset_t msi_page; /* VA of MSI page */ 312 bus_addr_t cfg_base_addr; /* base address of config */ 313 bus_size_t cfg_cur_offs; /* currently mapped window */ 314 bus_space_handle_t cfg_handle; /* handle of config window */ 315 bus_space_tag_t bus_tag; /* tag of config window */ 316 int lanes_cfg; 317 int num_ports; 318 struct tegra_pcib_port *ports[TEGRA_PCIB_MAX_PORTS]; 319 struct tegra_pcib_irqsrc *isrcs; 320}; 321 322static int 323tegra_pcib_maxslots(device_t dev) 324{ 325 return (16); 326} 327 328static int 329tegra_pcib_route_interrupt(device_t bus, device_t dev, int pin) 330{ 331 struct tegra_pcib_softc *sc; 332 u_int irq; 333 334 sc = device_get_softc(bus); 335 irq = intr_map_clone_irq(rman_get_start(sc->irq_res)); 336 device_printf(bus, "route pin %d for device %d.%d to %u\n", 337 pin, pci_get_slot(dev), pci_get_function(dev), 338 irq); 339 340 return (irq); 341} 342 343static int 344tegra_pcbib_map_cfg(struct tegra_pcib_softc *sc, u_int bus, u_int slot, 345 u_int func, u_int reg) 346{ 347 bus_size_t offs; 348 int rv; 349 350 offs = sc->cfg_base_addr; 351 offs |= PCI_CFG_BUS(bus) | PCI_CFG_DEV(slot) | PCI_CFG_FUN(func) | 352 PCI_CFG_EXT_REG(reg); 353 if ((sc->cfg_handle != 0) && (sc->cfg_cur_offs == offs)) 354 return (0); 355 if (sc->cfg_handle != 0) 356 bus_space_unmap(sc->bus_tag, sc->cfg_handle, 0x800); 357 358 rv = bus_space_map(sc->bus_tag, offs, 0x800, 0, &sc->cfg_handle); 359 if (rv != 0) 360 device_printf(sc->dev, "Cannot map config space\n"); 361 else 362 sc->cfg_cur_offs = offs; 363 return (rv); 364} 365 366static uint32_t 367tegra_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func, 368 u_int reg, int bytes) 369{ 370 struct tegra_pcib_softc *sc; 371 bus_space_handle_t hndl; 372 uint32_t off; 373 uint32_t val; 374 int rv, i; 375 376 sc = device_get_softc(dev); 377 if (bus == 0) { 378 if (func != 0) 379 return (0xFFFFFFFF); 380 for (i = 0; i < TEGRA_PCIB_MAX_PORTS; i++) { 381 if ((sc->ports[i] != NULL) && 382 (sc->ports[i]->port_idx == slot)) { 383 hndl = sc->ports[i]->cfg_handle; 384 off = reg & 0xFFF; 385 break; 386 } 387 } 388 if (i >= TEGRA_PCIB_MAX_PORTS) 389 return (0xFFFFFFFF); 390 } else { 391 rv = tegra_pcbib_map_cfg(sc, bus, slot, func, reg); 392 if (rv != 0) 393 return (0xFFFFFFFF); 394 hndl = sc->cfg_handle; 395 off = PCI_CFG_BASE_REG(reg); 396 } 397 398 val = bus_space_read_4(sc->bus_tag, hndl, off & ~3); 399 switch (bytes) { 400 case 4: 401 break; 402 case 2: 403 if (off & 3) 404 val >>= 16; 405 val &= 0xffff; 406 break; 407 case 1: 408 val >>= ((off & 3) << 3); 409 val &= 0xff; 410 break; 411 } 412 return val; 413} 414 415static void 416tegra_pcib_write_config(device_t dev, u_int bus, u_int slot, u_int func, 417 u_int reg, uint32_t val, int bytes) 418{ 419 struct tegra_pcib_softc *sc; 420 bus_space_handle_t hndl; 421 uint32_t off; 422 uint32_t val2; 423 int rv, i; 424 425 sc = device_get_softc(dev); 426 if (bus == 0) { 427 if (func != 0) 428 return; 429 for (i = 0; i < TEGRA_PCIB_MAX_PORTS; i++) { 430 if ((sc->ports[i] != NULL) && 431 (sc->ports[i]->port_idx == slot)) { 432 hndl = sc->ports[i]->cfg_handle; 433 off = reg & 0xFFF; 434 break; 435 } 436 } 437 if (i >= TEGRA_PCIB_MAX_PORTS) 438 return; 439 } else { 440 rv = tegra_pcbib_map_cfg(sc, bus, slot, func, reg); 441 if (rv != 0) 442 return; 443 hndl = sc->cfg_handle; 444 off = PCI_CFG_BASE_REG(reg); 445 } 446 447 switch (bytes) { 448 case 4: 449 bus_space_write_4(sc->bus_tag, hndl, off, val); 450 break; 451 case 2: 452 val2 = bus_space_read_4(sc->bus_tag, hndl, off & ~3); 453 val2 &= ~(0xffff << ((off & 3) << 3)); 454 val2 |= ((val & 0xffff) << ((off & 3) << 3)); 455 bus_space_write_4(sc->bus_tag, hndl, off & ~3, val2); 456 break; 457 case 1: 458 val2 = bus_space_read_4(sc->bus_tag, hndl, off & ~3); 459 val2 &= ~(0xff << ((off & 3) << 3)); 460 val2 |= ((val & 0xff) << ((off & 3) << 3)); 461 bus_space_write_4(sc->bus_tag, hndl, off & ~3, val2); 462 break; 463 } 464} 465 466static int tegra_pci_intr(void *arg) 467{ 468 struct tegra_pcib_softc *sc = arg; 469 uint32_t code, signature; 470 471 code = bus_read_4(sc->afi_mem_res, AFI_INTR_CODE) & AFI_INTR_CODE_MASK; 472 signature = bus_read_4(sc->afi_mem_res, AFI_INTR_SIGNATURE); 473 bus_write_4(sc->afi_mem_res, AFI_INTR_CODE, 0); 474 if (code == AFI_INTR_CODE_INT_CODE_SM_MSG) 475 return(FILTER_STRAY); 476 477 printf("tegra_pci_intr: code %x sig %x\n", code, signature); 478 return (FILTER_HANDLED); 479} 480 481/* ----------------------------------------------------------------------- 482 * 483 * PCI MSI interface 484 */ 485static int 486tegra_pcib_alloc_msi(device_t pci, device_t child, int count, int maxcount, 487 int *irqs) 488{ 489 phandle_t msi_parent; 490 491 /* XXXX ofw_bus_msimap() don't works for Tegra DT. 492 ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), &msi_parent, 493 NULL); 494 */ 495 msi_parent = OF_xref_from_node(ofw_bus_get_node(pci)); 496 return (intr_alloc_msi(pci, child, msi_parent, count, maxcount, 497 irqs)); 498} 499 500static int 501tegra_pcib_release_msi(device_t pci, device_t child, int count, int *irqs) 502{ 503 phandle_t msi_parent; 504 505 /* XXXX ofw_bus_msimap() don't works for Tegra DT. 506 ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), &msi_parent, 507 NULL); 508 */ 509 msi_parent = OF_xref_from_node(ofw_bus_get_node(pci)); 510 return (intr_release_msi(pci, child, msi_parent, count, irqs)); 511} 512 513static int 514tegra_pcib_map_msi(device_t pci, device_t child, int irq, uint64_t *addr, 515 uint32_t *data) 516{ 517 phandle_t msi_parent; 518 519 /* XXXX ofw_bus_msimap() don't works for Tegra DT. 520 ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), &msi_parent, 521 NULL); 522 */ 523 msi_parent = OF_xref_from_node(ofw_bus_get_node(pci)); 524 return (intr_map_msi(pci, child, msi_parent, irq, addr, data)); 525} 526 527#ifdef TEGRA_PCIB_MSI_ENABLE 528 529/* -------------------------------------------------------------------------- 530 * 531 * Interrupts 532 * 533 */ 534 535static inline void 536tegra_pcib_isrc_mask(struct tegra_pcib_softc *sc, 537 struct tegra_pcib_irqsrc *tgi, uint32_t val) 538{ 539 uint32_t reg; 540 int offs, bit; 541 542 offs = tgi->irq / AFI_MSI_INTR_IN_REG; 543 bit = 1 << (tgi->irq % AFI_MSI_INTR_IN_REG); 544 545 if (val != 0) 546 AFI_WR4(sc, AFI_MSI_VEC(offs), bit); 547 reg = AFI_RD4(sc, AFI_MSI_EN_VEC(offs)); 548 if (val != 0) 549 reg |= bit; 550 else 551 reg &= ~bit; 552 AFI_WR4(sc, AFI_MSI_EN_VEC(offs), reg); 553} 554 555static int 556tegra_pcib_msi_intr(void *arg) 557{ 558 u_int irq, i, bit, reg; 559 struct tegra_pcib_softc *sc; 560 struct trapframe *tf; 561 struct tegra_pcib_irqsrc *tgi; 562 563 sc = (struct tegra_pcib_softc *)arg; 564 tf = curthread->td_intr_frame; 565 566 for (i = 0; i < AFI_MSI_REGS; i++) { 567 reg = AFI_RD4(sc, AFI_MSI_VEC(i)); 568 /* Handle one vector. */ 569 while (reg != 0) { 570 bit = ffs(reg) - 1; 571 /* Send EOI */ 572 AFI_WR4(sc, AFI_MSI_VEC(i), 1 << bit); 573 irq = i * AFI_MSI_INTR_IN_REG + bit; 574 tgi = &sc->isrcs[irq]; 575 if (intr_isrc_dispatch(&tgi->isrc, tf) != 0) { 576 /* Disable stray. */ 577 tegra_pcib_isrc_mask(sc, tgi, 0); 578 device_printf(sc->dev, 579 "Stray irq %u disabled\n", irq); 580 } 581 reg = AFI_RD4(sc, AFI_MSI_VEC(i)); 582 } 583 } 584 return (FILTER_HANDLED); 585} 586 587static int 588tegra_pcib_msi_attach(struct tegra_pcib_softc *sc) 589{ 590 int error; 591 uint32_t irq; 592 const char *name; 593 594 sc->isrcs = malloc(sizeof(*sc->isrcs) * TEGRA_PCIB_MAX_MSI, M_DEVBUF, 595 M_WAITOK | M_ZERO); 596 597 name = device_get_nameunit(sc->dev); 598 for (irq = 0; irq < TEGRA_PCIB_MAX_MSI; irq++) { 599 sc->isrcs[irq].irq = irq; 600 error = intr_isrc_register(&sc->isrcs[irq].isrc, 601 sc->dev, 0, "%s,%u", name, irq); 602 if (error != 0) 603 return (error); /* XXX deregister ISRCs */ 604 } 605 if (intr_msi_register(sc->dev, 606 OF_xref_from_node(ofw_bus_get_node(sc->dev))) != 0) 607 return (ENXIO); 608 609 return (0); 610} 611 612static int 613tegra_pcib_msi_detach(struct tegra_pcib_softc *sc) 614{ 615 616 /* 617 * There has not been established any procedure yet 618 * how to detach PIC from living system correctly. 619 */ 620 device_printf(sc->dev, "%s: not implemented yet\n", __func__); 621 return (EBUSY); 622} 623 624 625static void 626tegra_pcib_msi_disable_intr(device_t dev, struct intr_irqsrc *isrc) 627{ 628 struct tegra_pcib_softc *sc; 629 struct tegra_pcib_irqsrc *tgi; 630 631 sc = device_get_softc(dev); 632 tgi = (struct tegra_pcib_irqsrc *)isrc; 633 tegra_pcib_isrc_mask(sc, tgi, 0); 634} 635 636static void 637tegra_pcib_msi_enable_intr(device_t dev, struct intr_irqsrc *isrc) 638{ 639 struct tegra_pcib_softc *sc; 640 struct tegra_pcib_irqsrc *tgi; 641 642 sc = device_get_softc(dev); 643 tgi = (struct tegra_pcib_irqsrc *)isrc; 644 tegra_pcib_isrc_mask(sc, tgi, 1); 645} 646 647/* MSI interrupts are edge trigered -> do nothing */ 648static void 649tegra_pcib_msi_post_filter(device_t dev, struct intr_irqsrc *isrc) 650{ 651} 652 653static void 654tegra_pcib_msi_post_ithread(device_t dev, struct intr_irqsrc *isrc) 655{ 656} 657 658static void 659tegra_pcib_msi_pre_ithread(device_t dev, struct intr_irqsrc *isrc) 660{ 661} 662 663static int 664tegra_pcib_msi_setup_intr(device_t dev, struct intr_irqsrc *isrc, 665 struct resource *res, struct intr_map_data *data) 666{ 667 struct tegra_pcib_softc *sc; 668 struct tegra_pcib_irqsrc *tgi; 669 670 sc = device_get_softc(dev); 671 tgi = (struct tegra_pcib_irqsrc *)isrc; 672 673 if (data == NULL || data->type != INTR_MAP_DATA_MSI) 674 return (ENOTSUP); 675 676 if (isrc->isrc_handlers == 0) 677 tegra_pcib_msi_enable_intr(dev, isrc); 678 679 return (0); 680} 681 682static int 683tegra_pcib_msi_teardown_intr(device_t dev, struct intr_irqsrc *isrc, 684 struct resource *res, struct intr_map_data *data) 685{ 686 struct tegra_pcib_softc *sc; 687 struct tegra_pcib_irqsrc *tgi; 688 689 sc = device_get_softc(dev); 690 tgi = (struct tegra_pcib_irqsrc *)isrc; 691 692 if (isrc->isrc_handlers == 0) 693 tegra_pcib_isrc_mask(sc, tgi, 0); 694 return (0); 695} 696 697 698static int 699tegra_pcib_msi_alloc_msi(device_t dev, device_t child, int count, int maxcount, 700 device_t *pic, struct intr_irqsrc **srcs) 701{ 702 struct tegra_pcib_softc *sc; 703 int i, irq, end_irq; 704 bool found; 705 706 KASSERT(powerof2(count), ("%s: bad count", __func__)); 707 KASSERT(powerof2(maxcount), ("%s: bad maxcount", __func__)); 708 709 sc = device_get_softc(dev); 710 mtx_lock(&sc->mtx); 711 712 found = false; 713 for (irq = 0; irq < TEGRA_PCIB_MAX_MSI && !found; irq++) { 714 /* Start on an aligned interrupt */ 715 if ((irq & (maxcount - 1)) != 0) 716 continue; 717 718 /* Assume we found a valid range until shown otherwise */ 719 found = true; 720 721 /* Check this range is valid */ 722 for (end_irq = irq; end_irq != irq + count - 1; end_irq++) { 723 /* No free interrupts */ 724 if (end_irq == (TEGRA_PCIB_MAX_MSI - 1)) { 725 found = false; 726 break; 727 } 728 729 /* This is already used */ 730 if ((sc->isrcs[irq].flags & TEGRA_FLAG_MSI_USED) == 731 TEGRA_FLAG_MSI_USED) { 732 found = false; 733 break; 734 } 735 } 736 } 737 738 /* Not enough interrupts were found */ 739 if (!found || irq == (TEGRA_PCIB_MAX_MSI - 1)) { 740 mtx_unlock(&sc->mtx); 741 return (ENXIO); 742 } 743 744 for (i = 0; i < count; i++) { 745 /* Mark the interrupt as used */ 746 sc->isrcs[irq + i].flags |= TEGRA_FLAG_MSI_USED; 747 748 } 749 mtx_unlock(&sc->mtx); 750 751 for (i = 0; i < count; i++) 752 srcs[i] = (struct intr_irqsrc *)&sc->isrcs[irq + i]; 753 *pic = device_get_parent(dev); 754 return (0); 755} 756 757static int 758tegra_pcib_msi_release_msi(device_t dev, device_t child, int count, 759 struct intr_irqsrc **isrc) 760{ 761 struct tegra_pcib_softc *sc; 762 struct tegra_pcib_irqsrc *ti; 763 int i; 764 765 sc = device_get_softc(dev); 766 mtx_lock(&sc->mtx); 767 for (i = 0; i < count; i++) { 768 ti = (struct tegra_pcib_irqsrc *)isrc; 769 770 KASSERT((ti->flags & TEGRA_FLAG_MSI_USED) == TEGRA_FLAG_MSI_USED, 771 ("%s: Trying to release an unused MSI-X interrupt", 772 __func__)); 773 774 ti->flags &= ~TEGRA_FLAG_MSI_USED; 775 mtx_unlock(&sc->mtx); 776 } 777 return (0); 778} 779 780static int 781tegra_pcib_msi_map_msi(device_t dev, device_t child, struct intr_irqsrc *isrc, 782 uint64_t *addr, uint32_t *data) 783{ 784 struct tegra_pcib_softc *sc = device_get_softc(dev); 785 struct tegra_pcib_irqsrc *ti = (struct tegra_pcib_irqsrc *)isrc; 786 787 *addr = vtophys(sc->msi_page); 788 *data = ti->irq; 789 return (0); 790} 791#endif 792 793/* ------------------------------------------------------------------- */ 794static bus_size_t 795tegra_pcib_pex_ctrl(struct tegra_pcib_softc *sc, int port) 796{ 797 if (port >= TEGRA_PCIB_MAX_PORTS) 798 panic("invalid port number: %d\n", port); 799 800 if (port == 0) 801 return (AFI_PEX0_CTRL); 802 else if (port == 1) 803 return (AFI_PEX1_CTRL); 804 else if (port == 2) 805 return (AFI_PEX2_CTRL); 806 else 807 panic("invalid port number: %d\n", port); 808} 809 810static int 811tegra_pcib_enable_fdt_resources(struct tegra_pcib_softc *sc) 812{ 813 int rv; 814 815 rv = hwreset_assert(sc->hwreset_pcie_x); 816 if (rv != 0) { 817 device_printf(sc->dev, "Cannot assert 'pcie_x' reset\n"); 818 return (rv); 819 } 820 rv = hwreset_assert(sc->hwreset_afi); 821 if (rv != 0) { 822 device_printf(sc->dev, "Cannot assert 'afi' reset\n"); 823 return (rv); 824 } 825 rv = hwreset_assert(sc->hwreset_pex); 826 if (rv != 0) { 827 device_printf(sc->dev, "Cannot assert 'pex' reset\n"); 828 return (rv); 829 } 830 831 tegra_powergate_power_off(TEGRA_POWERGATE_PCX); 832 833 /* Power supplies. */ 834 rv = regulator_enable(sc->supply_avddio_pex); 835 if (rv != 0) { 836 device_printf(sc->dev, 837 "Cannot enable 'avddio_pex' regulator\n"); 838 return (rv); 839 } 840 rv = regulator_enable(sc->supply_dvddio_pex); 841 if (rv != 0) { 842 device_printf(sc->dev, 843 "Cannot enable 'dvddio_pex' regulator\n"); 844 return (rv); 845 } 846 rv = regulator_enable(sc->supply_avdd_pex_pll); 847 if (rv != 0) { 848 device_printf(sc->dev, 849 "Cannot enable 'avdd-pex-pll' regulator\n"); 850 return (rv); 851 } 852 rv = regulator_enable(sc->supply_hvdd_pex); 853 if (rv != 0) { 854 device_printf(sc->dev, 855 "Cannot enable 'hvdd-pex-supply' regulator\n"); 856 return (rv); 857 } 858 rv = regulator_enable(sc->supply_hvdd_pex_pll_e); 859 if (rv != 0) { 860 device_printf(sc->dev, 861 "Cannot enable 'hvdd-pex-pll-e-supply' regulator\n"); 862 return (rv); 863 } 864 rv = regulator_enable(sc->supply_vddio_pex_ctl); 865 if (rv != 0) { 866 device_printf(sc->dev, 867 "Cannot enable 'vddio-pex-ctl' regulator\n"); 868 return (rv); 869 } 870 rv = regulator_enable(sc->supply_avdd_pll_erefe); 871 if (rv != 0) { 872 device_printf(sc->dev, 873 "Cannot enable 'avdd-pll-erefe-supply' regulator\n"); 874 return (rv); 875 } 876 877 rv = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_PCX, 878 sc->clk_pex, sc->hwreset_pex); 879 if (rv != 0) { 880 device_printf(sc->dev, "Cannot enable 'PCX' powergate\n"); 881 return (rv); 882 } 883 884 rv = hwreset_deassert(sc->hwreset_afi); 885 if (rv != 0) { 886 device_printf(sc->dev, "Cannot unreset 'afi' reset\n"); 887 return (rv); 888 } 889 890 rv = clk_enable(sc->clk_afi); 891 if (rv != 0) { 892 device_printf(sc->dev, "Cannot enable 'afi' clock\n"); 893 return (rv); 894 } 895 rv = clk_enable(sc->clk_cml); 896 if (rv != 0) { 897 device_printf(sc->dev, "Cannot enable 'cml' clock\n"); 898 return (rv); 899 } 900 rv = clk_enable(sc->clk_pll_e); 901 if (rv != 0) { 902 device_printf(sc->dev, "Cannot enable 'pll_e' clock\n"); 903 return (rv); 904 } 905 return (0); 906} 907 908static struct tegra_pcib_port * 909tegra_pcib_parse_port(struct tegra_pcib_softc *sc, phandle_t node) 910{ 911 struct tegra_pcib_port *port; 912 uint32_t tmp[5]; 913 char tmpstr[6]; 914 int rv; 915 916 port = malloc(sizeof(struct tegra_pcib_port), M_DEVBUF, M_WAITOK); 917 918 rv = OF_getprop(node, "status", tmpstr, sizeof(tmpstr)); 919 if (rv <= 0 || strcmp(tmpstr, "okay") == 0 || 920 strcmp(tmpstr, "ok") == 0) 921 port->enabled = 1; 922 else 923 port->enabled = 0; 924 925 rv = OF_getencprop(node, "assigned-addresses", tmp, sizeof(tmp)); 926 if (rv != sizeof(tmp)) { 927 device_printf(sc->dev, "Cannot parse assigned-address: %d\n", 928 rv); 929 goto fail; 930 } 931 port->rp_base_addr = tmp[2]; 932 port->rp_size = tmp[4]; 933 port->port_idx = OFW_PCI_PHYS_HI_DEVICE(tmp[0]) - 1; 934 if (port->port_idx >= TEGRA_PCIB_MAX_PORTS) { 935 device_printf(sc->dev, "Invalid port index: %d\n", 936 port->port_idx); 937 goto fail; 938 } 939 /* XXX - TODO: 940 * Implement proper function for parsing pci "reg" property: 941 * - it have PCI bus format 942 * - its relative to matching "assigned-addresses" 943 */ 944 rv = OF_getencprop(node, "reg", tmp, sizeof(tmp)); 945 if (rv != sizeof(tmp)) { 946 device_printf(sc->dev, "Cannot parse reg: %d\n", rv); 947 goto fail; 948 } 949 port->rp_base_addr += tmp[2]; 950 951 rv = OF_getencprop(node, "nvidia,num-lanes", &port->num_lanes, 952 sizeof(port->num_lanes)); 953 if (rv != sizeof(port->num_lanes)) { 954 device_printf(sc->dev, "Cannot parse nvidia,num-lanes: %d\n", 955 rv); 956 goto fail; 957 } 958 if (port->num_lanes > 4) { 959 device_printf(sc->dev, "Invalid nvidia,num-lanes: %d\n", 960 port->num_lanes); 961 goto fail; 962 } 963 964 port->afi_pex_ctrl = tegra_pcib_pex_ctrl(sc, port->port_idx); 965 sc->lanes_cfg |= port->num_lanes << (4 * port->port_idx); 966 967 return (port); 968fail: 969 free(port, M_DEVBUF); 970 return (NULL); 971} 972 973 974static int 975tegra_pcib_parse_fdt_resources(struct tegra_pcib_softc *sc, phandle_t node) 976{ 977 phandle_t child; 978 struct tegra_pcib_port *port; 979 int rv; 980 981 /* Power supplies. */ 982 rv = regulator_get_by_ofw_property(sc->dev, 0, "avddio-pex-supply", 983 &sc->supply_avddio_pex); 984 if (rv != 0) { 985 device_printf(sc->dev, 986 "Cannot get 'avddio-pex' regulator\n"); 987 return (ENXIO); 988 } 989 rv = regulator_get_by_ofw_property(sc->dev, 0, "dvddio-pex-supply", 990 &sc->supply_dvddio_pex); 991 if (rv != 0) { 992 device_printf(sc->dev, 993 "Cannot get 'dvddio-pex' regulator\n"); 994 return (ENXIO); 995 } 996 rv = regulator_get_by_ofw_property(sc->dev, 0, "avdd-pex-pll-supply", 997 &sc->supply_avdd_pex_pll); 998 if (rv != 0) { 999 device_printf(sc->dev, 1000 "Cannot get 'avdd-pex-pll' regulator\n"); 1001 return (ENXIO); 1002 } 1003 rv = regulator_get_by_ofw_property(sc->dev, 0, "hvdd-pex-supply", 1004 &sc->supply_hvdd_pex); 1005 if (rv != 0) { 1006 device_printf(sc->dev, 1007 "Cannot get 'hvdd-pex' regulator\n"); 1008 return (ENXIO); 1009 } 1010 rv = regulator_get_by_ofw_property(sc->dev, 0, "hvdd-pex-pll-e-supply", 1011 &sc->supply_hvdd_pex_pll_e); 1012 if (rv != 0) { 1013 device_printf(sc->dev, 1014 "Cannot get 'hvdd-pex-pll-e' regulator\n"); 1015 return (ENXIO); 1016 } 1017 rv = regulator_get_by_ofw_property(sc->dev, 0, "vddio-pex-ctl-supply", 1018 &sc->supply_vddio_pex_ctl); 1019 if (rv != 0) { 1020 device_printf(sc->dev, 1021 "Cannot get 'vddio-pex-ctl' regulator\n"); 1022 return (ENXIO); 1023 } 1024 rv = regulator_get_by_ofw_property(sc->dev, 0, "avdd-pll-erefe-supply", 1025 &sc->supply_avdd_pll_erefe); 1026 if (rv != 0) { 1027 device_printf(sc->dev, 1028 "Cannot get 'avdd-pll-erefe' regulator\n"); 1029 return (ENXIO); 1030 } 1031 1032 /* Resets. */ 1033 rv = hwreset_get_by_ofw_name(sc->dev, 0, "pex", &sc->hwreset_pex); 1034 if (rv != 0) { 1035 device_printf(sc->dev, "Cannot get 'pex' reset\n"); 1036 return (ENXIO); 1037 } 1038 rv = hwreset_get_by_ofw_name(sc->dev, 0, "afi", &sc->hwreset_afi); 1039 if (rv != 0) { 1040 device_printf(sc->dev, "Cannot get 'afi' reset\n"); 1041 return (ENXIO); 1042 } 1043 rv = hwreset_get_by_ofw_name(sc->dev, 0, "pcie_x", &sc->hwreset_pcie_x); 1044 if (rv != 0) { 1045 device_printf(sc->dev, "Cannot get 'pcie_x' reset\n"); 1046 return (ENXIO); 1047 } 1048 1049 /* Clocks. */ 1050 rv = clk_get_by_ofw_name(sc->dev, 0, "pex", &sc->clk_pex); 1051 if (rv != 0) { 1052 device_printf(sc->dev, "Cannot get 'pex' clock\n"); 1053 return (ENXIO); 1054 } 1055 rv = clk_get_by_ofw_name(sc->dev, 0, "afi", &sc->clk_afi); 1056 if (rv != 0) { 1057 device_printf(sc->dev, "Cannot get 'afi' clock\n"); 1058 return (ENXIO); 1059 } 1060 rv = clk_get_by_ofw_name(sc->dev, 0, "pll_e", &sc->clk_pll_e); 1061 if (rv != 0) { 1062 device_printf(sc->dev, "Cannot get 'pll_e' clock\n"); 1063 return (ENXIO); 1064 } 1065 rv = clk_get_by_ofw_name(sc->dev, 0, "cml", &sc->clk_cml); 1066 if (rv != 0) { 1067 device_printf(sc->dev, "Cannot get 'cml' clock\n"); 1068 return (ENXIO); 1069 } 1070 1071 /* Phy. */ 1072 rv = phy_get_by_ofw_name(sc->dev, 0, "pcie", &sc->phy); 1073 if (rv != 0) { 1074 device_printf(sc->dev, "Cannot get 'pcie' phy\n"); 1075 return (ENXIO); 1076 } 1077 1078 /* Ports */ 1079 sc->num_ports = 0; 1080 for (child = OF_child(node); child != 0; child = OF_peer(child)) { 1081 port = tegra_pcib_parse_port(sc, child); 1082 if (port == NULL) { 1083 device_printf(sc->dev, "Cannot parse PCIe port node\n"); 1084 return (ENXIO); 1085 } 1086 sc->ports[sc->num_ports++] = port; 1087 } 1088 1089 return (0); 1090} 1091 1092static int 1093tegra_pcib_decode_ranges(struct tegra_pcib_softc *sc, 1094 struct ofw_pci_range *ranges, int nranges) 1095{ 1096 int i; 1097 1098 for (i = 2; i < nranges; i++) { 1099 if ((ranges[i].pci_hi & OFW_PCI_PHYS_HI_SPACEMASK) == 1100 OFW_PCI_PHYS_HI_SPACE_IO) { 1101 if (sc->io_range.size != 0) { 1102 device_printf(sc->dev, 1103 "Duplicated IO range found in DT\n"); 1104 return (ENXIO); 1105 } 1106 sc->io_range = ranges[i]; 1107 } 1108 if (((ranges[i].pci_hi & OFW_PCI_PHYS_HI_SPACEMASK) == 1109 OFW_PCI_PHYS_HI_SPACE_MEM32)) { 1110 if (ranges[i].pci_hi & OFW_PCI_PHYS_HI_PREFETCHABLE) { 1111 if (sc->pref_mem_range.size != 0) { 1112 device_printf(sc->dev, 1113 "Duplicated memory range found " 1114 "in DT\n"); 1115 return (ENXIO); 1116 } 1117 sc->pref_mem_range = ranges[i]; 1118 } else { 1119 if (sc->mem_range.size != 0) { 1120 device_printf(sc->dev, 1121 "Duplicated memory range found " 1122 "in DT\n"); 1123 return (ENXIO); 1124 } 1125 sc->mem_range = ranges[i]; 1126 } 1127 } 1128 } 1129 if ((sc->io_range.size == 0) || (sc->mem_range.size == 0) 1130 || (sc->pref_mem_range.size == 0)) { 1131 device_printf(sc->dev, 1132 " Not all required ranges are found in DT\n"); 1133 return (ENXIO); 1134 } 1135 return (0); 1136} 1137 1138/* 1139 * Hardware config. 1140 */ 1141static int 1142tegra_pcib_wait_for_link(struct tegra_pcib_softc *sc, 1143 struct tegra_pcib_port *port) 1144{ 1145 uint32_t reg; 1146 int i; 1147 1148 1149 /* Setup link detection. */ 1150 reg = tegra_pcib_read_config(sc->dev, 0, port->port_idx, 0, 1151 RP_PRIV_MISC, 4); 1152 reg &= ~RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT; 1153 reg |= RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT; 1154 tegra_pcib_write_config(sc->dev, 0, port->port_idx, 0, 1155 RP_PRIV_MISC, reg, 4); 1156 1157 for (i = TEGRA_PCIE_LINKUP_TIMEOUT; i > 0; i--) { 1158 reg = tegra_pcib_read_config(sc->dev, 0, port->port_idx, 0, 1159 RP_VEND_XP, 4); 1160 if (reg & RP_VEND_XP_DL_UP) 1161 break; 1162 DELAY(1); 1163 1164 } 1165 if (i <= 0) 1166 return (ETIMEDOUT); 1167 1168 for (i = TEGRA_PCIE_LINKUP_TIMEOUT; i > 0; i--) { 1169 reg = tegra_pcib_read_config(sc->dev, 0, port->port_idx, 0, 1170 RP_LINK_CONTROL_STATUS, 4); 1171 if (reg & RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE) 1172 break; 1173 1174 DELAY(1); 1175 } 1176 if (i <= 0) 1177 return (ETIMEDOUT); 1178 return (0); 1179} 1180 1181static void 1182tegra_pcib_port_enable(struct tegra_pcib_softc *sc, int port_num) 1183{ 1184 struct tegra_pcib_port *port; 1185 uint32_t reg; 1186 int rv; 1187 1188 port = sc->ports[port_num]; 1189 1190 /* Put port to reset. */ 1191 reg = AFI_RD4(sc, port->afi_pex_ctrl); 1192 reg &= ~AFI_PEX_CTRL_RST_L; 1193 AFI_WR4(sc, port->afi_pex_ctrl, reg); 1194 AFI_RD4(sc, port->afi_pex_ctrl); 1195 DELAY(10); 1196 1197 /* Enable clocks. */ 1198 reg |= AFI_PEX_CTRL_REFCLK_EN; 1199 reg |= AFI_PEX_CTRL_CLKREQ_EN; 1200 reg |= AFI_PEX_CTRL_OVERRIDE_EN; 1201 AFI_WR4(sc, port->afi_pex_ctrl, reg); 1202 AFI_RD4(sc, port->afi_pex_ctrl); 1203 DELAY(100); 1204 1205 /* Release reset. */ 1206 reg |= AFI_PEX_CTRL_RST_L; 1207 AFI_WR4(sc, port->afi_pex_ctrl, reg); 1208 1209 rv = tegra_pcib_wait_for_link(sc, port); 1210 if (bootverbose) 1211 device_printf(sc->dev, " port %d (%d lane%s): Link is %s\n", 1212 port->port_idx, port->num_lanes, 1213 port->num_lanes > 1 ? "s": "", 1214 rv == 0 ? "up": "down"); 1215} 1216 1217 1218static void 1219tegra_pcib_port_disable(struct tegra_pcib_softc *sc, uint32_t port_num) 1220{ 1221 struct tegra_pcib_port *port; 1222 uint32_t reg; 1223 1224 port = sc->ports[port_num]; 1225 1226 /* Put port to reset. */ 1227 reg = AFI_RD4(sc, port->afi_pex_ctrl); 1228 reg &= ~AFI_PEX_CTRL_RST_L; 1229 AFI_WR4(sc, port->afi_pex_ctrl, reg); 1230 AFI_RD4(sc, port->afi_pex_ctrl); 1231 DELAY(10); 1232 1233 /* Disable clocks. */ 1234 reg &= ~AFI_PEX_CTRL_CLKREQ_EN; 1235 reg &= ~AFI_PEX_CTRL_REFCLK_EN; 1236 AFI_WR4(sc, port->afi_pex_ctrl, reg); 1237 1238 if (bootverbose) 1239 device_printf(sc->dev, " port %d (%d lane%s): Disabled\n", 1240 port->port_idx, port->num_lanes, 1241 port->num_lanes > 1 ? "s": ""); 1242} 1243 1244static void 1245tegra_pcib_set_bar(struct tegra_pcib_softc *sc, int bar, uint32_t axi, 1246 uint64_t fpci, uint32_t size, int is_memory) 1247{ 1248 uint32_t fpci_reg; 1249 uint32_t axi_reg; 1250 uint32_t size_reg; 1251 1252 axi_reg = axi & ~0xFFF; 1253 size_reg = size >> 12; 1254 fpci_reg = (uint32_t)(fpci >> 8) & ~0xF; 1255 fpci_reg |= is_memory ? 0x1 : 0x0; 1256 AFI_WR4(sc, bars[bar].axi_start, axi_reg); 1257 AFI_WR4(sc, bars[bar].size, size_reg); 1258 AFI_WR4(sc, bars[bar].fpci_start, fpci_reg); 1259} 1260 1261static int 1262tegra_pcib_enable(struct tegra_pcib_softc *sc, uint32_t port) 1263{ 1264 int rv; 1265 int i; 1266 uint32_t reg; 1267 1268 rv = tegra_pcib_enable_fdt_resources(sc); 1269 if (rv != 0) { 1270 device_printf(sc->dev, "Cannot enable FDT resources\n"); 1271 return (rv); 1272 } 1273 /* Enable PLLE control. */ 1274 reg = AFI_RD4(sc, AFI_PLLE_CONTROL); 1275 reg &= ~AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL; 1276 reg |= AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN; 1277 AFI_WR4(sc, AFI_PLLE_CONTROL, reg); 1278 1279 /* Set bias pad. */ 1280 AFI_WR4(sc, AFI_PEXBIAS_CTRL, 0); 1281 1282 /* Configure mode and ports. */ 1283 reg = AFI_RD4(sc, AFI_PCIE_CONFIG); 1284 reg &= ~AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK; 1285 if (sc->lanes_cfg == 0x14) { 1286 if (bootverbose) 1287 device_printf(sc->dev, 1288 "Using x1,x4 configuration\n"); 1289 reg |= AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_XBAR4_1; 1290 } else if (sc->lanes_cfg == 0x12) { 1291 if (bootverbose) 1292 device_printf(sc->dev, 1293 "Using x1,x2 configuration\n"); 1294 reg |= AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_XBAR2_1; 1295 } else { 1296 device_printf(sc->dev, 1297 "Unsupported lanes configuration: 0x%X\n", sc->lanes_cfg); 1298 } 1299 reg |= AFI_PCIE_CONFIG_PCIE_DISABLE_ALL; 1300 for (i = 0; i < TEGRA_PCIB_MAX_PORTS; i++) { 1301 if ((sc->ports[i] != NULL)) 1302 reg &= 1303 ~AFI_PCIE_CONFIG_PCIE_DISABLE(sc->ports[i]->port_idx); 1304 } 1305 AFI_WR4(sc, AFI_PCIE_CONFIG, reg); 1306 1307 /* Enable Gen2 support. */ 1308 reg = AFI_RD4(sc, AFI_FUSE); 1309 reg &= ~AFI_FUSE_PCIE_T0_GEN2_DIS; 1310 AFI_WR4(sc, AFI_FUSE, reg); 1311 1312 /* Enable PCIe phy. */ 1313 rv = phy_enable(sc->dev, sc->phy); 1314 if (rv != 0) { 1315 device_printf(sc->dev, "Cannot enable phy\n"); 1316 return (rv); 1317 } 1318 1319 rv = hwreset_deassert(sc->hwreset_pcie_x); 1320 if (rv != 0) { 1321 device_printf(sc->dev, "Cannot unreset 'pci_x' reset\n"); 1322 return (rv); 1323 } 1324 1325 /* Enable config space. */ 1326 reg = AFI_RD4(sc, AFI_CONFIGURATION); 1327 reg |= AFI_CONFIGURATION_EN_FPCI; 1328 AFI_WR4(sc, AFI_CONFIGURATION, reg); 1329 1330 /* Enable AFI errors. */ 1331 reg = 0; 1332 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_INI_SLVERR); 1333 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_INI_DECERR); 1334 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_TGT_SLVERR); 1335 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_TGT_DECERR); 1336 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_TGT_WRERR); 1337 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_SM_MSG); 1338 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_DFPCI_DECERR); 1339 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_AXI_DECERR); 1340 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_FPCI_TIMEOUT); 1341 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_PE_PRSNT_SENSE); 1342 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_PE_CLKREQ_SENSE); 1343 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_CLKCLAMP_SENSE); 1344 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_RDY4PD_SENSE); 1345 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_P2P_ERROR); 1346 AFI_WR4(sc, AFI_AFI_INTR_ENABLE, reg); 1347 AFI_WR4(sc, AFI_SM_INTR_ENABLE, 0xffffffff); 1348 1349 /* Enable INT, disable MSI. */ 1350 AFI_WR4(sc, AFI_INTR_MASK, AFI_INTR_MASK_INT_MASK); 1351 1352 /* Mask all FPCI errors. */ 1353 AFI_WR4(sc, AFI_FPCI_ERROR_MASKS, 0); 1354 1355 /* Setup AFI translation windows. */ 1356 /* BAR 0 - type 1 extended configuration. */ 1357 tegra_pcib_set_bar(sc, 0, rman_get_start(sc->cfg_mem_res), 1358 FPCI_MAP_EXT_TYPE1_CONFIG, rman_get_size(sc->cfg_mem_res), 0); 1359 1360 /* BAR 1 - downstream I/O. */ 1361 tegra_pcib_set_bar(sc, 1, sc->io_range.host, FPCI_MAP_IO, 1362 sc->io_range.size, 0); 1363 1364 /* BAR 2 - downstream prefetchable memory 1:1. */ 1365 tegra_pcib_set_bar(sc, 2, sc->pref_mem_range.host, 1366 sc->pref_mem_range.host, sc->pref_mem_range.size, 1); 1367 1368 /* BAR 3 - downstream not prefetchable memory 1:1 .*/ 1369 tegra_pcib_set_bar(sc, 3, sc->mem_range.host, 1370 sc->mem_range.host, sc->mem_range.size, 1); 1371 1372 /* BAR 3-8 clear. */ 1373 tegra_pcib_set_bar(sc, 4, 0, 0, 0, 0); 1374 tegra_pcib_set_bar(sc, 5, 0, 0, 0, 0); 1375 tegra_pcib_set_bar(sc, 6, 0, 0, 0, 0); 1376 tegra_pcib_set_bar(sc, 7, 0, 0, 0, 0); 1377 tegra_pcib_set_bar(sc, 8, 0, 0, 0, 0); 1378 1379 /* MSI BAR - clear. */ 1380 tegra_pcib_set_bar(sc, 9, 0, 0, 0, 0); 1381 return(0); 1382} 1383 1384#ifdef TEGRA_PCIB_MSI_ENABLE 1385static int 1386tegra_pcib_attach_msi(device_t dev) 1387{ 1388 struct tegra_pcib_softc *sc; 1389 uint32_t reg; 1390 int i, rv; 1391 1392 sc = device_get_softc(dev); 1393 1394 sc->msi_page = kmem_alloc_contig(kernel_arena, PAGE_SIZE, M_WAITOK, 1395 0, BUS_SPACE_MAXADDR, PAGE_SIZE, 0, VM_MEMATTR_DEFAULT); 1396 1397 /* MSI BAR */ 1398 tegra_pcib_set_bar(sc, 9, vtophys(sc->msi_page), vtophys(sc->msi_page), 1399 PAGE_SIZE, 0); 1400 1401 /* Disble and clear all interrupts. */ 1402 for (i = 0; i < AFI_MSI_REGS; i++) { 1403 AFI_WR4(sc, AFI_MSI_EN_VEC(i), 0); 1404 AFI_WR4(sc, AFI_MSI_VEC(i), 0xFFFFFFFF); 1405 } 1406 rv = bus_setup_intr(dev, sc->msi_irq_res, INTR_TYPE_BIO | INTR_MPSAFE, 1407 tegra_pcib_msi_intr, NULL, sc, &sc->msi_intr_cookie); 1408 if (rv != 0) { 1409 device_printf(dev, "cannot setup MSI interrupt handler\n"); 1410 rv = ENXIO; 1411 goto out; 1412 } 1413 1414 if (tegra_pcib_msi_attach(sc) != 0) { 1415 device_printf(dev, "WARNING: unable to attach PIC\n"); 1416 tegra_pcib_msi_detach(sc); 1417 goto out; 1418 } 1419 1420 /* Unmask MSI interrupt. */ 1421 reg = AFI_RD4(sc, AFI_INTR_MASK); 1422 reg |= AFI_INTR_MASK_MSI_MASK; 1423 AFI_WR4(sc, AFI_INTR_MASK, reg); 1424 1425out: 1426 return (rv); 1427} 1428#endif 1429 1430static int 1431tegra_pcib_probe(device_t dev) 1432{ 1433 if (!ofw_bus_status_okay(dev)) 1434 return (ENXIO); 1435 1436 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data != 0) { 1437 device_set_desc(dev, "Nvidia Integrated PCI/PCI-E Controller"); 1438 return (BUS_PROBE_DEFAULT); 1439 } 1440 return (ENXIO); 1441} 1442 1443static int 1444tegra_pcib_attach(device_t dev) 1445{ 1446 struct tegra_pcib_softc *sc; 1447 phandle_t node; 1448 uint32_t unit; 1449 int rv; 1450 int rid; 1451 struct tegra_pcib_port *port; 1452 int i; 1453 1454 sc = device_get_softc(dev); 1455 sc->dev = dev; 1456 unit = fdt_get_unit(dev); 1457 mtx_init(&sc->mtx, "msi_mtx", NULL, MTX_DEF); 1458 1459 node = ofw_bus_get_node(dev); 1460 1461 rv = tegra_pcib_parse_fdt_resources(sc, node); 1462 if (rv != 0) { 1463 device_printf(dev, "Cannot get FDT resources\n"); 1464 return (rv); 1465 } 1466 1467 /* Allocate bus_space resources. */ 1468 rid = 0; 1469 sc->pads_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1470 RF_ACTIVE); 1471 if (sc->pads_mem_res == NULL) { 1472 device_printf(dev, "Cannot allocate PADS register\n"); 1473 rv = ENXIO; 1474 goto out; 1475 } 1476 /* 1477 * XXX - FIXME 1478 * tag for config space is not filled when RF_ALLOCATED flag is used. 1479 */ 1480 sc->bus_tag = rman_get_bustag(sc->pads_mem_res); 1481 1482 rid = 1; 1483 sc->afi_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1484 RF_ACTIVE); 1485 if (sc->afi_mem_res == NULL) { 1486 device_printf(dev, "Cannot allocate AFI register\n"); 1487 rv = ENXIO; 1488 goto out; 1489 } 1490 1491 rid = 2; 1492 sc->cfg_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1493 RF_ALLOCATED); 1494 if (sc->cfg_mem_res == NULL) { 1495 device_printf(dev, "Cannot allocate config space memory\n"); 1496 rv = ENXIO; 1497 goto out; 1498 } 1499 sc->cfg_base_addr = rman_get_start(sc->cfg_mem_res); 1500 1501 1502 /* Map RP slots */ 1503 for (i = 0; i < TEGRA_PCIB_MAX_PORTS; i++) { 1504 if (sc->ports[i] == NULL) 1505 continue; 1506 port = sc->ports[i]; 1507 rv = bus_space_map(sc->bus_tag, port->rp_base_addr, 1508 port->rp_size, 0, &port->cfg_handle); 1509 if (rv != 0) { 1510 device_printf(sc->dev, "Cannot allocate memory for " 1511 "port: %d\n", i); 1512 rv = ENXIO; 1513 goto out; 1514 } 1515 } 1516 1517 /* 1518 * Get PCI interrupt 1519 */ 1520 rid = 0; 1521 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1522 RF_ACTIVE | RF_SHAREABLE); 1523 if (sc->irq_res == NULL) { 1524 device_printf(dev, "Cannot allocate IRQ resources\n"); 1525 rv = ENXIO; 1526 goto out; 1527 } 1528 1529 rid = 1; 1530 sc->msi_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1531 RF_ACTIVE); 1532 if (sc->irq_res == NULL) { 1533 device_printf(dev, "Cannot allocate MSI IRQ resources\n"); 1534 rv = ENXIO; 1535 goto out; 1536 } 1537 1538 sc->ofw_pci.sc_range_mask = 0x3; 1539 rv = ofw_pci_init(dev); 1540 if (rv != 0) 1541 goto out; 1542 1543 rv = tegra_pcib_decode_ranges(sc, sc->ofw_pci.sc_range, 1544 sc->ofw_pci.sc_nrange); 1545 if (rv != 0) 1546 goto out; 1547 1548 if (bus_setup_intr(dev, sc->irq_res, INTR_TYPE_BIO | INTR_MPSAFE, 1549 tegra_pci_intr, NULL, sc, &sc->intr_cookie)) { 1550 device_printf(dev, "cannot setup interrupt handler\n"); 1551 rv = ENXIO; 1552 goto out; 1553 } 1554 1555 /* 1556 * Enable PCIE device. 1557 */ 1558 rv = tegra_pcib_enable(sc, unit); 1559 if (rv != 0) 1560 goto out; 1561 for (i = 0; i < TEGRA_PCIB_MAX_PORTS; i++) { 1562 if (sc->ports[i] == NULL) 1563 continue; 1564 if (sc->ports[i]->enabled) 1565 tegra_pcib_port_enable(sc, i); 1566 else 1567 tegra_pcib_port_disable(sc, i); 1568 } 1569 1570#ifdef TEGRA_PCIB_MSI_ENABLE 1571 rv = tegra_pcib_attach_msi(dev); 1572 if (rv != 0) 1573 goto out; 1574#endif 1575 device_add_child(dev, "pci", -1); 1576 1577 return (bus_generic_attach(dev)); 1578 1579out: 1580 1581 return (rv); 1582} 1583 1584 1585static device_method_t tegra_pcib_methods[] = { 1586 /* Device interface */ 1587 DEVMETHOD(device_probe, tegra_pcib_probe), 1588 DEVMETHOD(device_attach, tegra_pcib_attach), 1589 1590 /* Bus interface */ 1591 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 1592 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 1593 1594 /* pcib interface */ 1595 DEVMETHOD(pcib_maxslots, tegra_pcib_maxslots), 1596 DEVMETHOD(pcib_read_config, tegra_pcib_read_config), 1597 DEVMETHOD(pcib_write_config, tegra_pcib_write_config), 1598 DEVMETHOD(pcib_route_interrupt, tegra_pcib_route_interrupt), 1599 DEVMETHOD(pcib_alloc_msi, tegra_pcib_alloc_msi), 1600 DEVMETHOD(pcib_release_msi, tegra_pcib_release_msi), 1601 DEVMETHOD(pcib_map_msi, tegra_pcib_map_msi), 1602 1603#ifdef TEGRA_PCIB_MSI_ENABLE 1604 /* MSI/MSI-X */ 1605 DEVMETHOD(msi_alloc_msi, tegra_pcib_msi_alloc_msi), 1606 DEVMETHOD(msi_release_msi, tegra_pcib_msi_release_msi), 1607 DEVMETHOD(msi_map_msi, tegra_pcib_msi_map_msi), 1608 1609 /* Interrupt controller interface */ 1610 DEVMETHOD(pic_disable_intr, tegra_pcib_msi_disable_intr), 1611 DEVMETHOD(pic_enable_intr, tegra_pcib_msi_enable_intr), 1612 DEVMETHOD(pic_setup_intr, tegra_pcib_msi_setup_intr), 1613 DEVMETHOD(pic_teardown_intr, tegra_pcib_msi_teardown_intr), 1614 DEVMETHOD(pic_post_filter, tegra_pcib_msi_post_filter), 1615 DEVMETHOD(pic_post_ithread, tegra_pcib_msi_post_ithread), 1616 DEVMETHOD(pic_pre_ithread, tegra_pcib_msi_pre_ithread), 1617#endif 1618 1619 /* OFW bus interface */ 1620 DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat), 1621 DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model), 1622 DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name), 1623 DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node), 1624 DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type), 1625 1626 DEVMETHOD_END 1627}; 1628 1629static devclass_t pcib_devclass; 1630DEFINE_CLASS_1(pcib, tegra_pcib_driver, tegra_pcib_methods, 1631 sizeof(struct tegra_pcib_softc), ofw_pci_driver); 1632DRIVER_MODULE(pcib, simplebus, tegra_pcib_driver, pcib_devclass, 1633 NULL, NULL); 1634