tegra_pcie.c revision 308326
1/*- 2 * Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD: stable/11/sys/arm/nvidia/tegra_pcie.c 308326 2016-11-05 04:32:46Z mmel $"); 29 30/* 31 * Nvidia Integrated PCI/PCI-Express controller driver. 32 */ 33 34#include <sys/param.h> 35#include <sys/systm.h> 36#include <sys/kernel.h> 37#include <sys/lock.h> 38#include <sys/malloc.h> 39#include <sys/module.h> 40#include <sys/mutex.h> 41#include <sys/queue.h> 42#include <sys/bus.h> 43#include <sys/rman.h> 44#include <sys/endian.h> 45#include <sys/devmap.h> 46 47#include <machine/intr.h> 48 49#include <vm/vm.h> 50#include <vm/pmap.h> 51 52#include <dev/extres/clk/clk.h> 53#include <dev/extres/hwreset/hwreset.h> 54#include <dev/extres/phy/phy.h> 55#include <dev/extres/regulator/regulator.h> 56#include <dev/fdt/fdt_common.h> 57#include <dev/ofw/ofw_bus.h> 58#include <dev/ofw/ofw_bus_subr.h> 59#include <dev/ofw/ofw_pci.h> 60#include <dev/pci/pcivar.h> 61#include <dev/pci/pcireg.h> 62#include <dev/pci/pcib_private.h> 63 64#include <machine/resource.h> 65#include <machine/bus.h> 66 67#include "ofw_bus_if.h" 68#include "pcib_if.h" 69 70#include <arm/nvidia/tegra_pmc.h> 71 72/* --- Move to ofw_pci.c/.h ----------------------- */ 73 74struct tegra_pci_range { 75 /* parsed phys.hi */ 76 int nonrelocatable; 77 int prefetchable; 78 int aliased; 79 int space_code; /* In native format (not shifted)*/ 80 int bus; 81 int device; 82 int function; 83 int reg; 84 pci_addr_t pci_addr; /* PCI Address */ 85 bus_addr_t host_addr; /* Host bus address*/ 86 bus_size_t size; /* Range size */ 87}; 88 89static int 90tegra_pci_get_ranges(phandle_t node, struct tegra_pci_range **ranges) 91{ 92 int host_address_cells, pci_address_cells, size_cells; 93 cell_t *base_ranges; 94 ssize_t nbase_ranges; 95 int nranges; 96 int i, j, k; 97 uint32_t flags; 98 uint64_t tmp; 99 100 host_address_cells = 1; 101 pci_address_cells = 3; 102 size_cells = 2; 103 OF_getencprop(OF_parent(node), "#address-cells", &host_address_cells, 104 sizeof(host_address_cells)); 105 OF_getencprop(node, "#address-cells", &pci_address_cells, 106 sizeof(pci_address_cells)); 107 OF_getencprop(node, "#size-cells", &size_cells, sizeof(size_cells)); 108 109 nbase_ranges = OF_getproplen(node, "ranges"); 110 if (nbase_ranges <= 0) 111 return (-1); 112 nranges = nbase_ranges / sizeof(cell_t) / 113 (pci_address_cells + host_address_cells + size_cells); 114 115 *ranges = malloc(nranges * sizeof(struct tegra_pci_range), 116 M_DEVBUF, M_WAITOK); 117 base_ranges = malloc(nbase_ranges, M_DEVBUF, M_WAITOK); 118 OF_getencprop(node, "ranges", base_ranges, nbase_ranges); 119 120 for (i = 0, j = 0; i < nranges; i++) { 121 flags = base_ranges[j++]; 122 (*ranges)[i].nonrelocatable = 123 flags & OFW_PCI_PHYS_HI_NONRELOCATABLE ? 1 : 0; 124 (*ranges)[i].prefetchable = 125 flags & OFW_PCI_PHYS_HI_PREFETCHABLE ? 1 : 0; 126 (*ranges)[i].aliased = 127 flags & OFW_PCI_PHYS_HI_ALIASED ? 1 : 0; 128 (*ranges)[i].space_code = flags & OFW_PCI_PHYS_HI_SPACEMASK; 129 (*ranges)[i].bus = OFW_PCI_PHYS_HI_BUS(flags); 130 (*ranges)[i].device = OFW_PCI_PHYS_HI_DEVICE(flags); 131 (*ranges)[i].function = OFW_PCI_PHYS_HI_FUNCTION(flags); 132 (*ranges)[i].reg = flags & OFW_PCI_PHYS_HI_REGISTERMASK; 133 134 tmp = 0; 135 for (k = 0; k < pci_address_cells - 1; k++) { 136 tmp <<= 32; 137 tmp |= base_ranges[j++]; 138 } 139 (*ranges)[i].pci_addr = (pci_addr_t)tmp; 140 141 tmp = 0; 142 for (k = 0; k < host_address_cells; k++) { 143 tmp <<= 32; 144 tmp |= base_ranges[j++]; 145 } 146 (*ranges)[i].host_addr = (bus_addr_t)tmp; 147 tmp = 0; 148 149 for (k = 0; k < size_cells; k++) { 150 tmp <<= 32; 151 tmp |= base_ranges[j++]; 152 } 153 (*ranges)[i].size = (bus_size_t)tmp; 154 } 155 156 free(base_ranges, M_DEVBUF); 157 return (nranges); 158} 159 160/* -------------------------------------------------------------------------- */ 161#define AFI_AXI_BAR0_SZ 0x000 162#define AFI_AXI_BAR1_SZ 0x004 163#define AFI_AXI_BAR2_SZ 0x008 164#define AFI_AXI_BAR3_SZ 0x00c 165#define AFI_AXI_BAR4_SZ 0x010 166#define AFI_AXI_BAR5_SZ 0x014 167#define AFI_AXI_BAR0_START 0x018 168#define AFI_AXI_BAR1_START 0x01c 169#define AFI_AXI_BAR2_START 0x020 170#define AFI_AXI_BAR3_START 0x024 171#define AFI_AXI_BAR4_START 0x028 172#define AFI_AXI_BAR5_START 0x02c 173#define AFI_FPCI_BAR0 0x030 174#define AFI_FPCI_BAR1 0x034 175#define AFI_FPCI_BAR2 0x038 176#define AFI_FPCI_BAR3 0x03c 177#define AFI_FPCI_BAR4 0x040 178#define AFI_FPCI_BAR5 0x044 179#define AFI_MSI_BAR_SZ 0x060 180#define AFI_MSI_FPCI_BAR_ST 0x064 181#define AFI_MSI_AXI_BAR_ST 0x068 182 183 184#define AFI_AXI_BAR6_SZ 0x134 185#define AFI_AXI_BAR7_SZ 0x138 186#define AFI_AXI_BAR8_SZ 0x13c 187#define AFI_AXI_BAR6_START 0x140 188#define AFI_AXI_BAR7_START 0x144 189#define AFI_AXI_BAR8_START 0x148 190#define AFI_FPCI_BAR6 0x14c 191#define AFI_FPCI_BAR7 0x150 192#define AFI_FPCI_BAR8 0x154 193 194#define AFI_CONFIGURATION 0x0ac 195#define AFI_CONFIGURATION_EN_FPCI (1 << 0) 196 197#define AFI_FPCI_ERROR_MASKS 0x0b0 198#define AFI_INTR_MASK 0x0b4 199#define AFI_INTR_MASK_MSI_MASK (1 << 8) 200#define AFI_INTR_MASK_INT_MASK (1 << 0) 201 202#define AFI_INTR_CODE 0x0b8 203#define AFI_INTR_CODE_MASK 0xf 204#define AFI_INTR_CODE_INT_CODE_INI_SLVERR 1 205#define AFI_INTR_CODE_INT_CODE_INI_DECERR 2 206#define AFI_INTR_CODE_INT_CODE_TGT_SLVERR 3 207#define AFI_INTR_CODE_INT_CODE_TGT_DECERR 4 208#define AFI_INTR_CODE_INT_CODE_TGT_WRERR 5 209#define AFI_INTR_CODE_INT_CODE_SM_MSG 6 210#define AFI_INTR_CODE_INT_CODE_DFPCI_DECERR 7 211#define AFI_INTR_CODE_INT_CODE_AXI_DECERR 8 212#define AFI_INTR_CODE_INT_CODE_FPCI_TIMEOUT 9 213#define AFI_INTR_CODE_INT_CODE_PE_PRSNT_SENSE 10 214#define AFI_INTR_CODE_INT_CODE_PE_CLKREQ_SENSE 11 215#define AFI_INTR_CODE_INT_CODE_CLKCLAMP_SENSE 12 216#define AFI_INTR_CODE_INT_CODE_RDY4PD_SENSE 13 217#define AFI_INTR_CODE_INT_CODE_P2P_ERROR 14 218 219 220#define AFI_INTR_SIGNATURE 0x0bc 221#define AFI_UPPER_FPCI_ADDRESS 0x0c0 222#define AFI_SM_INTR_ENABLE 0x0c4 223#define AFI_SM_INTR_RP_DEASSERT (1 << 14) 224#define AFI_SM_INTR_RP_ASSERT (1 << 13) 225#define AFI_SM_INTR_HOTPLUG (1 << 12) 226#define AFI_SM_INTR_PME (1 << 11) 227#define AFI_SM_INTR_FATAL_ERROR (1 << 10) 228#define AFI_SM_INTR_UNCORR_ERROR (1 << 9) 229#define AFI_SM_INTR_CORR_ERROR (1 << 8) 230#define AFI_SM_INTR_INTD_DEASSERT (1 << 7) 231#define AFI_SM_INTR_INTC_DEASSERT (1 << 6) 232#define AFI_SM_INTR_INTB_DEASSERT (1 << 5) 233#define AFI_SM_INTR_INTA_DEASSERT (1 << 4) 234#define AFI_SM_INTR_INTD_ASSERT (1 << 3) 235#define AFI_SM_INTR_INTC_ASSERT (1 << 2) 236#define AFI_SM_INTR_INTB_ASSERT (1 << 1) 237#define AFI_SM_INTR_INTA_ASSERT (1 << 0) 238 239#define AFI_AFI_INTR_ENABLE 0x0c8 240#define AFI_AFI_INTR_ENABLE_CODE(code) (1 << (code)) 241 242#define AFI_PCIE_CONFIG 0x0f8 243#define AFI_PCIE_CONFIG_PCIE_DISABLE(x) (1 << ((x) + 1)) 244#define AFI_PCIE_CONFIG_PCIE_DISABLE_ALL 0x6 245#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK (0xf << 20) 246#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_XBAR2_1 (0x0 << 20) 247#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_XBAR4_1 (0x1 << 20) 248 249#define AFI_FUSE 0x104 250#define AFI_FUSE_PCIE_T0_GEN2_DIS (1 << 2) 251 252#define AFI_PEX0_CTRL 0x110 253#define AFI_PEX1_CTRL 0x118 254#define AFI_PEX2_CTRL 0x128 255#define AFI_PEX_CTRL_OVERRIDE_EN (1 << 4) 256#define AFI_PEX_CTRL_REFCLK_EN (1 << 3) 257#define AFI_PEX_CTRL_CLKREQ_EN (1 << 1) 258#define AFI_PEX_CTRL_RST_L (1 << 0) 259 260#define AFI_AXI_BAR6_SZ 0x134 261#define AFI_AXI_BAR7_SZ 0x138 262#define AFI_AXI_BAR8_SZ 0x13c 263#define AFI_AXI_BAR6_START 0x140 264#define AFI_AXI_BAR7_START 0x144 265#define AFI_AXI_BAR8_START 0x148 266#define AFI_FPCI_BAR6 0x14c 267#define AFI_FPCI_BAR7 0x150 268#define AFI_FPCI_BAR8 0x154 269#define AFI_PLLE_CONTROL 0x160 270#define AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL (1 << 9) 271#define AFI_PLLE_CONTROL_BYPASS_PCIE2PLLE_CONTROL (1 << 8) 272#define AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN (1 << 1) 273#define AFI_PLLE_CONTROL_PCIE2PLLE_CONTROL_EN (1 << 0) 274 275#define AFI_PEXBIAS_CTRL 0x168 276 277/* FPCI Address space */ 278#define FPCI_MAP_IO 0xfdfc000000ULL 279#define FPCI_MAP_TYPE0_CONFIG 0xfdfc000000ULL 280#define FPCI_MAP_TYPE1_CONFIG 0xfdff000000ULL 281#define FPCI_MAP_EXT_TYPE0_CONFIG 0xfe00000000ULL 282#define FPCI_MAP_EXT_TYPE1_CONFIG 0xfe10000000ULL 283 284/* Configuration space */ 285#define RP_VEND_XP 0x00000F00 286#define RP_VEND_XP_DL_UP (1 << 30) 287 288#define RP_PRIV_MISC 0x00000FE0 289#define RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT (0xE << 0) 290#define RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT (0xF << 0) 291 292#define RP_LINK_CONTROL_STATUS 0x00000090 293#define RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE 0x20000000 294#define RP_LINK_CONTROL_STATUS_LINKSTAT_MASK 0x3fff0000 295 296/* Wait 50 ms (per port) for link. */ 297#define TEGRA_PCIE_LINKUP_TIMEOUT 50000 298 299#define DEBUG 300#ifdef DEBUG 301#define debugf(fmt, args...) do { printf(fmt,##args); } while (0) 302#else 303#define debugf(fmt, args...) 304#endif 305 306/* 307 * Configuration space format: 308 * [27:24] extended register 309 * [23:16] bus 310 * [15:11] slot (device) 311 * [10: 8] function 312 * [ 7: 0] register 313 */ 314#define PCI_CFG_EXT_REG(reg) ((((reg) >> 8) & 0x0f) << 24) 315#define PCI_CFG_BUS(bus) (((bus) & 0xff) << 16) 316#define PCI_CFG_DEV(dev) (((dev) & 0x1f) << 11) 317#define PCI_CFG_FUN(fun) (((fun) & 0x07) << 8) 318#define PCI_CFG_BASE_REG(reg) ((reg) & 0xff) 319 320#define PADS_WR4(_sc, _r, _v) bus_write_4((_sc)-pads_mem_res, (_r), (_v)) 321#define PADS_RD4(_sc, _r) bus_read_4((_sc)->pads_mem_res, (_r)) 322#define AFI_WR4(_sc, _r, _v) bus_write_4((_sc)->afi_mem_res, (_r), (_v)) 323#define AFI_RD4(_sc, _r) bus_read_4((_sc)->afi_mem_res, (_r)) 324 325static struct { 326 bus_size_t axi_start; 327 bus_size_t fpci_start; 328 bus_size_t size; 329} bars[] = { 330 {AFI_AXI_BAR0_START, AFI_FPCI_BAR0, AFI_AXI_BAR0_SZ}, /* BAR 0 */ 331 {AFI_AXI_BAR1_START, AFI_FPCI_BAR1, AFI_AXI_BAR1_SZ}, /* BAR 1 */ 332 {AFI_AXI_BAR2_START, AFI_FPCI_BAR2, AFI_AXI_BAR2_SZ}, /* BAR 2 */ 333 {AFI_AXI_BAR3_START, AFI_FPCI_BAR3, AFI_AXI_BAR3_SZ}, /* BAR 3 */ 334 {AFI_AXI_BAR4_START, AFI_FPCI_BAR4, AFI_AXI_BAR4_SZ}, /* BAR 4 */ 335 {AFI_AXI_BAR5_START, AFI_FPCI_BAR5, AFI_AXI_BAR5_SZ}, /* BAR 5 */ 336 {AFI_AXI_BAR6_START, AFI_FPCI_BAR6, AFI_AXI_BAR6_SZ}, /* BAR 6 */ 337 {AFI_AXI_BAR7_START, AFI_FPCI_BAR7, AFI_AXI_BAR7_SZ}, /* BAR 7 */ 338 {AFI_AXI_BAR8_START, AFI_FPCI_BAR8, AFI_AXI_BAR8_SZ}, /* BAR 8 */ 339 {AFI_MSI_AXI_BAR_ST, AFI_MSI_FPCI_BAR_ST, AFI_MSI_BAR_SZ}, /* MSI 9 */ 340}; 341 342/* Compatible devices. */ 343static struct ofw_compat_data compat_data[] = { 344 {"nvidia,tegra124-pcie", 1}, 345 {NULL, 0}, 346}; 347 348struct tegra_pcib_port { 349 int enabled; 350 int port_idx; /* chip port index */ 351 int num_lanes; /* number of lanes */ 352 bus_size_t afi_pex_ctrl; /* offset of afi_pex_ctrl */ 353 354 /* Config space properties. */ 355 bus_addr_t rp_base_addr; /* PA of config window */ 356 bus_size_t rp_size; /* size of config window */ 357 bus_space_handle_t cfg_handle; /* handle of config window */ 358}; 359 360#define TEGRA_PCIB_MAX_PORTS 3 361struct tegra_pcib_softc { 362 device_t dev; 363 struct mtx mtx; 364 struct ofw_bus_iinfo pci_iinfo; 365 struct rman pref_mem_rman; 366 struct rman mem_rman; 367 struct rman io_rman; 368 struct resource *pads_mem_res; 369 struct resource *afi_mem_res; 370 struct resource *cfg_mem_res; 371 struct resource *irq_res; 372 struct resource *msi_irq_res; 373 void *intr_cookie; 374 void *msi_intr_cookie; 375 376 struct tegra_pci_range mem_range; 377 struct tegra_pci_range pref_mem_range; 378 struct tegra_pci_range io_range; 379 380 phy_t phy; 381 clk_t clk_pex; 382 clk_t clk_afi; 383 clk_t clk_pll_e; 384 clk_t clk_cml; 385 hwreset_t hwreset_pex; 386 hwreset_t hwreset_afi; 387 hwreset_t hwreset_pcie_x; 388 regulator_t supply_avddio_pex; 389 regulator_t supply_dvddio_pex; 390 regulator_t supply_avdd_pex_pll; 391 regulator_t supply_hvdd_pex; 392 regulator_t supply_hvdd_pex_pll_e; 393 regulator_t supply_vddio_pex_ctl; 394 regulator_t supply_avdd_pll_erefe; 395 396 int busnr; /* host bridge bus number */ 397 uint32_t msi_bitmap; 398 bus_addr_t cfg_base_addr; /* base address of config */ 399 bus_size_t cfg_cur_offs; /* currently mapped window */ 400 bus_space_handle_t cfg_handle; /* handle of config window */ 401 bus_space_tag_t bus_tag; /* tag of config window */ 402 int lanes_cfg; 403 int num_ports; 404 struct tegra_pcib_port *ports[TEGRA_PCIB_MAX_PORTS]; 405}; 406 407/* ------------------------------------------------------------------------- */ 408/* 409 * Resource manager 410 */ 411static int 412tegra_pcib_rman_init(struct tegra_pcib_softc *sc) 413{ 414 int err; 415 char buf[64]; 416 417 /* Memory management. */ 418 sc->pref_mem_rman.rm_type = RMAN_ARRAY; 419 snprintf(buf, sizeof(buf), "%s prefetchable memory space", 420 device_get_nameunit(sc->dev)); 421 sc->pref_mem_rman.rm_descr = strdup(buf, M_DEVBUF); 422 err = rman_init(&sc->pref_mem_rman); 423 if (err) 424 return (err); 425 426 sc->mem_rman.rm_type = RMAN_ARRAY; 427 snprintf(buf, sizeof(buf), "%s non prefetchable memory space", 428 device_get_nameunit(sc->dev)); 429 sc->mem_rman.rm_descr = strdup(buf, M_DEVBUF); 430 err = rman_init(&sc->mem_rman); 431 if (err) 432 return (err); 433 434 sc->io_rman.rm_type = RMAN_ARRAY; 435 snprintf(buf, sizeof(buf), "%s I/O space", 436 device_get_nameunit(sc->dev)); 437 sc->io_rman.rm_descr = strdup(buf, M_DEVBUF); 438 err = rman_init(&sc->io_rman); 439 if (err) { 440 rman_fini(&sc->mem_rman); 441 return (err); 442 } 443 444 err = rman_manage_region(&sc->pref_mem_rman, 445 sc->pref_mem_range.host_addr, 446 sc->pref_mem_range.host_addr + sc->pref_mem_range.size - 1); 447 if (err) 448 goto error; 449 err = rman_manage_region(&sc->mem_rman, 450 sc->mem_range.host_addr, 451 sc->mem_range.host_addr + sc->mem_range.size - 1); 452 if (err) 453 goto error; 454 err = rman_manage_region(&sc->io_rman, 455 sc->io_range.pci_addr, 456 sc->io_range.pci_addr + sc->io_range.size - 1); 457 if (err) 458 goto error; 459 return (0); 460 461error: 462 rman_fini(&sc->pref_mem_rman); 463 rman_fini(&sc->mem_rman); 464 rman_fini(&sc->io_rman); 465 return (err); 466} 467 468static struct rman * 469tegra_pcib_rman(struct tegra_pcib_softc *sc, int type, u_int flags) 470{ 471 472 switch (type) { 473 case SYS_RES_IOPORT: 474 return (&sc->io_rman); 475 case SYS_RES_MEMORY: 476 if (flags & RF_PREFETCHABLE) 477 return (&sc->pref_mem_rman); 478 else 479 return (&sc->mem_rman); 480 default: 481 break; 482 } 483 484 return (NULL); 485} 486 487static struct resource * 488tegra_pcib_alloc_resource(device_t dev, device_t child, int type, int *rid, 489 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 490{ 491 struct tegra_pcib_softc *sc; 492 struct rman *rm; 493 struct resource *res; 494 495 debugf("%s: enter %d start %#jx end %#jx count %#jx\n", __func__, 496 type, start, end, count); 497 sc = device_get_softc(dev); 498 499#if defined(NEW_PCIB) && defined(PCI_RES_BUS) 500 if (type == PCI_RES_BUS) { 501 return (pci_domain_alloc_bus(0, child, rid, start, end, count, 502 flags)); 503 } 504#endif 505 506 rm = tegra_pcib_rman(sc, type, flags); 507 508 if (rm == NULL) { 509 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), dev, 510 type, rid, start, end, count, flags); 511 512 return (res); 513 } 514 515 if (bootverbose) { 516 device_printf(dev, 517 "rman_reserve_resource: start=%#jx, end=%#jx, count=%#jx\n", 518 start, end, count); 519 } 520 521 res = rman_reserve_resource(rm, start, end, count, flags, child); 522 if (res == NULL) 523 goto fail; 524 rman_set_rid(res, *rid); 525 if (flags & RF_ACTIVE) { 526 if (bus_activate_resource(child, type, *rid, res)) { 527 rman_release_resource(res); 528 goto fail; 529 } 530 } 531 return (res); 532 533fail: 534 if (bootverbose) { 535 device_printf(dev, "%s FAIL: type=%d, rid=%d, " 536 "start=%016jx, end=%016jx, count=%016jx, flags=%x\n", 537 __func__, type, *rid, start, end, count, flags); 538 } 539 540 return (NULL); 541} 542 543static int 544tegra_pcib_release_resource(device_t dev, device_t child, int type, int rid, 545 struct resource *res) 546{ 547 struct tegra_pcib_softc *sc; 548 struct rman *rm; 549 550 sc = device_get_softc(dev); 551 debugf("%s: %d rid %x\n", __func__, type, rid); 552 553#if defined(NEW_PCIB) && defined(PCI_RES_BUS) 554 if (type == PCI_RES_BUS) 555 return (pci_domain_release_bus(0, child, rid, res)); 556#endif 557 558 rm = tegra_pcib_rman(sc, type, rman_get_flags(res)); 559 if (rm != NULL) { 560 KASSERT(rman_is_region_manager(res, rm), ("rman mismatch")); 561 rman_release_resource(res); 562 } 563 564 return (bus_generic_release_resource(dev, child, type, rid, res)); 565} 566 567static int 568tegra_pcib_adjust_resource(device_t dev, device_t child, int type, 569 struct resource *res, rman_res_t start, rman_res_t end) 570{ 571 struct tegra_pcib_softc *sc; 572 struct rman *rm; 573 574 sc = device_get_softc(dev); 575 debugf("%s: %d start %jx end %jx \n", __func__, type, start, end); 576 577#if defined(NEW_PCIB) && defined(PCI_RES_BUS) 578 if (type == PCI_RES_BUS) 579 return (pci_domain_adjust_bus(0, child, res, start, end)); 580#endif 581 582 rm = tegra_pcib_rman(sc, type, rman_get_flags(res)); 583 if (rm != NULL) 584 return (rman_adjust_resource(res, start, end)); 585 return (bus_generic_adjust_resource(dev, child, type, res, start, end)); 586} 587extern bus_space_tag_t fdtbus_bs_tag; 588static int 589tegra_pcib_pcie_activate_resource(device_t dev, device_t child, int type, 590 int rid, struct resource *r) 591{ 592 struct tegra_pcib_softc *sc; 593 vm_offset_t start; 594 void *p; 595 int rv; 596 597 sc = device_get_softc(dev); 598 rv = rman_activate_resource(r); 599 if (rv != 0) 600 return (rv); 601 switch(type) { 602 case SYS_RES_IOPORT: 603 start = rman_get_start(r) + sc->io_range.host_addr; 604 break; 605 default: 606 start = rman_get_start(r); 607 rman_get_start(r); 608 break; 609 } 610 611 if (bootverbose) 612 printf("%s: start %zx, len %jd\n", __func__, start, 613 rman_get_size(r)); 614 615 p = pmap_mapdev(start, (vm_size_t)rman_get_size(r)); 616 rman_set_virtual(r, p); 617 rman_set_bustag(r, fdtbus_bs_tag); 618 rman_set_bushandle(r, (u_long)p); 619 return (0); 620} 621 622/* ------------------------------------------------------------------------- */ 623/* 624 * IVARs 625 */ 626static int 627tegra_pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 628{ 629 struct tegra_pcib_softc *sc = device_get_softc(dev); 630 631 switch (which) { 632 case PCIB_IVAR_BUS: 633 *result = sc->busnr; 634 return (0); 635 case PCIB_IVAR_DOMAIN: 636 *result = device_get_unit(dev); 637 return (0); 638 } 639 640 return (ENOENT); 641} 642 643static int 644tegra_pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 645{ 646 struct tegra_pcib_softc *sc = device_get_softc(dev); 647 648 switch (which) { 649 case PCIB_IVAR_BUS: 650 sc->busnr = value; 651 return (0); 652 } 653 654 return (ENOENT); 655} 656 657static int 658tegra_pcib_maxslots(device_t dev) 659{ 660 return (16); 661} 662 663 664static int 665tegra_pcib_route_interrupt(device_t bus, device_t dev, int pin) 666{ 667 struct tegra_pcib_softc *sc; 668 669 sc = device_get_softc(bus); 670 device_printf(bus, "route pin %d for device %d.%d to %ju\n", 671 pin, pci_get_slot(dev), pci_get_function(dev), 672 rman_get_start(sc->irq_res)); 673 674 return (rman_get_start(sc->irq_res)); 675} 676 677static int 678tegra_pcbib_map_cfg(struct tegra_pcib_softc *sc, u_int bus, u_int slot, 679 u_int func, u_int reg) 680{ 681 bus_size_t offs; 682 int rv; 683 684 offs = sc->cfg_base_addr; 685 offs |= PCI_CFG_BUS(bus) | PCI_CFG_DEV(slot) | PCI_CFG_FUN(func) | 686 PCI_CFG_EXT_REG(reg); 687 if ((sc->cfg_handle != 0) && (sc->cfg_cur_offs == offs)) 688 return (0); 689 if (sc->cfg_handle != 0) 690 bus_space_unmap(sc->bus_tag, sc->cfg_handle, 0x800); 691 692 rv = bus_space_map(sc->bus_tag, offs, 0x800, 0, &sc->cfg_handle); 693 if (rv != 0) 694 device_printf(sc->dev, "Cannot map config space\n"); 695 else 696 sc->cfg_cur_offs = offs; 697 return (rv); 698} 699 700static uint32_t 701tegra_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func, 702 u_int reg, int bytes) 703{ 704 struct tegra_pcib_softc *sc; 705 bus_space_handle_t hndl; 706 uint32_t off; 707 uint32_t val; 708 int rv, i; 709 710 sc = device_get_softc(dev); 711 if (bus == 0) { 712 if (func != 0) 713 return (0xFFFFFFFF); 714 for (i = 0; i < TEGRA_PCIB_MAX_PORTS; i++) { 715 if ((sc->ports[i] != NULL) && 716 (sc->ports[i]->port_idx == slot)) { 717 hndl = sc->ports[i]->cfg_handle; 718 off = reg & 0xFFF; 719 break; 720 } 721 } 722 if (i >= TEGRA_PCIB_MAX_PORTS) 723 return (0xFFFFFFFF); 724 } else { 725 rv = tegra_pcbib_map_cfg(sc, bus, slot, func, reg); 726 if (rv != 0) 727 return (0xFFFFFFFF); 728 hndl = sc->cfg_handle; 729 off = PCI_CFG_BASE_REG(reg); 730 } 731 732 val = bus_space_read_4(sc->bus_tag, hndl, off & ~3); 733 switch (bytes) { 734 case 4: 735 break; 736 case 2: 737 if (off & 3) 738 val >>= 16; 739 val &= 0xffff; 740 break; 741 case 1: 742 val >>= ((off & 3) << 3); 743 val &= 0xff; 744 break; 745 } 746 return val; 747} 748 749static void 750tegra_pcib_write_config(device_t dev, u_int bus, u_int slot, u_int func, 751 u_int reg, uint32_t val, int bytes) 752{ 753 struct tegra_pcib_softc *sc; 754 bus_space_handle_t hndl; 755 uint32_t off; 756 uint32_t val2; 757 int rv, i; 758 759 sc = device_get_softc(dev); 760 if (bus == 0) { 761 if (func != 0) 762 return; 763 for (i = 0; i < TEGRA_PCIB_MAX_PORTS; i++) { 764 if ((sc->ports[i] != NULL) && 765 (sc->ports[i]->port_idx == slot)) { 766 hndl = sc->ports[i]->cfg_handle; 767 off = reg & 0xFFF; 768 break; 769 } 770 } 771 if (i >= TEGRA_PCIB_MAX_PORTS) 772 return; 773 } else { 774 rv = tegra_pcbib_map_cfg(sc, bus, slot, func, reg); 775 if (rv != 0) 776 return; 777 hndl = sc->cfg_handle; 778 off = PCI_CFG_BASE_REG(reg); 779 } 780 781 switch (bytes) { 782 case 4: 783 bus_space_write_4(sc->bus_tag, hndl, off, val); 784 break; 785 case 2: 786 val2 = bus_space_read_4(sc->bus_tag, hndl, off & ~3); 787 val2 &= ~(0xffff << ((off & 3) << 3)); 788 val2 |= ((val & 0xffff) << ((off & 3) << 3)); 789 bus_space_write_4(sc->bus_tag, hndl, off & ~3, val2); 790 break; 791 case 1: 792 val2 = bus_space_read_4(sc->bus_tag, hndl, off & ~3); 793 val2 &= ~(0xff << ((off & 3) << 3)); 794 val2 |= ((val & 0xff) << ((off & 3) << 3)); 795 bus_space_write_4(sc->bus_tag, hndl, off & ~3, val2); 796 break; 797 } 798} 799 800static int tegra_pci_intr(void *arg) 801{ 802 struct tegra_pcib_softc *sc = arg; 803 uint32_t code, signature; 804 805 code = bus_read_4(sc->afi_mem_res, AFI_INTR_CODE) & AFI_INTR_CODE_MASK; 806 signature = bus_read_4(sc->afi_mem_res, AFI_INTR_SIGNATURE); 807 bus_write_4(sc->afi_mem_res, AFI_INTR_CODE, 0); 808 if (code == AFI_INTR_CODE_INT_CODE_SM_MSG) 809 return(FILTER_STRAY); 810 811 printf("tegra_pci_intr: code %x sig %x\n", code, signature); 812 return (FILTER_HANDLED); 813} 814 815#if defined(TEGRA_PCI_MSI) 816static int 817tegra_pcib_map_msi(device_t dev, device_t child, int irq, uint64_t *addr, 818 uint32_t *data) 819{ 820 struct tegra_pcib_softc *sc; 821 822 sc = device_get_softc(dev); 823 irq = irq - MSI_IRQ; 824 825 /* validate parameters */ 826 if (isclr(&sc->msi_bitmap, irq)) { 827 device_printf(dev, "invalid MSI 0x%x\n", irq); 828 return (EINVAL); 829 } 830 831 tegra_msi_data(irq, addr, data); 832 833 debugf("%s: irq: %d addr: %jx data: %x\n", 834 __func__, irq, *addr, *data); 835 836 return (0); 837} 838 839static int 840tegra_pcib_alloc_msi(device_t dev, device_t child, int count, 841 int maxcount __unused, int *irqs) 842{ 843 struct tegra_pcib_softc *sc; 844 u_int start = 0, i; 845 846 if (powerof2(count) == 0 || count > MSI_IRQ_NUM) 847 return (EINVAL); 848 849 sc = device_get_softc(dev); 850 mtx_lock(&sc->mtx); 851 852 for (start = 0; (start + count) < MSI_IRQ_NUM; start++) { 853 for (i = start; i < start + count; i++) { 854 if (isset(&sc->msi_bitmap, i)) 855 break; 856 } 857 if (i == start + count) 858 break; 859 } 860 861 if ((start + count) == MSI_IRQ_NUM) { 862 mtx_unlock(&sc->mtx); 863 return (ENXIO); 864 } 865 866 for (i = start; i < start + count; i++) { 867 setbit(&sc->msi_bitmap, i); 868 irqs[i] = MSI_IRQ + i; 869 } 870 debugf("%s: start: %x count: %x\n", __func__, start, count); 871 872 mtx_unlock(&sc->mtx); 873 return (0); 874} 875 876static int 877tegra_pcib_release_msi(device_t dev, device_t child, int count, int *irqs) 878{ 879 struct tegra_pcib_softc *sc; 880 u_int i; 881 882 sc = device_get_softc(dev); 883 mtx_lock(&sc->mtx); 884 885 for (i = 0; i < count; i++) 886 clrbit(&sc->msi_bitmap, irqs[i] - MSI_IRQ); 887 888 mtx_unlock(&sc->mtx); 889 return (0); 890} 891#endif 892 893static bus_size_t 894tegra_pcib_pex_ctrl(struct tegra_pcib_softc *sc, int port) 895{ 896 if (port >= TEGRA_PCIB_MAX_PORTS) 897 panic("invalid port number: %d\n", port); 898 899 if (port == 0) 900 return (AFI_PEX0_CTRL); 901 else if (port == 1) 902 return (AFI_PEX1_CTRL); 903 else if (port == 2) 904 return (AFI_PEX2_CTRL); 905 else 906 panic("invalid port number: %d\n", port); 907} 908 909static int 910tegra_pcib_enable_fdt_resources(struct tegra_pcib_softc *sc) 911{ 912 int rv; 913 914 rv = hwreset_assert(sc->hwreset_pcie_x); 915 if (rv != 0) { 916 device_printf(sc->dev, "Cannot assert 'pcie_x' reset\n"); 917 return (rv); 918 } 919 rv = hwreset_assert(sc->hwreset_afi); 920 if (rv != 0) { 921 device_printf(sc->dev, "Cannot assert 'afi' reset\n"); 922 return (rv); 923 } 924 rv = hwreset_assert(sc->hwreset_pex); 925 if (rv != 0) { 926 device_printf(sc->dev, "Cannot assert 'pex' reset\n"); 927 return (rv); 928 } 929 930 tegra_powergate_power_off(TEGRA_POWERGATE_PCX); 931 932 /* Power supplies. */ 933 rv = regulator_enable(sc->supply_avddio_pex); 934 if (rv != 0) { 935 device_printf(sc->dev, 936 "Cannot enable 'avddio_pex' regulator\n"); 937 return (rv); 938 } 939 rv = regulator_enable(sc->supply_dvddio_pex); 940 if (rv != 0) { 941 device_printf(sc->dev, 942 "Cannot enable 'dvddio_pex' regulator\n"); 943 return (rv); 944 } 945 rv = regulator_enable(sc->supply_avdd_pex_pll); 946 if (rv != 0) { 947 device_printf(sc->dev, 948 "Cannot enable 'avdd-pex-pll' regulator\n"); 949 return (rv); 950 } 951 952 rv = regulator_enable(sc->supply_hvdd_pex); 953 if (rv != 0) { 954 device_printf(sc->dev, 955 "Cannot enable 'hvdd-pex-supply' regulator\n"); 956 return (rv); 957 } 958 rv = regulator_enable(sc->supply_hvdd_pex_pll_e); 959 if (rv != 0) { 960 device_printf(sc->dev, 961 "Cannot enable 'hvdd-pex-pll-e-supply' regulator\n"); 962 return (rv); 963 } 964 rv = regulator_enable(sc->supply_vddio_pex_ctl); 965 if (rv != 0) { 966 device_printf(sc->dev, 967 "Cannot enable 'vddio-pex-ctl' regulator\n"); 968 return (rv); 969 } 970 rv = regulator_enable(sc->supply_avdd_pll_erefe); 971 if (rv != 0) { 972 device_printf(sc->dev, 973 "Cannot enable 'avdd-pll-erefe-supply' regulator\n"); 974 return (rv); 975 } 976 977 rv = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_PCX, 978 sc->clk_pex, sc->hwreset_pex); 979 if (rv != 0) { 980 device_printf(sc->dev, "Cannot enable 'PCX' powergate\n"); 981 return (rv); 982 } 983 984 rv = hwreset_deassert(sc->hwreset_afi); 985 if (rv != 0) { 986 device_printf(sc->dev, "Cannot unreset 'afi' reset\n"); 987 return (rv); 988 } 989 990 rv = clk_enable(sc->clk_afi); 991 if (rv != 0) { 992 device_printf(sc->dev, "Cannot enable 'afi' clock\n"); 993 return (rv); 994 } 995 996 rv = clk_enable(sc->clk_cml); 997 if (rv != 0) { 998 device_printf(sc->dev, "Cannot enable 'cml' clock\n"); 999 return (rv); 1000 } 1001 1002 rv = clk_enable(sc->clk_pll_e); 1003 if (rv != 0) { 1004 device_printf(sc->dev, "Cannot enable 'pll_e' clock\n"); 1005 return (rv); 1006 } 1007 return (0); 1008} 1009 1010static struct tegra_pcib_port * 1011tegra_pcib_parse_port(struct tegra_pcib_softc *sc, phandle_t node) 1012{ 1013 struct tegra_pcib_port *port; 1014 uint32_t tmp[5]; 1015 char tmpstr[6]; 1016 int rv; 1017 1018 port = malloc(sizeof(struct tegra_pcib_port), M_DEVBUF, M_WAITOK); 1019 1020 rv = OF_getprop(node, "status", tmpstr, sizeof(tmpstr)); 1021 if (rv <= 0 || strcmp(tmpstr, "okay") == 0 || 1022 strcmp(tmpstr, "ok") == 0) 1023 port->enabled = 1; 1024 else 1025 port->enabled = 0; 1026 1027 rv = OF_getencprop(node, "assigned-addresses", tmp, sizeof(tmp)); 1028 if (rv != sizeof(tmp)) { 1029 device_printf(sc->dev, "Cannot parse assigned-address: %d\n", 1030 rv); 1031 goto fail; 1032 } 1033 port->rp_base_addr = tmp[2]; 1034 port->rp_size = tmp[4]; 1035 port->port_idx = OFW_PCI_PHYS_HI_DEVICE(tmp[0]) - 1; 1036 if (port->port_idx >= TEGRA_PCIB_MAX_PORTS) { 1037 device_printf(sc->dev, "Invalid port index: %d\n", 1038 port->port_idx); 1039 goto fail; 1040 } 1041 /* XXX - TODO: 1042 * Implement proper function for parsing pci "reg" property: 1043 * - it have PCI bus format 1044 * - its relative to matching "assigned-addresses" 1045 */ 1046 rv = OF_getencprop(node, "reg", tmp, sizeof(tmp)); 1047 if (rv != sizeof(tmp)) { 1048 device_printf(sc->dev, "Cannot parse reg: %d\n", rv); 1049 goto fail; 1050 } 1051 port->rp_base_addr += tmp[2]; 1052 1053 rv = OF_getencprop(node, "nvidia,num-lanes", &port->num_lanes, 1054 sizeof(port->num_lanes)); 1055 if (rv != sizeof(port->num_lanes)) { 1056 device_printf(sc->dev, "Cannot parse nvidia,num-lanes: %d\n", 1057 rv); 1058 goto fail; 1059 } 1060 if (port->num_lanes > 4) { 1061 device_printf(sc->dev, "Invalid nvidia,num-lanes: %d\n", 1062 port->num_lanes); 1063 goto fail; 1064 } 1065 1066 port->afi_pex_ctrl = tegra_pcib_pex_ctrl(sc, port->port_idx); 1067 sc->lanes_cfg |= port->num_lanes << (4 * port->port_idx); 1068 1069 return (port); 1070fail: 1071 free(port, M_DEVBUF); 1072 return (NULL); 1073} 1074 1075 1076static int 1077tegra_pcib_parse_fdt_resources(struct tegra_pcib_softc *sc, phandle_t node) 1078{ 1079 phandle_t child; 1080 struct tegra_pcib_port *port; 1081 int rv; 1082 1083 /* Power supplies. */ 1084 rv = regulator_get_by_ofw_property(sc->dev, 0, "avddio-pex-supply", 1085 &sc->supply_avddio_pex); 1086 if (rv != 0) { 1087 device_printf(sc->dev, 1088 "Cannot get 'avddio-pex' regulator\n"); 1089 return (ENXIO); 1090 } 1091 rv = regulator_get_by_ofw_property(sc->dev, 0, "dvddio-pex-supply", 1092 &sc->supply_dvddio_pex); 1093 if (rv != 0) { 1094 device_printf(sc->dev, 1095 "Cannot get 'dvddio-pex' regulator\n"); 1096 return (ENXIO); 1097 } 1098 rv = regulator_get_by_ofw_property(sc->dev, 0, "avdd-pex-pll-supply", 1099 &sc->supply_avdd_pex_pll); 1100 if (rv != 0) { 1101 device_printf(sc->dev, 1102 "Cannot get 'avdd-pex-pll' regulator\n"); 1103 return (ENXIO); 1104 } 1105 rv = regulator_get_by_ofw_property(sc->dev, 0, "hvdd-pex-supply", 1106 &sc->supply_hvdd_pex); 1107 if (rv != 0) { 1108 device_printf(sc->dev, 1109 "Cannot get 'hvdd-pex' regulator\n"); 1110 return (ENXIO); 1111 } 1112 rv = regulator_get_by_ofw_property(sc->dev, 0, "hvdd-pex-pll-e-supply", 1113 &sc->supply_hvdd_pex_pll_e); 1114 if (rv != 0) { 1115 device_printf(sc->dev, 1116 "Cannot get 'hvdd-pex-pll-e' regulator\n"); 1117 return (ENXIO); 1118 } 1119 rv = regulator_get_by_ofw_property(sc->dev, 0, "vddio-pex-ctl-supply", 1120 &sc->supply_vddio_pex_ctl); 1121 if (rv != 0) { 1122 device_printf(sc->dev, 1123 "Cannot get 'vddio-pex-ctl' regulator\n"); 1124 return (ENXIO); 1125 } 1126 rv = regulator_get_by_ofw_property(sc->dev, 0, "avdd-pll-erefe-supply", 1127 &sc->supply_avdd_pll_erefe); 1128 if (rv != 0) { 1129 device_printf(sc->dev, 1130 "Cannot get 'avdd-pll-erefe' regulator\n"); 1131 return (ENXIO); 1132 } 1133 1134 /* Resets. */ 1135 rv = hwreset_get_by_ofw_name(sc->dev, 0, "pex", &sc->hwreset_pex); 1136 if (rv != 0) { 1137 device_printf(sc->dev, "Cannot get 'pex' reset\n"); 1138 return (ENXIO); 1139 } 1140 rv = hwreset_get_by_ofw_name(sc->dev, 0, "afi", &sc->hwreset_afi); 1141 if (rv != 0) { 1142 device_printf(sc->dev, "Cannot get 'afi' reset\n"); 1143 return (ENXIO); 1144 } 1145 rv = hwreset_get_by_ofw_name(sc->dev, 0, "pcie_x", &sc->hwreset_pcie_x); 1146 if (rv != 0) { 1147 device_printf(sc->dev, "Cannot get 'pcie_x' reset\n"); 1148 return (ENXIO); 1149 } 1150 1151 /* Clocks. */ 1152 rv = clk_get_by_ofw_name(sc->dev, 0, "pex", &sc->clk_pex); 1153 if (rv != 0) { 1154 device_printf(sc->dev, "Cannot get 'pex' clock\n"); 1155 return (ENXIO); 1156 } 1157 rv = clk_get_by_ofw_name(sc->dev, 0, "afi", &sc->clk_afi); 1158 if (rv != 0) { 1159 device_printf(sc->dev, "Cannot get 'afi' clock\n"); 1160 return (ENXIO); 1161 } 1162 rv = clk_get_by_ofw_name(sc->dev, 0, "pll_e", &sc->clk_pll_e); 1163 if (rv != 0) { 1164 device_printf(sc->dev, "Cannot get 'pll_e' clock\n"); 1165 return (ENXIO); 1166 } 1167 rv = clk_get_by_ofw_name(sc->dev, 0, "cml", &sc->clk_cml); 1168 if (rv != 0) { 1169 device_printf(sc->dev, "Cannot get 'cml' clock\n"); 1170 return (ENXIO); 1171 } 1172 1173 /* Phy. */ 1174 rv = phy_get_by_ofw_name(sc->dev, 0, "pcie", &sc->phy); 1175 if (rv != 0) { 1176 device_printf(sc->dev, "Cannot get 'pcie' phy\n"); 1177 return (ENXIO); 1178 } 1179 1180 /* Ports */ 1181 sc->num_ports = 0; 1182 for (child = OF_child(node); child != 0; child = OF_peer(child)) { 1183 port = tegra_pcib_parse_port(sc, child); 1184 if (port == NULL) { 1185 device_printf(sc->dev, "Cannot parse PCIe port node\n"); 1186 return (ENXIO); 1187 } 1188 sc->ports[sc->num_ports++] = port; 1189 } 1190 1191 return (0); 1192} 1193 1194static int 1195tegra_pcib_decode_ranges(struct tegra_pcib_softc *sc, 1196 struct tegra_pci_range *ranges, int nranges) 1197{ 1198 int i; 1199 1200 for (i = 2; i < nranges; i++) { 1201 if (ranges[i].space_code == OFW_PCI_PHYS_HI_SPACE_IO) { 1202 if (sc->io_range.size != 0) { 1203 device_printf(sc->dev, 1204 "Duplicated IO range found in DT\n"); 1205 return (ENXIO); 1206 } 1207 sc->io_range = ranges[i]; 1208 } 1209 if ((ranges[i].space_code == OFW_PCI_PHYS_HI_SPACE_MEM32) && 1210 !ranges[i].prefetchable) { 1211 if (sc->mem_range.size != 0) { 1212 device_printf(sc->dev, 1213 "Duplicated memory range found in DT\n"); 1214 return (ENXIO); 1215 } 1216 sc->mem_range = ranges[i]; 1217 } 1218 if ((ranges[i].space_code == OFW_PCI_PHYS_HI_SPACE_MEM32) && 1219 ranges[i].prefetchable) { 1220 if (sc->pref_mem_range.size != 0) { 1221 device_printf(sc->dev, 1222 "Duplicated memory range found in DT\n"); 1223 return (ENXIO); 1224 } 1225 sc->pref_mem_range = ranges[i]; 1226 } 1227 } 1228 if ((sc->io_range.size == 0) || (sc->mem_range.size == 0) 1229 || (sc->pref_mem_range.size == 0)) { 1230 device_printf(sc->dev, 1231 " Not all required ranges are found in DT\n"); 1232 return (ENXIO); 1233 } 1234 return (0); 1235} 1236 1237/* 1238 * Hardware config. 1239 */ 1240static int 1241tegra_pcib_wait_for_link(struct tegra_pcib_softc *sc, 1242 struct tegra_pcib_port *port) 1243{ 1244 uint32_t reg; 1245 int i; 1246 1247 1248 /* Setup link detection. */ 1249 reg = tegra_pcib_read_config(sc->dev, 0, port->port_idx, 0, 1250 RP_PRIV_MISC, 4); 1251 reg &= ~RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT; 1252 reg |= RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT; 1253 tegra_pcib_write_config(sc->dev, 0, port->port_idx, 0, 1254 RP_PRIV_MISC, reg, 4); 1255 1256 for (i = TEGRA_PCIE_LINKUP_TIMEOUT; i > 0; i--) { 1257 reg = tegra_pcib_read_config(sc->dev, 0, port->port_idx, 0, 1258 RP_VEND_XP, 4); 1259 if (reg & RP_VEND_XP_DL_UP) 1260 break; 1261 DELAY(1); 1262 1263 } 1264 if (i <= 0) 1265 return (ETIMEDOUT); 1266 1267 for (i = TEGRA_PCIE_LINKUP_TIMEOUT; i > 0; i--) { 1268 reg = tegra_pcib_read_config(sc->dev, 0, port->port_idx, 0, 1269 RP_LINK_CONTROL_STATUS, 4); 1270 if (reg & RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE) 1271 break; 1272 1273 DELAY(1); 1274 } 1275 if (i <= 0) 1276 return (ETIMEDOUT); 1277 return (0); 1278} 1279 1280static void 1281tegra_pcib_port_enable(struct tegra_pcib_softc *sc, int port_num) 1282{ 1283 struct tegra_pcib_port *port; 1284 uint32_t reg; 1285 int rv; 1286 1287 port = sc->ports[port_num]; 1288 1289 /* Put port to reset. */ 1290 reg = AFI_RD4(sc, port->afi_pex_ctrl); 1291 reg &= ~AFI_PEX_CTRL_RST_L; 1292 AFI_WR4(sc, port->afi_pex_ctrl, reg); 1293 AFI_RD4(sc, port->afi_pex_ctrl); 1294 DELAY(10); 1295 1296 /* Enable clocks. */ 1297 reg |= AFI_PEX_CTRL_REFCLK_EN; 1298 reg |= AFI_PEX_CTRL_CLKREQ_EN; 1299 reg |= AFI_PEX_CTRL_OVERRIDE_EN; 1300 AFI_WR4(sc, port->afi_pex_ctrl, reg); 1301 AFI_RD4(sc, port->afi_pex_ctrl); 1302 DELAY(100); 1303 1304 /* Release reset. */ 1305 reg |= AFI_PEX_CTRL_RST_L; 1306 AFI_WR4(sc, port->afi_pex_ctrl, reg); 1307 1308 rv = tegra_pcib_wait_for_link(sc, port); 1309 if (bootverbose) 1310 device_printf(sc->dev, " port %d (%d lane%s): Link is %s\n", 1311 port->port_idx, port->num_lanes, 1312 port->num_lanes > 1 ? "s": "", 1313 rv == 0 ? "up": "down"); 1314} 1315 1316 1317static void 1318tegra_pcib_port_disable(struct tegra_pcib_softc *sc, uint32_t port_num) 1319{ 1320 struct tegra_pcib_port *port; 1321 uint32_t reg; 1322 1323 port = sc->ports[port_num]; 1324 1325 /* Put port to reset. */ 1326 reg = AFI_RD4(sc, port->afi_pex_ctrl); 1327 reg &= ~AFI_PEX_CTRL_RST_L; 1328 AFI_WR4(sc, port->afi_pex_ctrl, reg); 1329 AFI_RD4(sc, port->afi_pex_ctrl); 1330 DELAY(10); 1331 1332 /* Disable clocks. */ 1333 reg &= ~AFI_PEX_CTRL_CLKREQ_EN; 1334 reg &= ~AFI_PEX_CTRL_REFCLK_EN; 1335 AFI_WR4(sc, port->afi_pex_ctrl, reg); 1336 1337 if (bootverbose) 1338 device_printf(sc->dev, " port %d (%d lane%s): Disabled\n", 1339 port->port_idx, port->num_lanes, 1340 port->num_lanes > 1 ? "s": ""); 1341} 1342 1343static void 1344tegra_pcib_set_bar(struct tegra_pcib_softc *sc, int bar, uint32_t axi, 1345 uint64_t fpci, uint32_t size, int is_memory) 1346{ 1347 uint32_t fpci_reg; 1348 uint32_t axi_reg; 1349 uint32_t size_reg; 1350 1351 axi_reg = axi & ~0xFFF; 1352 size_reg = size >> 12; 1353 fpci_reg = (uint32_t)(fpci >> 8) & ~0xF; 1354 fpci_reg |= is_memory ? 0x1 : 0x0; 1355 AFI_WR4(sc, bars[bar].axi_start, axi_reg); 1356 AFI_WR4(sc, bars[bar].size, size_reg); 1357 AFI_WR4(sc, bars[bar].fpci_start, fpci_reg); 1358} 1359 1360static int 1361tegra_pcib_enable(struct tegra_pcib_softc *sc, uint32_t port) 1362{ 1363 int rv; 1364 int i; 1365 uint32_t reg; 1366 1367 rv = tegra_pcib_enable_fdt_resources(sc); 1368 if (rv != 0) { 1369 device_printf(sc->dev, "Cannot enable FDT resources\n"); 1370 return (rv); 1371 } 1372 /* Enable PLLE control. */ 1373 reg = AFI_RD4(sc, AFI_PLLE_CONTROL); 1374 reg &= ~AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL; 1375 reg |= AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN; 1376 AFI_WR4(sc, AFI_PLLE_CONTROL, reg); 1377 1378 /* Set bias pad. */ 1379 AFI_WR4(sc, AFI_PEXBIAS_CTRL, 0); 1380 1381 /* Configure mode and ports. */ 1382 reg = AFI_RD4(sc, AFI_PCIE_CONFIG); 1383 reg &= ~AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK; 1384 if (sc->lanes_cfg == 0x14) { 1385 if (bootverbose) 1386 device_printf(sc->dev, 1387 "Using x1,x4 configuration\n"); 1388 reg |= AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_XBAR4_1; 1389 } else if (sc->lanes_cfg == 0x12) { 1390 if (bootverbose) 1391 device_printf(sc->dev, 1392 "Using x1,x2 configuration\n"); 1393 reg |= AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_XBAR2_1; 1394 } else { 1395 device_printf(sc->dev, 1396 "Unsupported lanes configuration: 0x%X\n", sc->lanes_cfg); 1397 } 1398 reg |= AFI_PCIE_CONFIG_PCIE_DISABLE_ALL; 1399 for (i = 0; i < TEGRA_PCIB_MAX_PORTS; i++) { 1400 if ((sc->ports[i] != NULL)) 1401 reg &= 1402 ~AFI_PCIE_CONFIG_PCIE_DISABLE(sc->ports[i]->port_idx); 1403 } 1404 AFI_WR4(sc, AFI_PCIE_CONFIG, reg); 1405 1406 /* Enable Gen2 support. */ 1407 reg = AFI_RD4(sc, AFI_FUSE); 1408 reg &= ~AFI_FUSE_PCIE_T0_GEN2_DIS; 1409 AFI_WR4(sc, AFI_FUSE, reg); 1410 1411 /* Enable PCIe phy. */ 1412 rv = phy_enable(sc->dev, sc->phy); 1413 if (rv != 0) { 1414 device_printf(sc->dev, "Cannot enable phy\n"); 1415 return (rv); 1416 } 1417 1418 rv = hwreset_deassert(sc->hwreset_pcie_x); 1419 if (rv != 0) { 1420 device_printf(sc->dev, "Cannot unreset 'pci_x' reset\n"); 1421 return (rv); 1422 } 1423 1424 /* Enable config space. */ 1425 reg = AFI_RD4(sc, AFI_CONFIGURATION); 1426 reg |= AFI_CONFIGURATION_EN_FPCI; 1427 AFI_WR4(sc, AFI_CONFIGURATION, reg); 1428 1429 /* Enable AFI errors. */ 1430 reg = 0; 1431 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_INI_SLVERR); 1432 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_INI_DECERR); 1433 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_TGT_SLVERR); 1434 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_TGT_DECERR); 1435 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_TGT_WRERR); 1436 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_SM_MSG); 1437 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_DFPCI_DECERR); 1438 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_AXI_DECERR); 1439 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_FPCI_TIMEOUT); 1440 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_PE_PRSNT_SENSE); 1441 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_PE_CLKREQ_SENSE); 1442 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_CLKCLAMP_SENSE); 1443 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_RDY4PD_SENSE); 1444 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_P2P_ERROR); 1445 AFI_WR4(sc, AFI_AFI_INTR_ENABLE, reg); 1446 AFI_WR4(sc, AFI_SM_INTR_ENABLE, 0xffffffff); 1447 1448 /* Enable INT, disable MSI. */ 1449 AFI_WR4(sc, AFI_INTR_MASK, AFI_INTR_MASK_INT_MASK); 1450 1451 /* Mask all FPCI errors. */ 1452 AFI_WR4(sc, AFI_FPCI_ERROR_MASKS, 0); 1453 1454 /* Setup AFI translation windows. */ 1455 /* BAR 0 - type 1 extended configuration. */ 1456 tegra_pcib_set_bar(sc, 0, rman_get_start(sc->cfg_mem_res), 1457 FPCI_MAP_EXT_TYPE1_CONFIG, rman_get_size(sc->cfg_mem_res), 0); 1458 1459 /* BAR 1 - downstream I/O. */ 1460 tegra_pcib_set_bar(sc, 1, sc->io_range.host_addr, FPCI_MAP_IO, 1461 sc->io_range.size, 0); 1462 1463 /* BAR 2 - downstream prefetchable memory 1:1. */ 1464 tegra_pcib_set_bar(sc, 2, sc->pref_mem_range.host_addr, 1465 sc->pref_mem_range.host_addr, sc->pref_mem_range.size, 1); 1466 1467 /* BAR 3 - downstream not prefetchable memory 1:1 .*/ 1468 tegra_pcib_set_bar(sc, 3, sc->mem_range.host_addr, 1469 sc->mem_range.host_addr, sc->mem_range.size, 1); 1470 1471 /* BAR 3-8 clear. */ 1472 tegra_pcib_set_bar(sc, 4, 0, 0, 0, 0); 1473 tegra_pcib_set_bar(sc, 5, 0, 0, 0, 0); 1474 tegra_pcib_set_bar(sc, 6, 0, 0, 0, 0); 1475 tegra_pcib_set_bar(sc, 7, 0, 0, 0, 0); 1476 tegra_pcib_set_bar(sc, 8, 0, 0, 0, 0); 1477 1478 /* MSI BAR - clear. */ 1479 tegra_pcib_set_bar(sc, 9, 0, 0, 0, 0); 1480 return(0); 1481} 1482 1483static int 1484tegra_pcib_probe(device_t dev) 1485{ 1486 if (!ofw_bus_status_okay(dev)) 1487 return (ENXIO); 1488 1489 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data != 0) { 1490 device_set_desc(dev, "Nvidia Integrated PCI/PCI-E Controller"); 1491 return (BUS_PROBE_DEFAULT); 1492 } 1493 return (ENXIO); 1494} 1495 1496static int 1497tegra_pcib_attach(device_t dev) 1498{ 1499 struct tegra_pcib_softc *sc; 1500 phandle_t node; 1501 uint32_t unit; 1502 int rv; 1503 int rid; 1504 int nranges; 1505 struct tegra_pci_range *ranges; 1506 struct tegra_pcib_port *port; 1507 int i; 1508 1509 sc = device_get_softc(dev); 1510 sc->dev = dev; 1511 unit = fdt_get_unit(dev); 1512 mtx_init(&sc->mtx, "msi_mtx", NULL, MTX_DEF); 1513 1514 1515 node = ofw_bus_get_node(dev); 1516 1517 rv = tegra_pcib_parse_fdt_resources(sc, node); 1518 if (rv != 0) { 1519 device_printf(dev, "Cannot get FDT resources\n"); 1520 return (rv); 1521 } 1522 1523 nranges = tegra_pci_get_ranges(node, &ranges); 1524 if (nranges != 5) { 1525 device_printf(sc->dev, "Unexpected number of ranges: %d\n", 1526 nranges); 1527 rv = ENXIO; 1528 goto out; 1529 } 1530 1531 /* Allocate bus_space resources. */ 1532 rid = 0; 1533 sc->pads_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1534 RF_ACTIVE); 1535 if (sc->pads_mem_res == NULL) { 1536 device_printf(dev, "Cannot allocate PADS register\n"); 1537 rv = ENXIO; 1538 goto out; 1539 } 1540 /* 1541 * XXX - FIXME 1542 * tag for config space is not filled when RF_ALLOCATED flag is used. 1543 */ 1544 sc->bus_tag = rman_get_bustag(sc->pads_mem_res); 1545 1546 rid = 1; 1547 sc->afi_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1548 RF_ACTIVE); 1549 if (sc->afi_mem_res == NULL) { 1550 device_printf(dev, "Cannot allocate AFI register\n"); 1551 rv = ENXIO; 1552 goto out; 1553 } 1554 1555 rid = 2; 1556 sc->cfg_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1557 RF_ALLOCATED); 1558 if (sc->cfg_mem_res == NULL) { 1559 device_printf(dev, "Cannot allocate config space memory\n"); 1560 rv = ENXIO; 1561 goto out; 1562 } 1563 sc->cfg_base_addr = rman_get_start(sc->cfg_mem_res); 1564 1565 1566 /* Map RP slots */ 1567 for (i = 0; i < TEGRA_PCIB_MAX_PORTS; i++) { 1568 if (sc->ports[i] == NULL) 1569 continue; 1570 port = sc->ports[i]; 1571 rv = bus_space_map(sc->bus_tag, port->rp_base_addr, 1572 port->rp_size, 0, &port->cfg_handle); 1573 if (rv != 0) { 1574 device_printf(sc->dev, "Cannot allocate memory for " 1575 "port: %d\n", i); 1576 rv = ENXIO; 1577 goto out; 1578 } 1579 } 1580 1581 /* 1582 * Get PCI interrupt info. 1583 */ 1584 ofw_bus_setup_iinfo(node, &sc->pci_iinfo, sizeof(pcell_t)); 1585 rid = 0; 1586 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1587 RF_ACTIVE | RF_SHAREABLE); 1588 if (sc->irq_res == NULL) { 1589 device_printf(dev, "Cannot allocate IRQ resources\n"); 1590 rv = ENXIO; 1591 goto out; 1592 } 1593 1594 rid = 1; 1595 sc->msi_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1596 RF_ACTIVE); 1597 if (sc->irq_res == NULL) { 1598 device_printf(dev, "Cannot allocate MSI IRQ resources\n"); 1599 rv = ENXIO; 1600 goto out; 1601 } 1602 1603 if (bus_setup_intr(dev, sc->irq_res, INTR_TYPE_BIO | INTR_MPSAFE, 1604 tegra_pci_intr, NULL, sc, &sc->intr_cookie)) { 1605 device_printf(dev, "cannot setup interrupt handler\n"); 1606 rv = ENXIO; 1607 goto out; 1608 } 1609 1610 /* Memory management. */ 1611 rv = tegra_pcib_decode_ranges(sc, ranges, nranges); 1612 if (rv != 0) 1613 goto out; 1614 1615 rv = tegra_pcib_rman_init(sc); 1616 if (rv != 0) 1617 goto out; 1618 free(ranges, M_DEVBUF); 1619 ranges = NULL; 1620 1621 /* 1622 * Enable PCIE device. 1623 */ 1624 rv = tegra_pcib_enable(sc, unit); 1625 if (rv != 0) 1626 goto out; 1627 for (i = 0; i < TEGRA_PCIB_MAX_PORTS; i++) { 1628 if (sc->ports[i] == NULL) 1629 continue; 1630 if (sc->ports[i]->enabled) 1631 tegra_pcib_port_enable(sc, i); 1632 else 1633 tegra_pcib_port_disable(sc, i); 1634 } 1635 1636 device_add_child(dev, "pci", -1); 1637 1638 return (bus_generic_attach(dev)); 1639 1640out: 1641 if (ranges != NULL) 1642 free(ranges, M_DEVBUF); 1643 1644 return (rv); 1645} 1646 1647 1648static device_method_t tegra_pcib_methods[] = { 1649 /* Device interface */ 1650 DEVMETHOD(device_probe, tegra_pcib_probe), 1651 DEVMETHOD(device_attach, tegra_pcib_attach), 1652 1653 /* Bus interface */ 1654 DEVMETHOD(bus_read_ivar, tegra_pcib_read_ivar), 1655 DEVMETHOD(bus_write_ivar, tegra_pcib_write_ivar), 1656 DEVMETHOD(bus_alloc_resource, tegra_pcib_alloc_resource), 1657 DEVMETHOD(bus_adjust_resource, tegra_pcib_adjust_resource), 1658 DEVMETHOD(bus_release_resource, tegra_pcib_release_resource), 1659 DEVMETHOD(bus_activate_resource, tegra_pcib_pcie_activate_resource), 1660 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 1661 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 1662 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 1663 1664 /* pcib interface */ 1665 DEVMETHOD(pcib_maxslots, tegra_pcib_maxslots), 1666 DEVMETHOD(pcib_read_config, tegra_pcib_read_config), 1667 DEVMETHOD(pcib_write_config, tegra_pcib_write_config), 1668 DEVMETHOD(pcib_route_interrupt, tegra_pcib_route_interrupt), 1669 1670#if defined(TEGRA_PCI_MSI) 1671 DEVMETHOD(pcib_alloc_msi, tegra_pcib_alloc_msi), 1672 DEVMETHOD(pcib_release_msi, tegra_pcib_release_msi), 1673 DEVMETHOD(pcib_map_msi, tegra_pcib_map_msi), 1674#endif 1675 1676 /* OFW bus interface */ 1677 DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat), 1678 DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model), 1679 DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name), 1680 DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node), 1681 DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type), 1682 1683 DEVMETHOD_END 1684}; 1685 1686static driver_t tegra_pcib_driver = { 1687 "pcib", 1688 tegra_pcib_methods, 1689 sizeof(struct tegra_pcib_softc), 1690}; 1691 1692devclass_t pcib_devclass; 1693 1694DRIVER_MODULE(pcib, simplebus, tegra_pcib_driver, pcib_devclass, 0, 0); 1695