tegra_i2c.c revision 308324
1/*- 2 * Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD: stable/11/sys/arm/nvidia/tegra_i2c.c 308324 2016-11-05 04:17:32Z mmel $"); 29 30/* 31 * I2C driver for Tegra SoCs. 32 */ 33#include <sys/param.h> 34#include <sys/systm.h> 35#include <sys/bus.h> 36#include <sys/kernel.h> 37#include <sys/limits.h> 38#include <sys/module.h> 39#include <sys/resource.h> 40 41#include <machine/bus.h> 42#include <machine/resource.h> 43#include <sys/rman.h> 44 45#include <sys/lock.h> 46#include <sys/mutex.h> 47 48#include <dev/extres/clk/clk.h> 49#include <dev/extres/hwreset/hwreset.h> 50#include <dev/fdt/fdt_common.h> 51#include <dev/iicbus/iiconf.h> 52#include <dev/iicbus/iicbus.h> 53#include <dev/ofw/ofw_bus.h> 54#include <dev/ofw/ofw_bus_subr.h> 55 56#include "iicbus_if.h" 57 58#define I2C_CNFG 0x000 59#define I2C_CNFG_MSTR_CLR_BUS_ON_TIMEOUT (1 << 15) 60#define I2C_CNFG_DEBOUNCE_CNT(x) (((x) & 0x07) << 12) 61#define I2C_CNFG_NEW_MASTER_FSM (1 << 11) 62#define I2C_CNFG_PACKET_MODE_EN (1 << 10) 63#define I2C_CNFG_SEND (1 << 9) 64#define I2C_CNFG_NOACK (1 << 8) 65#define I2C_CNFG_CMD2 (1 << 7) 66#define I2C_CNFG_CMD1 (1 << 6) 67#define I2C_CNFG_START (1 << 5) 68#define I2C_CNFG_SLV2 (1 << 4) 69#define I2C_CNFG_LENGTH_SHIFT 1 70#define I2C_CNFG_LENGTH_MASK 0x7 71#define I2C_CNFG_A_MOD (1 << 0) 72 73#define I2C_CMD_ADDR0 0x004 74#define I2C_CMD_ADDR1 0x008 75#define I2C_CMD_DATA1 0x00c 76#define I2C_CMD_DATA2 0x010 77#define I2C_STATUS 0x01c 78#define I2C_SL_CNFG 0x020 79#define I2C_SL_RCVD 0x024 80#define I2C_SL_STATUS 0x028 81#define I2C_SL_ADDR1 0x02c 82#define I2C_SL_ADDR2 0x030 83#define I2C_TLOW_SEXT 0x034 84#define I2C_SL_DELAY_COUNT 0x03c 85#define I2C_SL_INT_MASK 0x040 86#define I2C_SL_INT_SOURCE 0x044 87#define I2C_SL_INT_SET 0x048 88#define I2C_TX_PACKET_FIFO 0x050 89#define I2C_RX_FIFO 0x054 90#define I2C_PACKET_TRANSFER_STATUS 0x058 91#define I2C_FIFO_CONTROL 0x05c 92#define I2C_FIFO_CONTROL_SLV_TX_FIFO_TRIG(x) (((x) & 0x07) << 13) 93#define I2C_FIFO_CONTROL_SLV_RX_FIFO_TRIG(x) (((x) & 0x07) << 10) 94#define I2C_FIFO_CONTROL_SLV_TX_FIFO_FLUSH (1 << 9) 95#define I2C_FIFO_CONTROL_SLV_RX_FIFO_FLUSH (1 << 8) 96#define I2C_FIFO_CONTROL_TX_FIFO_TRIG(x) (((x) & 0x07) << 5) 97#define I2C_FIFO_CONTROL_RX_FIFO_TRIG(x) (((x) & 0x07) << 2) 98#define I2C_FIFO_CONTROL_TX_FIFO_FLUSH (1 << 1) 99#define I2C_FIFO_CONTROL_RX_FIFO_FLUSH (1 << 0) 100 101#define I2C_FIFO_STATUS 0x060 102#define I2C_FIFO_STATUS_SLV_XFER_ERR_REASON (1 << 25) 103#define I2C_FIFO_STATUS_TX_FIFO_SLV_EMPTY_CNT(x) (((x) >> 20) & 0xF) 104#define I2C_FIFO_STATUS_RX_FIFO_SLV_FULL_CNT(x) (((x) >> 16) & 0xF) 105#define I2C_FIFO_STATUS_TX_FIFO_EMPTY_CNT(x) (((x) >> 4) & 0xF) 106#define I2C_FIFO_STATUS_RX_FIFO_FULL_CNT(x) (((x) >> 0) & 0xF) 107 108#define I2C_INTERRUPT_MASK_REGISTER 0x064 109#define I2C_INTERRUPT_STATUS_REGISTER 0x068 110#define I2C_INT_SLV_ACK_WITHHELD (1 << 28) 111#define I2C_INT_SLV_RD2WR (1 << 27) 112#define I2C_INT_SLV_WR2RD (1 << 26) 113#define I2C_INT_SLV_PKT_XFER_ERR (1 << 25) 114#define I2C_INT_SLV_TX_BUFFER_REQ (1 << 24) 115#define I2C_INT_SLV_RX_BUFFER_FILLED (1 << 23) 116#define I2C_INT_SLV_PACKET_XFER_COMPLETE (1 << 22) 117#define I2C_INT_SLV_TFIFO_OVF (1 << 21) 118#define I2C_INT_SLV_RFIFO_UNF (1 << 20) 119#define I2C_INT_SLV_TFIFO_DATA_REQ (1 << 17) 120#define I2C_INT_SLV_RFIFO_DATA_REQ (1 << 16) 121#define I2C_INT_BUS_CLEAR_DONE (1 << 11) 122#define I2C_INT_TLOW_MEXT_TIMEOUT (1 << 10) 123#define I2C_INT_TLOW_SEXT_TIMEOUT (1 << 9) 124#define I2C_INT_TIMEOUT (1 << 8) 125#define I2C_INT_PACKET_XFER_COMPLETE (1 << 7) 126#define I2C_INT_ALL_PACKETS_XFER_COMPLETE (1 << 6) 127#define I2C_INT_TFIFO_OVR (1 << 5) 128#define I2C_INT_RFIFO_UNF (1 << 4) 129#define I2C_INT_NOACK (1 << 3) 130#define I2C_INT_ARB_LOST (1 << 2) 131#define I2C_INT_TFIFO_DATA_REQ (1 << 1) 132#define I2C_INT_RFIFO_DATA_REQ (1 << 0) 133#define I2C_ERROR_MASK (I2C_INT_ARB_LOST | I2C_INT_NOACK | \ 134 I2C_INT_RFIFO_UNF | I2C_INT_TFIFO_OVR) 135 136#define I2C_CLK_DIVISOR 0x06c 137#define I2C_CLK_DIVISOR_STD_FAST_MODE_SHIFT 16 138#define I2C_CLK_DIVISOR_STD_FAST_MODE_MASK 0xffff 139#define I2C_CLK_DIVISOR_HSMODE_SHIFT 0 140#define I2C_CLK_DIVISOR_HSMODE_MASK 0xffff 141#define I2C_INTERRUPT_SOURCE_REGISTER 0x070 142#define I2C_INTERRUPT_SET_REGISTER 0x074 143#define I2C_SLV_TX_PACKET_FIFO 0x07c 144#define I2C_SLV_PACKET_STATUS 0x080 145#define I2C_BUS_CLEAR_CONFIG 0x084 146#define I2C_BUS_CLEAR_CONFIG_BC_SCLK_THRESHOLD(x) (((x) & 0xFF) << 16) 147#define I2C_BUS_CLEAR_CONFIG_BC_STOP_COND (1 << 2) 148#define I2C_BUS_CLEAR_CONFIG_BC_TERMINATE (1 << 1) 149#define I2C_BUS_CLEAR_CONFIG_BC_ENABLE (1 << 0) 150 151#define I2C_BUS_CLEAR_STATUS 0x088 152#define I2C_BUS_CLEAR_STATUS_BC_STATUS (1 << 0) 153 154#define I2C_CONFIG_LOAD 0x08c 155#define I2C_CONFIG_LOAD_TIMEOUT_CONFIG_LOAD (1 << 2) 156#define I2C_CONFIG_LOAD_SLV_CONFIG_LOAD (1 << 1) 157#define I2C_CONFIG_LOAD_MSTR_CONFIG_LOAD (1 << 0) 158 159#define I2C_INTERFACE_TIMING_0 0x094 160#define I2C_INTERFACE_TIMING_1 0x098 161#define I2C_HS_INTERFACE_TIMING_0 0x09c 162#define I2C_HS_INTERFACE_TIMING_1 0x0a0 163 164/* Protocol header 0 */ 165#define PACKET_HEADER0_HEADER_SIZE_SHIFT 28 166#define PACKET_HEADER0_HEADER_SIZE_MASK 0x3 167#define PACKET_HEADER0_PACKET_ID_SHIFT 16 168#define PACKET_HEADER0_PACKET_ID_MASK 0xff 169#define PACKET_HEADER0_CONT_ID_SHIFT 12 170#define PACKET_HEADER0_CONT_ID_MASK 0xf 171#define PACKET_HEADER0_PROTOCOL_I2C (1 << 4) 172#define PACKET_HEADER0_TYPE_SHIFT 0 173#define PACKET_HEADER0_TYPE_MASK 0x7 174 175/* I2C header */ 176#define I2C_HEADER_HIGHSPEED_MODE (1 << 22) 177#define I2C_HEADER_CONT_ON_NAK (1 << 21) 178#define I2C_HEADER_SEND_START_BYTE (1 << 20) 179#define I2C_HEADER_READ (1 << 19) 180#define I2C_HEADER_10BIT_ADDR (1 << 18) 181#define I2C_HEADER_IE_ENABLE (1 << 17) 182#define I2C_HEADER_REPEAT_START (1 << 16) 183#define I2C_HEADER_CONTINUE_XFER (1 << 15) 184#define I2C_HEADER_MASTER_ADDR_SHIFT 12 185#define I2C_HEADER_MASTER_ADDR_MASK 0x7 186#define I2C_HEADER_SLAVE_ADDR_SHIFT 0 187#define I2C_HEADER_SLAVE_ADDR_MASK 0x3ff 188 189#define I2C_CLK_DIVISOR_STD_FAST_MODE 0x19 190#define I2C_CLK_MULTIPLIER_STD_FAST_MODE 8 191 192#define I2C_REQUEST_TIMEOUT (5 * hz) 193 194#define WR4(_sc, _r, _v) bus_write_4((_sc)->mem_res, (_r), (_v)) 195#define RD4(_sc, _r) bus_read_4((_sc)->mem_res, (_r)) 196 197#define LOCK(_sc) mtx_lock(&(_sc)->mtx) 198#define UNLOCK(_sc) mtx_unlock(&(_sc)->mtx) 199#define SLEEP(_sc, timeout) \ 200 mtx_sleep(sc, &sc->mtx, 0, "i2cbuswait", timeout); 201#define LOCK_INIT(_sc) \ 202 mtx_init(&_sc->mtx, device_get_nameunit(_sc->dev), "tegra_i2c", MTX_DEF) 203#define LOCK_DESTROY(_sc) mtx_destroy(&_sc->mtx) 204#define ASSERT_LOCKED(_sc) mtx_assert(&_sc->mtx, MA_OWNED) 205#define ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->mtx, MA_NOTOWNED) 206 207static struct ofw_compat_data compat_data[] = { 208 {"nvidia,tegra124-i2c", 1}, 209 {NULL, 0} 210}; 211enum tegra_i2c_xfer_type { 212 XFER_STOP, /* Send stop condition after xfer */ 213 XFER_REPEAT_START, /* Send repeated start after xfer */ 214 XFER_CONTINUE /* Don't send nothing */ 215} ; 216 217struct tegra_i2c_softc { 218 device_t dev; 219 struct mtx mtx; 220 221 struct resource *mem_res; 222 struct resource *irq_res; 223 void *irq_h; 224 225 device_t iicbus; 226 clk_t clk; 227 hwreset_t reset; 228 uint32_t core_freq; 229 uint32_t bus_freq; 230 int bus_inuse; 231 232 struct iic_msg *msg; 233 int msg_idx; 234 uint32_t bus_err; 235 int done; 236}; 237 238static int 239tegra_i2c_flush_fifo(struct tegra_i2c_softc *sc) 240{ 241 int timeout; 242 uint32_t reg; 243 244 reg = RD4(sc, I2C_FIFO_CONTROL); 245 reg |= I2C_FIFO_CONTROL_TX_FIFO_FLUSH | I2C_FIFO_CONTROL_RX_FIFO_FLUSH; 246 WR4(sc, I2C_FIFO_CONTROL, reg); 247 248 timeout = 10; 249 while (timeout > 0) { 250 reg = RD4(sc, I2C_FIFO_CONTROL); 251 reg &= I2C_FIFO_CONTROL_TX_FIFO_FLUSH | 252 I2C_FIFO_CONTROL_RX_FIFO_FLUSH; 253 if (reg == 0) 254 break; 255 DELAY(10); 256 } 257 if (timeout <= 0) { 258 device_printf(sc->dev, "FIFO flush timedout\n"); 259 return (ETIMEDOUT); 260 } 261 return (0); 262} 263 264static void 265tegra_i2c_setup_clk(struct tegra_i2c_softc *sc, int clk_freq) 266{ 267 int div; 268 269 div = ((sc->core_freq / clk_freq) / 10) - 1; 270 if ((sc->core_freq / (10 * (div + 1))) > clk_freq) 271 div++; 272 if (div > 65535) 273 div = 65535; 274 WR4(sc, I2C_CLK_DIVISOR, 275 (1 << I2C_CLK_DIVISOR_HSMODE_SHIFT) | 276 (div << I2C_CLK_DIVISOR_STD_FAST_MODE_SHIFT)); 277} 278 279static void 280tegra_i2c_bus_clear(struct tegra_i2c_softc *sc) 281{ 282 int timeout; 283 uint32_t reg, status; 284 285 WR4(sc, I2C_BUS_CLEAR_CONFIG, 286 I2C_BUS_CLEAR_CONFIG_BC_SCLK_THRESHOLD(18) | 287 I2C_BUS_CLEAR_CONFIG_BC_STOP_COND | 288 I2C_BUS_CLEAR_CONFIG_BC_TERMINATE); 289 290 WR4(sc, I2C_CONFIG_LOAD, I2C_CONFIG_LOAD_MSTR_CONFIG_LOAD); 291 for (timeout = 1000; timeout > 0; timeout--) { 292 if (RD4(sc, I2C_CONFIG_LOAD) == 0) 293 break; 294 DELAY(10); 295 } 296 if (timeout <= 0) 297 device_printf(sc->dev, "config load timeouted\n"); 298 reg = RD4(sc, I2C_BUS_CLEAR_CONFIG); 299 reg |= I2C_BUS_CLEAR_CONFIG_BC_ENABLE; 300 WR4(sc, I2C_BUS_CLEAR_CONFIG,reg); 301 302 for (timeout = 1000; timeout > 0; timeout--) { 303 if ((RD4(sc, I2C_BUS_CLEAR_CONFIG) & 304 I2C_BUS_CLEAR_CONFIG_BC_ENABLE) == 0) 305 break; 306 DELAY(10); 307 } 308 if (timeout <= 0) 309 device_printf(sc->dev, "bus clear timeouted\n"); 310 311 status = RD4(sc, I2C_BUS_CLEAR_STATUS); 312 if ((status & I2C_BUS_CLEAR_STATUS_BC_STATUS) == 0) 313 device_printf(sc->dev, "bus clear failed\n"); 314} 315 316static int 317tegra_i2c_hw_init(struct tegra_i2c_softc *sc) 318{ 319 int rv, timeout; 320 321 /* Reset the core. */ 322 rv = hwreset_assert(sc->reset); 323 if (rv != 0) { 324 device_printf(sc->dev, "Cannot assert reset\n"); 325 return (rv); 326 } 327 DELAY(10); 328 rv = hwreset_deassert(sc->reset); 329 if (rv != 0) { 330 device_printf(sc->dev, "Cannot clear reset\n"); 331 return (rv); 332 } 333 334 WR4(sc, I2C_INTERRUPT_MASK_REGISTER, 0); 335 WR4(sc, I2C_INTERRUPT_STATUS_REGISTER, 0xFFFFFFFF); 336 WR4(sc, I2C_CNFG, I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN | 337 I2C_CNFG_DEBOUNCE_CNT(2)); 338 339 tegra_i2c_setup_clk(sc, sc->bus_freq); 340 341 WR4(sc, I2C_FIFO_CONTROL, I2C_FIFO_CONTROL_TX_FIFO_TRIG(7) | 342 I2C_FIFO_CONTROL_RX_FIFO_TRIG(0)); 343 344 WR4(sc, I2C_CONFIG_LOAD, I2C_CONFIG_LOAD_MSTR_CONFIG_LOAD); 345 for (timeout = 1000; timeout > 0; timeout--) { 346 if (RD4(sc, I2C_CONFIG_LOAD) == 0) 347 break; 348 DELAY(10); 349 } 350 if (timeout <= 0) 351 device_printf(sc->dev, "config load timeouted\n"); 352 353 tegra_i2c_bus_clear(sc); 354 return (0); 355} 356 357static int 358tegra_i2c_tx(struct tegra_i2c_softc *sc) 359{ 360 uint32_t reg; 361 int cnt, i; 362 363 if (sc->msg_idx >= sc->msg->len) 364 panic("Invalid call to tegra_i2c_tx\n"); 365 366 while(sc->msg_idx < sc->msg->len) { 367 reg = RD4(sc, I2C_FIFO_STATUS); 368 if (I2C_FIFO_STATUS_TX_FIFO_EMPTY_CNT(reg) == 0) 369 break; 370 cnt = min(4, sc->msg->len - sc->msg_idx); 371 reg = 0; 372 for (i = 0; i < cnt; i++) { 373 reg |= sc->msg->buf[sc->msg_idx] << (i * 8); 374 sc->msg_idx++; 375 } 376 WR4(sc, I2C_TX_PACKET_FIFO, reg); 377 } 378 if (sc->msg_idx >= sc->msg->len) 379 return (0); 380 return (sc->msg->len - sc->msg_idx - 1); 381} 382 383static int 384tegra_i2c_rx(struct tegra_i2c_softc *sc) 385{ 386 uint32_t reg; 387 int cnt, i; 388 389 if (sc->msg_idx >= sc->msg->len) 390 panic("Invalid call to tegra_i2c_rx\n"); 391 392 while(sc->msg_idx < sc->msg->len) { 393 reg = RD4(sc, I2C_FIFO_STATUS); 394 if (I2C_FIFO_STATUS_RX_FIFO_FULL_CNT(reg) == 0) 395 break; 396 cnt = min(4, sc->msg->len - sc->msg_idx); 397 reg = RD4(sc, I2C_RX_FIFO); 398 for (i = 0; i < cnt; i++) { 399 sc->msg->buf[sc->msg_idx] = (reg >> (i * 8)) & 0xFF; 400 sc->msg_idx++; 401 } 402 } 403 404 if (sc->msg_idx >= sc->msg->len) 405 return (0); 406 return (sc->msg->len - sc->msg_idx - 1); 407} 408 409static void 410tegra_i2c_intr(void *arg) 411{ 412 struct tegra_i2c_softc *sc; 413 uint32_t status, reg; 414 int rv; 415 416 sc = (struct tegra_i2c_softc *)arg; 417 418 LOCK(sc); 419 status = RD4(sc, I2C_INTERRUPT_SOURCE_REGISTER); 420 if (sc->msg == NULL) { 421 /* Unexpected interrupt - disable FIFOs, clear reset. */ 422 reg = RD4(sc, I2C_INTERRUPT_MASK_REGISTER); 423 reg &= ~I2C_INT_TFIFO_DATA_REQ; 424 reg &= ~I2C_INT_RFIFO_DATA_REQ; 425 WR4(sc, I2C_INTERRUPT_MASK_REGISTER, 0); 426 WR4(sc, I2C_INTERRUPT_STATUS_REGISTER, status); 427 UNLOCK(sc); 428 return; 429 } 430 431 if ((status & I2C_ERROR_MASK) != 0) { 432 if (status & I2C_INT_NOACK) 433 sc->bus_err = IIC_ENOACK; 434 if (status & I2C_INT_ARB_LOST) 435 sc->bus_err = IIC_EBUSERR; 436 if ((status & I2C_INT_TFIFO_OVR) || 437 (status & I2C_INT_RFIFO_UNF)) 438 sc->bus_err = IIC_EBUSERR; 439 sc->done = 1; 440 } else if ((status & I2C_INT_RFIFO_DATA_REQ) && 441 (sc->msg != NULL) && (sc->msg->flags & IIC_M_RD)) { 442 rv = tegra_i2c_rx(sc); 443 if (rv == 0) { 444 reg = RD4(sc, I2C_INTERRUPT_MASK_REGISTER); 445 reg &= ~I2C_INT_RFIFO_DATA_REQ; 446 WR4(sc, I2C_INTERRUPT_MASK_REGISTER, reg); 447 } 448 } else if ((status & I2C_INT_TFIFO_DATA_REQ) && 449 (sc->msg != NULL) && !(sc->msg->flags & IIC_M_RD)) { 450 rv = tegra_i2c_tx(sc); 451 if (rv == 0) { 452 reg = RD4(sc, I2C_INTERRUPT_MASK_REGISTER); 453 reg &= ~I2C_INT_TFIFO_DATA_REQ; 454 WR4(sc, I2C_INTERRUPT_MASK_REGISTER, reg); 455 } 456 } else if ((status & I2C_INT_RFIFO_DATA_REQ) || 457 (status & I2C_INT_TFIFO_DATA_REQ)) { 458 device_printf(sc->dev, "Unexpected data interrupt: 0x%08X\n", 459 status); 460 reg = RD4(sc, I2C_INTERRUPT_MASK_REGISTER); 461 reg &= ~I2C_INT_TFIFO_DATA_REQ; 462 reg &= ~I2C_INT_RFIFO_DATA_REQ; 463 WR4(sc, I2C_INTERRUPT_MASK_REGISTER, reg); 464 } 465 if (status & I2C_INT_PACKET_XFER_COMPLETE) 466 sc->done = 1; 467 WR4(sc, I2C_INTERRUPT_STATUS_REGISTER, status); 468 if (sc->done) { 469 WR4(sc, I2C_INTERRUPT_MASK_REGISTER, 0); 470 wakeup(&(sc->done)); 471 } 472 UNLOCK(sc); 473} 474 475static void 476tegra_i2c_start_msg(struct tegra_i2c_softc *sc, struct iic_msg *msg, 477 enum tegra_i2c_xfer_type xtype) 478{ 479 uint32_t tmp, mask; 480 481 /* Packet header. */ 482 tmp = (0 << PACKET_HEADER0_HEADER_SIZE_SHIFT) | 483 PACKET_HEADER0_PROTOCOL_I2C | 484 (1 << PACKET_HEADER0_CONT_ID_SHIFT) | 485 (1 << PACKET_HEADER0_PACKET_ID_SHIFT); 486 WR4(sc, I2C_TX_PACKET_FIFO, tmp); 487 488 489 /* Packet size. */ 490 WR4(sc, I2C_TX_PACKET_FIFO, msg->len - 1); 491 492 /* I2C header. */ 493 tmp = I2C_HEADER_IE_ENABLE; 494 if (xtype == XFER_CONTINUE) 495 tmp |= I2C_HEADER_CONTINUE_XFER; 496 else if (xtype == XFER_REPEAT_START) 497 tmp |= I2C_HEADER_REPEAT_START; 498 tmp |= msg->slave << I2C_HEADER_SLAVE_ADDR_SHIFT; 499 if (msg->flags & IIC_M_RD) { 500 tmp |= I2C_HEADER_READ; 501 tmp |= 1 << I2C_HEADER_SLAVE_ADDR_SHIFT; 502 } else 503 tmp &= ~(1 << I2C_HEADER_SLAVE_ADDR_SHIFT); 504 505 WR4(sc, I2C_TX_PACKET_FIFO, tmp); 506 507 /* Interrupt mask. */ 508 mask = I2C_INT_NOACK | I2C_INT_ARB_LOST | I2C_INT_PACKET_XFER_COMPLETE; 509 if (msg->flags & IIC_M_RD) 510 mask |= I2C_INT_RFIFO_DATA_REQ; 511 else 512 mask |= I2C_INT_TFIFO_DATA_REQ; 513 WR4(sc, I2C_INTERRUPT_MASK_REGISTER, mask); 514} 515 516static int 517tegra_i2c_poll(struct tegra_i2c_softc *sc) 518{ 519 int timeout; 520 521 for(timeout = 10000; timeout > 0; timeout--) { 522 UNLOCK(sc); 523 tegra_i2c_intr(sc); 524 LOCK(sc); 525 if (sc->done != 0) 526 break; 527 DELAY(1); 528 } 529 if (timeout <= 0) 530 return (ETIMEDOUT); 531 return (0); 532} 533 534static int 535tegra_i2c_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs) 536{ 537 int rv, i; 538 struct tegra_i2c_softc *sc; 539 enum tegra_i2c_xfer_type xtype; 540 541 sc = device_get_softc(dev); 542 LOCK(sc); 543 544 /* Get the bus. */ 545 while (sc->bus_inuse == 1) 546 SLEEP(sc, 0); 547 sc->bus_inuse = 1; 548 549 rv = 0; 550 for (i = 0; i < nmsgs; i++) { 551 sc->msg = &msgs[i]; 552 sc->msg_idx = 0; 553 sc->bus_err = 0; 554 sc->done = 0; 555 /* Check for valid parameters. */ 556 if (sc->msg == NULL || sc->msg->buf == NULL || 557 sc->msg->len == 0) { 558 rv = EINVAL; 559 break; 560 } 561 562 /* Get flags for next transfer. */ 563 if (i == (nmsgs - 1)) { 564 if (msgs[i].flags & IIC_M_NOSTOP) 565 xtype = XFER_CONTINUE; 566 else 567 xtype = XFER_STOP; 568 } else { 569 if (msgs[i + 1].flags & IIC_M_NOSTART) 570 xtype = XFER_CONTINUE; 571 else 572 xtype = XFER_REPEAT_START; 573 } 574 tegra_i2c_start_msg(sc, sc->msg, xtype); 575 if (cold) 576 rv = tegra_i2c_poll(sc); 577 else 578 rv = msleep(&sc->done, &sc->mtx, PZERO, "iic", 579 I2C_REQUEST_TIMEOUT); 580 581 WR4(sc, I2C_INTERRUPT_MASK_REGISTER, 0); 582 WR4(sc, I2C_INTERRUPT_STATUS_REGISTER, 0xFFFFFFFF); 583 if (rv == 0) 584 rv = sc->bus_err; 585 if (rv != 0) 586 break; 587 } 588 589 if (rv != 0) { 590 tegra_i2c_hw_init(sc); 591 tegra_i2c_flush_fifo(sc); 592 } 593 594 sc->msg = NULL; 595 sc->msg_idx = 0; 596 sc->bus_err = 0; 597 sc->done = 0; 598 599 /* Wake up the processes that are waiting for the bus. */ 600 sc->bus_inuse = 0; 601 wakeup(sc); 602 UNLOCK(sc); 603 604 return (rv); 605} 606 607static int 608tegra_i2c_iicbus_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr) 609{ 610 struct tegra_i2c_softc *sc; 611 int busfreq; 612 613 sc = device_get_softc(dev); 614 busfreq = IICBUS_GET_FREQUENCY(sc->iicbus, speed); 615 sc = device_get_softc(dev); 616 LOCK(sc); 617 tegra_i2c_setup_clk(sc, busfreq); 618 UNLOCK(sc); 619 return (0); 620} 621 622static int 623tegra_i2c_probe(device_t dev) 624{ 625 if (!ofw_bus_status_okay(dev)) 626 return (ENXIO); 627 628 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 629 return (ENXIO); 630 631 return (BUS_PROBE_DEFAULT); 632} 633 634static int 635tegra_i2c_attach(device_t dev) 636{ 637 int rv, rid; 638 phandle_t node; 639 struct tegra_i2c_softc *sc; 640 uint64_t freq; 641 642 sc = device_get_softc(dev); 643 sc->dev = dev; 644 node = ofw_bus_get_node(dev); 645 646 LOCK_INIT(sc); 647 648 /* Get the memory resource for the register mapping. */ 649 rid = 0; 650 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 651 RF_ACTIVE); 652 if (sc->mem_res == NULL) { 653 device_printf(dev, "Cannot map registers.\n"); 654 rv = ENXIO; 655 goto fail; 656 } 657 658 /* Allocate our IRQ resource. */ 659 rid = 0; 660 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 661 RF_ACTIVE); 662 if (sc->irq_res == NULL) { 663 device_printf(dev, "Cannot allocate interrupt.\n"); 664 rv = ENXIO; 665 goto fail; 666 } 667 668 /* FDT resources. */ 669 rv = clk_get_by_ofw_name(dev, 0, "div-clk", &sc->clk); 670 if (rv != 0) { 671 device_printf(dev, "Cannot get i2c clock: %d\n", rv); 672 goto fail; 673 } 674 rv = hwreset_get_by_ofw_name(sc->dev, 0, "i2c", &sc->reset); 675 if (rv != 0) { 676 device_printf(sc->dev, "Cannot get i2c reset\n"); 677 return (ENXIO); 678 } 679 rv = OF_getencprop(node, "clock-frequency", &sc->bus_freq, 680 sizeof(sc->bus_freq)); 681 if (rv != sizeof(sc->bus_freq)) { 682 sc->bus_freq = 100000; 683 goto fail; 684 } 685 686 /* Request maximum frequency for I2C block 136MHz (408MHz / 3). */ 687 rv = clk_set_freq(sc->clk, 136000000, CLK_SET_ROUND_DOWN); 688 if (rv != 0) { 689 device_printf(dev, "Cannot set clock frequency\n"); 690 goto fail; 691 } 692 rv = clk_get_freq(sc->clk, &freq); 693 if (rv != 0) { 694 device_printf(dev, "Cannot get clock frequency\n"); 695 goto fail; 696 } 697 sc->core_freq = (uint32_t)freq; 698 699 rv = clk_enable(sc->clk); 700 if (rv != 0) { 701 device_printf(dev, "Cannot enable clock: %d\n", rv); 702 goto fail; 703 } 704 705 /* Init hardware. */ 706 rv = tegra_i2c_hw_init(sc); 707 if (rv) { 708 device_printf(dev, "tegra_i2c_activate failed\n"); 709 goto fail; 710 } 711 712 /* Setup interrupt. */ 713 rv = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 714 NULL, tegra_i2c_intr, sc, &sc->irq_h); 715 if (rv) { 716 device_printf(dev, "Cannot setup interrupt.\n"); 717 goto fail; 718 } 719 720 /* Attach the iicbus. */ 721 sc->iicbus = device_add_child(dev, "iicbus", -1); 722 if (sc->iicbus == NULL) { 723 device_printf(dev, "Could not allocate iicbus instance.\n"); 724 rv = ENXIO; 725 goto fail; 726 } 727 728 /* Probe and attach the iicbus. */ 729 return (bus_generic_attach(dev)); 730 731fail: 732 if (sc->irq_h != NULL) 733 bus_teardown_intr(dev, sc->irq_res, sc->irq_h); 734 if (sc->irq_res != NULL) 735 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq_res); 736 if (sc->mem_res != NULL) 737 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res); 738 LOCK_DESTROY(sc); 739 740 return (rv); 741} 742 743static int 744tegra_i2c_detach(device_t dev) 745{ 746 struct tegra_i2c_softc *sc; 747 int rv; 748 749 sc = device_get_softc(dev); 750 tegra_i2c_hw_init(sc); 751 if (sc->irq_h != NULL) 752 bus_teardown_intr(dev, sc->irq_res, sc->irq_h); 753 if (sc->irq_res != NULL) 754 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq_res); 755 if (sc->mem_res != NULL) 756 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res); 757 758 LOCK_DESTROY(sc); 759 if (sc->iicbus) 760 rv = device_delete_child(dev, sc->iicbus); 761 return (bus_generic_detach(dev)); 762} 763 764static phandle_t 765tegra_i2c_get_node(device_t bus, device_t dev) 766{ 767 768 /* Share controller node with iibus device. */ 769 return (ofw_bus_get_node(bus)); 770} 771 772static device_method_t tegra_i2c_methods[] = { 773 /* Device interface */ 774 DEVMETHOD(device_probe, tegra_i2c_probe), 775 DEVMETHOD(device_attach, tegra_i2c_attach), 776 DEVMETHOD(device_detach, tegra_i2c_detach), 777 778 /* Bus interface */ 779 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 780 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 781 DEVMETHOD(bus_alloc_resource, bus_generic_alloc_resource), 782 DEVMETHOD(bus_release_resource, bus_generic_release_resource), 783 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 784 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 785 DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource), 786 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 787 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 788 789 /* OFW methods */ 790 DEVMETHOD(ofw_bus_get_node, tegra_i2c_get_node), 791 792 /* iicbus interface */ 793 DEVMETHOD(iicbus_callback, iicbus_null_callback), 794 DEVMETHOD(iicbus_reset, tegra_i2c_iicbus_reset), 795 DEVMETHOD(iicbus_transfer, tegra_i2c_transfer), 796 797 DEVMETHOD_END 798}; 799 800DEFINE_CLASS_0(iichb, tegra_i2c_driver, tegra_i2c_methods, 801 sizeof(struct tegra_i2c_softc)); 802static devclass_t tegra_i2c_devclass; 803EARLY_DRIVER_MODULE(tegra_iic, simplebus, tegra_i2c_driver, tegra_i2c_devclass, 804 0, 0, 73); 805extern devclass_t ofwiicbus_devclass; 806extern driver_t ofw_iicbus_driver; 807EARLY_DRIVER_MODULE(ofw_iicbus, tegra_iic, ofw_iicbus_driver, 808 ofwiicbus_devclass, 0, 0, BUS_PASS_BUS); 809