tegra124_car.c revision 317013
1145247Sdamien/*- 2156321Sdamien * Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org> 3145247Sdamien * All rights reserved. 4145247Sdamien * 5145247Sdamien * Redistribution and use in source and binary forms, with or without 6145247Sdamien * modification, are permitted provided that the following conditions 7145247Sdamien * are met: 8145247Sdamien * 1. Redistributions of source code must retain the above copyright 9145247Sdamien * notice, this list of conditions and the following disclaimer. 10145247Sdamien * 2. Redistributions in binary form must reproduce the above copyright 11145247Sdamien * notice, this list of conditions and the following disclaimer in the 12145247Sdamien * documentation and/or other materials provided with the distribution. 13145247Sdamien * 14145247Sdamien * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15145247Sdamien * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16145247Sdamien * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17145247Sdamien * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18145247Sdamien * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19145247Sdamien * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20145247Sdamien * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21145247Sdamien * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22156321Sdamien * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23145247Sdamien * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24145247Sdamien * SUCH DAMAGE. 25145247Sdamien */ 26264952Smarius 27264952Smarius#include <sys/cdefs.h> 28145247Sdamien__FBSDID("$FreeBSD: stable/11/sys/arm/nvidia/tegra124/tegra124_car.c 317013 2017-04-16 08:21:14Z mmel $"); 29264952Smarius 30145247Sdamien#include <sys/param.h> 31145247Sdamien#include <sys/systm.h> 32264952Smarius#include <sys/bus.h> 33264952Smarius#include <sys/kernel.h> 34264952Smarius#include <sys/kobj.h> 35145247Sdamien#include <sys/module.h> 36145247Sdamien#include <sys/malloc.h> 37145247Sdamien#include <sys/rman.h> 38145247Sdamien#include <sys/lock.h> 39264952Smarius#include <sys/mutex.h> 40145247Sdamien 41145247Sdamien#include <machine/bus.h> 42264952Smarius#include <machine/cpu.h> 43145247Sdamien 44145247Sdamien#include <dev/extres/clk/clk_div.h> 45145247Sdamien#include <dev/extres/clk/clk_fixed.h> 46145247Sdamien#include <dev/extres/clk/clk_gate.h> 47145247Sdamien#include <dev/extres/clk/clk_mux.h> 48145247Sdamien#include <dev/extres/hwreset/hwreset.h> 49145247Sdamien#include <dev/ofw/openfirm.h> 50156327Ssilby#include <dev/ofw/ofw_bus.h> 51156327Ssilby#include <dev/ofw/ofw_bus_subr.h> 52235233Sbschmidt 53145247Sdamien#include <gnu/dts/include/dt-bindings/clock/tegra124-car.h> 54145247Sdamien 55178354Ssam#include "clkdev_if.h" 56145247Sdamien#include "hwreset_if.h" 57178354Ssam#include "tegra124_car.h" 58145247Sdamien 59264952Smariusstatic struct ofw_compat_data compat_data[] = { 60264952Smarius {"nvidia,tegra124-car", 1}, 61264952Smarius {NULL, 0}, 62145247Sdamien}; 63145247Sdamien 64145247Sdamien#define PLIST(x) static const char *x[] 65145247Sdamien 66145247Sdamien/* Pure multiplexer. */ 67145247Sdamien#define MUX(_id, cname, plists, o, s, w) \ 68145247Sdamien{ \ 69235233Sbschmidt .clkdef.id = _id, \ 70235233Sbschmidt .clkdef.name = cname, \ 71235233Sbschmidt .clkdef.parent_names = plists, \ 72235233Sbschmidt .clkdef.parent_cnt = nitems(plists), \ 73235233Sbschmidt .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ 74235233Sbschmidt .offset = o, \ 75235233Sbschmidt .shift = s, \ 76235233Sbschmidt .width = w, \ 77235233Sbschmidt} 78235233Sbschmidt 79156321Sdamien/* Fractional divider (7.1). */ 80156321Sdamien#define DIV7_1(_id, cname, plist, o, s) \ 81156321Sdamien{ \ 82156321Sdamien .clkdef.id = _id, \ 83235233Sbschmidt .clkdef.name = cname, \ 84235233Sbschmidt .clkdef.parent_names = (const char *[]){plist}, \ 85235233Sbschmidt .clkdef.parent_cnt = 1, \ 86235233Sbschmidt .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ 87235233Sbschmidt .offset = o, \ 88235233Sbschmidt .i_shift = (s) + 1, \ 89235233Sbschmidt .i_width = 7, \ 90235233Sbschmidt .f_shift = s, \ 91235233Sbschmidt .f_width = 1, \ 92235233Sbschmidt} 93235233Sbschmidt 94235233Sbschmidt/* Integer divider. */ 95235233Sbschmidt#define DIV(_id, cname, plist, o, s, w, f) \ 96279157Skevlo{ \ 97279157Skevlo .clkdef.id = _id, \ 98235233Sbschmidt .clkdef.name = cname, \ 99279157Skevlo .clkdef.parent_names = (const char *[]){plist}, \ 100235233Sbschmidt .clkdef.parent_cnt = 1, \ 101235233Sbschmidt .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ 102235233Sbschmidt .offset = o, \ 103145247Sdamien .i_shift = s, \ 104145247Sdamien .i_width = w, \ 105145247Sdamien .div_flags = f, \ 106264952Smarius} 107156321Sdamien 108156321Sdamien/* Gate in PLL block. */ 109156321Sdamien#define GATE_PLL(_id, cname, plist, o, s) \ 110156321Sdamien{ \ 111156321Sdamien .clkdef.id = _id, \ 112156321Sdamien .clkdef.name = cname, \ 113156321Sdamien .clkdef.parent_names = (const char *[]){plist}, \ 114156321Sdamien .clkdef.parent_cnt = 1, \ 115156321Sdamien .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ 116156321Sdamien .offset = o, \ 117170530Ssam .shift = s, \ 118170530Ssam .mask = 3, \ 119156321Sdamien .on_value = 3, \ 120156321Sdamien .off_value = 0, \ 121156321Sdamien} 122156321Sdamien 123156321Sdamien/* Standard gate. */ 124156321Sdamien#define GATE(_id, cname, plist, o, s) \ 125156321Sdamien{ \ 126156321Sdamien .clkdef.id = _id, \ 127156321Sdamien .clkdef.name = cname, \ 128156321Sdamien .clkdef.parent_names = (const char *[]){plist}, \ 129235233Sbschmidt .clkdef.parent_cnt = 1, \ 130235233Sbschmidt .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ 131235233Sbschmidt .offset = o, \ 132235233Sbschmidt .shift = s, \ 133235233Sbschmidt .mask = 1, \ 134235233Sbschmidt .on_value = 1, \ 135235233Sbschmidt .off_value = 0, \ 136156321Sdamien} 137156321Sdamien 138156321Sdamien/* Inverted gate. */ 139156321Sdamien#define GATE_INV(_id, cname, plist, o, s) \ 140156321Sdamien{ \ 141156321Sdamien .clkdef.id = _id, \ 142235233Sbschmidt .clkdef.name = cname, \ 143156321Sdamien .clkdef.parent_names = (const char *[]){plist}, \ 144156321Sdamien .clkdef.parent_cnt = 1, \ 145264952Smarius .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ 146156321Sdamien .offset = o, \ 147156321Sdamien .shift = s, \ 148156321Sdamien .mask = 1, \ 149156321Sdamien .on_value = 0, \ 150156321Sdamien .off_value = 1, \ 151145247Sdamien} 152145247Sdamien 153156321Sdamien/* Fixed rate clock. */ 154156321Sdamien#define FRATE(_id, cname, _freq) \ 155145247Sdamien{ \ 156145247Sdamien .clkdef.id = _id, \ 157145247Sdamien .clkdef.name = cname, \ 158145247Sdamien .clkdef.parent_names = NULL, \ 159145247Sdamien .clkdef.parent_cnt = 0, \ 160145247Sdamien .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ 161145247Sdamien .freq = _freq, \ 162156321Sdamien} 163156321Sdamien 164145247Sdamien/* Fixed rate multipier/divider. */ 165145247Sdamien#define FACT(_id, cname, pname, _mult, _div) \ 166145247Sdamien{ \ 167264952Smarius .clkdef.id = _id, \ 168145247Sdamien .clkdef.name = cname, \ 169145247Sdamien .clkdef.parent_names = (const char *[]){pname}, \ 170145247Sdamien .clkdef.parent_cnt = 1, \ 171145247Sdamien .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ 172145247Sdamien .mult = _mult, \ 173156321Sdamien .div = _div, \ 174145247Sdamien} 175145247Sdamien 176156321Sdamienstatic uint32_t osc_freqs[16] = { 177156321Sdamien [0] = 13000000, 178264952Smarius [1] = 16800000, 179145247Sdamien [4] = 19200000, 180145247Sdamien [5] = 38400000, 181145247Sdamien [8] = 12000000, 182145247Sdamien [9] = 48000000, 183145247Sdamien [12] = 260000000, 184145247Sdamien}; 185145247Sdamien 186145247Sdamien 187145247Sdamien/* Parent lists. */ 188145247SdamienPLIST(mux_pll_srcs) = {"osc_div_clk", NULL, "pllP_out0", NULL}; /* FIXME */ 189264952SmariusPLIST(mux_plle_src1) = {"osc_div_clk", "pllP_out0"}; 190145247SdamienPLIST(mux_plle_src) = {"pllE_src1", "pllREFE_out"}; 191145247SdamienPLIST(mux_plld_out0_plld2_out0) = {"pllD_out0", "pllD2_out0"}; 192145247SdamienPLIST(mux_xusb_hs) = {"xusb_ss_div2", "pllU_60"}; 193145247SdamienPLIST(mux_xusb_ss) = {"pc_xusb_ss", "osc_div_clk"}; 194145247Sdamien 195145247Sdamien 196145247Sdamien/* Clocks ajusted online. */ 197145247Sdamienstatic struct clk_fixed_def fixed_clk_m = 198156321Sdamien FRATE(TEGRA124_CLK_CLK_M, "clk_m", 12000000); 199156321Sdamienstatic struct clk_fixed_def fixed_osc_div_clk = 200264952Smarius FACT(0, "osc_div_clk", "clk_m", 1, 1); 201145247Sdamien 202145247Sdamienstatic struct clk_fixed_def tegra124_fixed_clks[] = { 203145247Sdamien /* Core clocks. */ 204235233Sbschmidt FRATE(0, "clk_s", 32768), 205235233Sbschmidt FACT(0, "clk_m_div2", "clk_m", 1, 2), 206235233Sbschmidt FACT(0, "clk_m_div4", "clk_m", 1, 3), 207235233Sbschmidt FACT(0, "pllU_60", "pllU_out", 1, 8), 208235233Sbschmidt FACT(0, "pllU_48", "pllU_out", 1, 10), 209235233Sbschmidt FACT(0, "pllU_12", "pllU_out", 1, 40), 210235233Sbschmidt FACT(TEGRA124_CLK_PLL_D_OUT0, "pllD_out0", "pllD_out", 1, 2), 211235233Sbschmidt FACT(TEGRA124_CLK_PLL_D2_OUT0, "pllD2_out0", "pllD2_out", 1, 1), 212235233Sbschmidt FACT(0, "pllX_out0", "pllX_out", 1, 2), 213235233Sbschmidt FACT(0, "pllC_UD", "pllC_out0", 1, 1), 214235233Sbschmidt FACT(0, "pllM_UD", "pllM_out0", 1, 1), 215235233Sbschmidt 216235233Sbschmidt /* Audio clocks. */ 217156321Sdamien FRATE(0, "audio0", 10000000), 218264952Smarius FRATE(0, "audio1", 10000000), 219264952Smarius FRATE(0, "audio2", 10000000), 220156321Sdamien FRATE(0, "audio3", 10000000), 221156321Sdamien FRATE(0, "audio4", 10000000), 222156321Sdamien FRATE(0, "ext_vimclk", 10000000), 223156321Sdamien 224156321Sdamien /* XUSB */ 225156321Sdamien FACT(TEGRA124_CLK_XUSB_SS_DIV2, "xusb_ss_div2", "xusb_ss", 1, 2), 226156321Sdamien 227156321Sdamien}; 228170530Ssam 229170530Ssam 230264952Smariusstatic struct clk_mux_def tegra124_mux_clks[] = { 231264952Smarius /* Core clocks. */ 232264952Smarius MUX(0, "pllD2_src", mux_pll_srcs, PLLD2_BASE, 25, 2), 233264952Smarius MUX(0, "pllDP_src", mux_pll_srcs, PLLDP_BASE, 25, 2), 234264952Smarius MUX(0, "pllC4_src", mux_pll_srcs, PLLC4_BASE, 25, 2), 235264952Smarius MUX(0, "pllE_src1", mux_plle_src1, PLLE_AUX, 2, 1), 236264952Smarius MUX(0, "pllE_src", mux_plle_src, PLLE_AUX, 28, 1), 237264952Smarius 238156321Sdamien /* Base peripheral clocks. */ 239156321Sdamien MUX(0, "dsia_mux", mux_plld_out0_plld2_out0, PLLD_BASE, 25, 1), 240264952Smarius MUX(0, "dsib_mux", mux_plld_out0_plld2_out0, PLLD2_BASE, 25, 1), 241264952Smarius 242264952Smarius /* USB. */ 243156321Sdamien MUX(TEGRA124_CLK_XUSB_HS_SRC, "xusb_hs", mux_xusb_hs, CLK_SOURCE_XUSB_SS, 25, 1), 244156321Sdamien MUX(0, "xusb_ss_mux", mux_xusb_ss, CLK_SOURCE_XUSB_SS, 24, 1), 245156321Sdamien 246156321Sdamien}; 247264952Smarius 248264952Smarius 249145247Sdamienstatic struct clk_gate_def tegra124_gate_clks[] = { 250264952Smarius /* Core clocks. */ 251145247Sdamien GATE_PLL(0, "pllC_out1", "pllC_out1_div", PLLC_OUT, 0), 252156321Sdamien GATE_PLL(0, "pllM_out1", "pllM_out1_div", PLLM_OUT, 0), 253156321Sdamien GATE_PLL(TEGRA124_CLK_PLL_U_480M, "pllU_480", "pllU_out", PLLU_BASE, 22), 254156321Sdamien GATE_PLL(0, "pllP_outX0", "pllP_outX0_div", PLLP_RESHIFT, 0), 255156321Sdamien GATE_PLL(0, "pllP_out1", "pllP_out1_div", PLLP_OUTA, 0), 256166901Spiso GATE_PLL(0, "pllP_out2", "pllP_out2_div", PLLP_OUTA, 16), 257156321Sdamien GATE_PLL(0, "pllP_out3", "pllP_out3_div", PLLP_OUTB, 0), 258156321Sdamien GATE_PLL(0, "pllP_out4", "pllP_out4_div", PLLP_OUTB, 16), 259264952Smarius GATE_PLL(0, "pllP_out5", "pllP_out5_div", PLLP_OUTC, 16), 260156321Sdamien GATE_PLL(0, "pllA_out0", "pllA_out1_div", PLLA_OUT, 0), 261156321Sdamien 262170530Ssam /* Base peripheral clocks. */ 263170530Ssam GATE(TEGRA124_CLK_CML0, "cml0", "pllE_out0", PLLE_AUX, 0), 264156321Sdamien GATE(TEGRA124_CLK_CML1, "cml1", "pllE_out0", PLLE_AUX, 1), 265145247Sdamien GATE_INV(TEGRA124_CLK_HCLK, "hclk", "hclk_div", CLK_SYSTEM_RATE, 7), 266145247Sdamien GATE_INV(TEGRA124_CLK_PCLK, "pclk", "pclk_div", CLK_SYSTEM_RATE, 3), 267145247Sdamien}; 268156321Sdamien 269156321Sdamienstatic struct clk_div_def tegra124_div_clks[] = { 270156321Sdamien /* Core clocks. */ 271170530Ssam DIV7_1(0, "pllC_out1_div", "pllC_out0", PLLC_OUT, 2), 272170530Ssam DIV7_1(0, "pllM_out1_div", "pllM_out0", PLLM_OUT, 8), 273170530Ssam DIV7_1(0, "pllP_outX0_div", "pllP_out0", PLLP_RESHIFT, 2), 274170530Ssam DIV7_1(0, "pllP_out1_div", "pllP_out0", PLLP_OUTA, 8), 275264952Smarius DIV7_1(0, "pllP_out2_div", "pllP_out0", PLLP_OUTA, 24), 276264952Smarius DIV7_1(0, "pllP_out3_div", "pllP_out0", PLLP_OUTB, 8), 277264952Smarius DIV7_1(0, "pllP_out4_div", "pllP_out0", PLLP_OUTB, 24), 278156321Sdamien DIV7_1(0, "pllP_out5_div", "pllP_out0", PLLP_OUTC, 24), 279156321Sdamien DIV7_1(0, "pllA_out1_div", "pllA_out", PLLA_OUT, 8), 280156321Sdamien 281264952Smarius /* Base peripheral clocks. */ 282264952Smarius DIV(0, "hclk_div", "sclk", CLK_SYSTEM_RATE, 4, 2, 0), 283264952Smarius DIV(0, "pclk_div", "hclk", CLK_SYSTEM_RATE, 0, 2, 0), 284156321Sdamien}; 285264952Smarius 286264952Smarius/* Initial setup table. */ 287156321Sdamienstatic struct tegra124_init_item clk_init_table[] = { 288156321Sdamien /* clock, partent, frequency, enable */ 289156321Sdamien {"uarta", "pllP_out0", 408000000, 0}, 290156321Sdamien {"uartb", "pllP_out0", 408000000, 0}, 291156321Sdamien {"uartc", "pllP_out0", 408000000, 0}, 292156321Sdamien {"uartd", "pllP_out0", 408000000, 0}, 293156321Sdamien {"pllA_out", NULL, 282240000, 1}, 294156321Sdamien {"pllA_out0", NULL, 11289600, 1}, 295156321Sdamien {"extperiph1", "pllA_out0", 0, 1}, 296156321Sdamien {"i2s0", "pllA_out0", 11289600, 0}, 297156321Sdamien {"i2s1", "pllA_out0", 11289600, 0}, 298156321Sdamien {"i2s2", "pllA_out0", 11289600, 0}, 299156321Sdamien {"i2s3", "pllA_out0", 11289600, 0}, 300156321Sdamien {"i2s4", "pllA_out0", 11289600, 0}, 301156321Sdamien {"vde", "pllP_out0", 0, 0}, 302145247Sdamien {"host1x", "pllP_out0", 136000000, 1}, 303145247Sdamien {"sclk", "pllP_out2", 102000000, 1}, 304156321Sdamien {"dvfs_soc", "pllP_out0", 51000000, 1}, 305145247Sdamien {"dvfs_ref", "pllP_out0", 51000000, 1}, 306156321Sdamien {"pllC_out0", NULL, 600000000, 0}, 307145247Sdamien {"pllC_out1", NULL, 100000000, 0}, 308145247Sdamien {"spi4", "pllP_out0", 12000000, 1}, 309145247Sdamien {"tsec", "pllC3_out0", 0, 0}, 310145247Sdamien {"msenc", "pllC3_out0", 0, 0}, 311145247Sdamien {"pllREFE_out", NULL, 672000000, 0}, 312145247Sdamien {"pc_xusb_ss", "pllU_480", 120000000, 0}, 313145247Sdamien {"xusb_ss", "pc_xusb_ss", 120000000, 0}, 314156321Sdamien {"pc_xusb_fs", "pllU_48", 48000000, 0}, 315145247Sdamien {"xusb_hs", "pllU_60", 60000000, 0}, 316156321Sdamien {"pc_xusb_falcon", "pllREFE_out", 224000000, 0}, 317145247Sdamien {"xusb_core_host", "pllREFE_out", 112000000, 0}, 318145247Sdamien {"sata", "pllP_out0", 102000000, 0}, 319145247Sdamien {"sata_oob", "pllP_out0", 204000000, 0}, 320 {"sata_cold", NULL, 0, 1}, 321 {"emc", NULL, 0, 1}, 322 {"mselect", NULL, 0, 1}, 323 {"csite", NULL, 0, 1}, 324 {"tsensor", "clk_m", 400000, 0}, 325 326 /* tegra124 only*/ 327 {"soc_therm", "pllP_out0", 51000000, 0}, 328 {"cclk_g", NULL, 0, 1}, 329 {"hda", "pllP_out0", 102000000, 0}, 330 {"hda2codec_2x", "pllP_out0", 48000000, 0}, 331}; 332 333static void 334init_divs(struct tegra124_car_softc *sc, struct clk_div_def *clks, int nclks) 335{ 336 int i, rv; 337 338 for (i = 0; i < nclks; i++) { 339 rv = clknode_div_register(sc->clkdom, clks + i); 340 if (rv != 0) 341 panic("clk_div_register failed"); 342 } 343} 344 345static void 346init_gates(struct tegra124_car_softc *sc, struct clk_gate_def *clks, int nclks) 347{ 348 int i, rv; 349 350 351 for (i = 0; i < nclks; i++) { 352 rv = clknode_gate_register(sc->clkdom, clks + i); 353 if (rv != 0) 354 panic("clk_gate_register failed"); 355 } 356} 357 358static void 359init_muxes(struct tegra124_car_softc *sc, struct clk_mux_def *clks, int nclks) 360{ 361 int i, rv; 362 363 364 for (i = 0; i < nclks; i++) { 365 rv = clknode_mux_register(sc->clkdom, clks + i); 366 if (rv != 0) 367 panic("clk_mux_register failed"); 368 } 369} 370 371static void 372init_fixeds(struct tegra124_car_softc *sc, struct clk_fixed_def *clks, 373 int nclks) 374{ 375 int i, rv; 376 uint32_t val; 377 int osc_idx; 378 379 CLKDEV_READ_4(sc->dev, OSC_CTRL, &val); 380 osc_idx = val >> OSC_CTRL_OSC_FREQ_SHIFT; 381 fixed_clk_m.freq = osc_freqs[osc_idx]; 382 if (fixed_clk_m.freq == 0) 383 panic("Undefined input frequency"); 384 rv = clknode_fixed_register(sc->clkdom, &fixed_clk_m); 385 if (rv != 0) panic("clk_fixed_register failed"); 386 387 val = (val >> OSC_CTRL_PLL_REF_DIV_SHIFT) & 3; 388 fixed_osc_div_clk.div = 1 << val; 389 rv = clknode_fixed_register(sc->clkdom, &fixed_osc_div_clk); 390 if (rv != 0) panic("clk_fixed_register failed"); 391 392 for (i = 0; i < nclks; i++) { 393 rv = clknode_fixed_register(sc->clkdom, clks + i); 394 if (rv != 0) 395 panic("clk_fixed_register failed"); 396 } 397} 398 399static void 400postinit_clock(struct tegra124_car_softc *sc) 401{ 402 int i; 403 struct tegra124_init_item *tbl; 404 struct clknode *clknode; 405 int rv; 406 407 for (i = 0; i < nitems(clk_init_table); i++) { 408 tbl = &clk_init_table[i]; 409 410 clknode = clknode_find_by_name(tbl->name); 411 if (clknode == NULL) { 412 device_printf(sc->dev, "Cannot find clock %s\n", 413 tbl->name); 414 continue; 415 } 416 if (tbl->parent != NULL) { 417 rv = clknode_set_parent_by_name(clknode, tbl->parent); 418 if (rv != 0) { 419 device_printf(sc->dev, 420 "Cannot set parent for %s (to %s): %d\n", 421 tbl->name, tbl->parent, rv); 422 continue; 423 } 424 } 425 if (tbl->frequency != 0) { 426 rv = clknode_set_freq(clknode, tbl->frequency, 0 , 9999); 427 if (rv != 0) { 428 device_printf(sc->dev, 429 "Cannot set frequency for %s: %d\n", 430 tbl->name, rv); 431 continue; 432 } 433 } 434 if (tbl->enable!= 0) { 435 rv = clknode_enable(clknode); 436 if (rv != 0) { 437 device_printf(sc->dev, 438 "Cannot enable %s: %d\n", tbl->name, rv); 439 continue; 440 } 441 } 442 } 443} 444 445static void 446register_clocks(device_t dev) 447{ 448 struct tegra124_car_softc *sc; 449 450 sc = device_get_softc(dev); 451 sc->clkdom = clkdom_create(dev); 452 if (sc->clkdom == NULL) 453 panic("clkdom == NULL"); 454 455 tegra124_init_plls(sc); 456 init_fixeds(sc, tegra124_fixed_clks, nitems(tegra124_fixed_clks)); 457 init_muxes(sc, tegra124_mux_clks, nitems(tegra124_mux_clks)); 458 init_divs(sc, tegra124_div_clks, nitems(tegra124_div_clks)); 459 init_gates(sc, tegra124_gate_clks, nitems(tegra124_gate_clks)); 460 tegra124_periph_clock(sc); 461 tegra124_super_mux_clock(sc); 462 clkdom_finit(sc->clkdom); 463 clkdom_xlock(sc->clkdom); 464 postinit_clock(sc); 465 clkdom_unlock(sc->clkdom); 466 if (bootverbose) 467 clkdom_dump(sc->clkdom); 468} 469 470static int 471tegra124_car_clkdev_read_4(device_t dev, bus_addr_t addr, uint32_t *val) 472{ 473 struct tegra124_car_softc *sc; 474 475 sc = device_get_softc(dev); 476 *val = bus_read_4(sc->mem_res, addr); 477 return (0); 478} 479 480static int 481tegra124_car_clkdev_write_4(device_t dev, bus_addr_t addr, uint32_t val) 482{ 483 struct tegra124_car_softc *sc; 484 485 sc = device_get_softc(dev); 486 bus_write_4(sc->mem_res, addr, val); 487 return (0); 488} 489 490static int 491tegra124_car_clkdev_modify_4(device_t dev, bus_addr_t addr, uint32_t clear_mask, 492 uint32_t set_mask) 493{ 494 struct tegra124_car_softc *sc; 495 uint32_t reg; 496 497 sc = device_get_softc(dev); 498 reg = bus_read_4(sc->mem_res, addr); 499 reg &= ~clear_mask; 500 reg |= set_mask; 501 bus_write_4(sc->mem_res, addr, reg); 502 return (0); 503} 504 505static void 506tegra124_car_clkdev_device_lock(device_t dev) 507{ 508 struct tegra124_car_softc *sc; 509 510 sc = device_get_softc(dev); 511 mtx_lock(&sc->mtx); 512} 513 514static void 515tegra124_car_clkdev_device_unlock(device_t dev) 516{ 517 struct tegra124_car_softc *sc; 518 519 sc = device_get_softc(dev); 520 mtx_unlock(&sc->mtx); 521} 522 523static int 524tegra124_car_detach(device_t dev) 525{ 526 527 device_printf(dev, "Error: Clock driver cannot be detached\n"); 528 return (EBUSY); 529} 530 531static int 532tegra124_car_probe(device_t dev) 533{ 534 535 if (!ofw_bus_status_okay(dev)) 536 return (ENXIO); 537 538 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data != 0) { 539 device_set_desc(dev, "Tegra Clock Driver"); 540 return (BUS_PROBE_DEFAULT); 541 } 542 543 return (ENXIO); 544} 545 546static int 547tegra124_car_attach(device_t dev) 548{ 549 struct tegra124_car_softc *sc = device_get_softc(dev); 550 int rid, rv; 551 552 sc->dev = dev; 553 554 mtx_init(&sc->mtx, device_get_nameunit(dev), NULL, MTX_DEF); 555 sc->type = ofw_bus_search_compatible(dev, compat_data)->ocd_data; 556 557 /* Resource setup. */ 558 rid = 0; 559 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 560 RF_ACTIVE); 561 if (!sc->mem_res) { 562 device_printf(dev, "cannot allocate memory resource\n"); 563 rv = ENXIO; 564 goto fail; 565 } 566 567 register_clocks(dev); 568 hwreset_register_ofw_provider(dev); 569 return (0); 570 571fail: 572 if (sc->mem_res) 573 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res); 574 575 return (rv); 576} 577 578static int 579tegra124_car_hwreset_assert(device_t dev, intptr_t id, bool value) 580{ 581 struct tegra124_car_softc *sc = device_get_softc(dev); 582 583 return (tegra124_hwreset_by_idx(sc, id, value)); 584} 585 586static device_method_t tegra124_car_methods[] = { 587 /* Device interface */ 588 DEVMETHOD(device_probe, tegra124_car_probe), 589 DEVMETHOD(device_attach, tegra124_car_attach), 590 DEVMETHOD(device_detach, tegra124_car_detach), 591 592 /* Clkdev interface*/ 593 DEVMETHOD(clkdev_read_4, tegra124_car_clkdev_read_4), 594 DEVMETHOD(clkdev_write_4, tegra124_car_clkdev_write_4), 595 DEVMETHOD(clkdev_modify_4, tegra124_car_clkdev_modify_4), 596 DEVMETHOD(clkdev_device_lock, tegra124_car_clkdev_device_lock), 597 DEVMETHOD(clkdev_device_unlock, tegra124_car_clkdev_device_unlock), 598 599 /* Reset interface */ 600 DEVMETHOD(hwreset_assert, tegra124_car_hwreset_assert), 601 602 DEVMETHOD_END 603}; 604 605static devclass_t tegra124_car_devclass; 606static DEFINE_CLASS_0(car, tegra124_car_driver, tegra124_car_methods, 607 sizeof(struct tegra124_car_softc)); 608EARLY_DRIVER_MODULE(tegra124_car, simplebus, tegra124_car_driver, 609 tegra124_car_devclass, NULL, NULL, BUS_PASS_TIMER); 610