lpc_dmac.c revision 330897 
1/*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2011 Jakub Wojciech Klama <jceel@FreeBSD.org>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 *
28 */
29
30#include <sys/cdefs.h>
31__FBSDID("$FreeBSD: stable/11/sys/arm/lpc/lpc_dmac.c 330897 2018-03-14 03:19:51Z eadler $");
32
33#include <sys/param.h>
34#include <sys/systm.h>
35#include <sys/bio.h>
36#include <sys/bus.h>
37#include <sys/conf.h>
38#include <sys/endian.h>
39#include <sys/kernel.h>
40#include <sys/kthread.h>
41#include <sys/lock.h>
42#include <sys/malloc.h>
43#include <sys/module.h>
44#include <sys/mutex.h>
45#include <sys/queue.h>
46#include <sys/resource.h>
47#include <sys/rman.h>
48#include <sys/time.h>
49#include <sys/timetc.h>
50#include <sys/watchdog.h>
51
52#include <sys/kdb.h>
53
54#include <dev/ofw/ofw_bus.h>
55#include <dev/ofw/ofw_bus_subr.h>
56
57#include <arm/lpc/lpcreg.h>
58#include <arm/lpc/lpcvar.h>
59
60struct lpc_dmac_channel
61{
62	struct lpc_dmac_channel_config *ldc_config;
63	int			ldc_flags;
64};
65
66struct lpc_dmac_softc
67{
68	device_t		ld_dev;
69	struct mtx		ld_mtx;
70	struct resource *	ld_mem_res;
71	struct resource *	ld_irq_res;
72	bus_space_tag_t		ld_bst;
73	bus_space_handle_t	ld_bsh;
74	void *			ld_intrhand;
75	struct lpc_dmac_channel	ld_channels[8];
76};
77
78static struct lpc_dmac_softc *lpc_dmac_sc = NULL;
79
80static int lpc_dmac_probe(device_t);
81static int lpc_dmac_attach(device_t);
82static void lpc_dmac_intr(void *);
83
84#define	lpc_dmac_read_4(_sc, _reg) \
85    bus_space_read_4(_sc->ld_bst, _sc->ld_bsh, _reg)
86#define	lpc_dmac_write_4(_sc, _reg, _value) \
87    bus_space_write_4(_sc->ld_bst, _sc->ld_bsh, _reg, _value)
88#define	lpc_dmac_read_ch_4(_sc, _n, _reg) \
89    bus_space_read_4(_sc->ld_bst, _sc->ld_bsh, (_reg + LPC_DMAC_CHADDR(_n)))
90#define	lpc_dmac_write_ch_4(_sc, _n, _reg, _value) \
91    bus_space_write_4(_sc->ld_bst, _sc->ld_bsh, (_reg + LPC_DMAC_CHADDR(_n)), _value)
92
93static int lpc_dmac_probe(device_t dev)
94{
95
96	if (!ofw_bus_status_okay(dev))
97		return (ENXIO);
98
99	if (!ofw_bus_is_compatible(dev, "lpc,dmac"))
100		return (ENXIO);
101
102	device_set_desc(dev, "LPC32x0 General Purpose DMA controller");
103	return (BUS_PROBE_DEFAULT);
104}
105
106static int lpc_dmac_attach(device_t dev)
107{
108	struct lpc_dmac_softc *sc = device_get_softc(dev);
109	int rid;
110
111	rid = 0;
112	sc->ld_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
113	    RF_ACTIVE);
114	if (!sc->ld_mem_res) {
115		device_printf(dev, "cannot allocate memory window\n");
116		return (ENXIO);
117	}
118
119	sc->ld_bst = rman_get_bustag(sc->ld_mem_res);
120	sc->ld_bsh = rman_get_bushandle(sc->ld_mem_res);
121
122	rid = 0;
123	sc->ld_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
124	    RF_ACTIVE);
125	if (!sc->ld_irq_res) {
126		device_printf(dev, "cannot allocate cmd interrupt\n");
127		bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->ld_mem_res);
128		return (ENXIO);
129	}
130
131	if (bus_setup_intr(dev, sc->ld_irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
132	    NULL, lpc_dmac_intr, sc, &sc->ld_intrhand))
133	{
134		bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->ld_mem_res);
135		bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ld_irq_res);
136		device_printf(dev, "cannot setup interrupt handler\n");
137		return (ENXIO);
138	}
139
140	lpc_dmac_sc = sc;
141
142	lpc_pwr_write(dev, LPC_CLKPWR_DMACLK_CTRL, LPC_CLKPWR_DMACLK_CTRL_EN);
143	lpc_dmac_write_4(sc, LPC_DMAC_CONFIG, LPC_DMAC_CONFIG_ENABLE);
144
145	lpc_dmac_write_4(sc, LPC_DMAC_INTTCCLEAR, 0xff);
146	lpc_dmac_write_4(sc, LPC_DMAC_INTERRCLEAR, 0xff);
147
148	return (0);
149}
150
151static void lpc_dmac_intr(void *arg)
152{
153	struct lpc_dmac_softc *sc = (struct lpc_dmac_softc *)arg;
154	struct lpc_dmac_channel *ch;
155	uint32_t intstat, tcstat, errstat;
156	int i;
157
158	do {
159		intstat = lpc_dmac_read_4(sc, LPC_DMAC_INTSTAT);
160
161		for (i = 0; i < LPC_DMAC_CHNUM; i++) {
162			if ((intstat & (1 << i)) == 0)
163				continue;
164
165			ch = &sc->ld_channels[i];
166			tcstat = lpc_dmac_read_4(sc, LPC_DMAC_INTTCSTAT);
167			errstat = lpc_dmac_read_4(sc, LPC_DMAC_INTERRSTAT);
168
169			if (tcstat & (1 << i)) {
170				ch->ldc_config->ldc_success_handler(
171				    ch->ldc_config->ldc_handler_arg);
172				lpc_dmac_write_4(sc, LPC_DMAC_INTTCCLEAR, (1 << i));
173			}
174
175			if (errstat & (1 << i)) {
176				ch->ldc_config->ldc_error_handler(
177				    ch->ldc_config->ldc_handler_arg);
178				lpc_dmac_write_4(sc, LPC_DMAC_INTERRCLEAR, (1 << i));
179			}
180		}
181
182	} while (intstat);
183}
184
185int
186lpc_dmac_config_channel(device_t dev, int chno, struct lpc_dmac_channel_config *cfg)
187{
188	struct lpc_dmac_softc *sc = lpc_dmac_sc;
189	struct lpc_dmac_channel *ch;
190
191	if (sc == NULL)
192		return (ENXIO);
193
194	ch = &sc->ld_channels[chno];
195	ch->ldc_config = cfg;
196
197	return 0;
198}
199
200int
201lpc_dmac_setup_transfer(device_t dev, int chno, bus_addr_t src, bus_addr_t dst,
202    bus_size_t size, int flags)
203{
204	struct lpc_dmac_softc *sc = lpc_dmac_sc;
205	struct lpc_dmac_channel *ch;
206	uint32_t ctrl, cfg;
207
208	if (sc == NULL)
209		return (ENXIO);
210
211	ch = &sc->ld_channels[chno];
212
213	ctrl = LPC_DMAC_CH_CONTROL_I |
214	    (ch->ldc_config->ldc_dst_incr ? LPC_DMAC_CH_CONTROL_DI : 0) |
215	    (ch->ldc_config->ldc_src_incr ? LPC_DMAC_CH_CONTROL_SI : 0) |
216	    LPC_DMAC_CH_CONTROL_DWIDTH(ch->ldc_config->ldc_dst_width) |
217	    LPC_DMAC_CH_CONTROL_SWIDTH(ch->ldc_config->ldc_src_width) |
218	    LPC_DMAC_CH_CONTROL_DBSIZE(ch->ldc_config->ldc_dst_burst) |
219	    LPC_DMAC_CH_CONTROL_SBSIZE(ch->ldc_config->ldc_src_burst) |
220	    size;
221
222	cfg = LPC_DMAC_CH_CONFIG_ITC | LPC_DMAC_CH_CONFIG_IE |
223	    LPC_DMAC_CH_CONFIG_FLOWCNTL(ch->ldc_config->ldc_fcntl) |
224	    LPC_DMAC_CH_CONFIG_DESTP(ch->ldc_config->ldc_dst_periph) |
225	    LPC_DMAC_CH_CONFIG_SRCP(ch->ldc_config->ldc_src_periph) | LPC_DMAC_CH_CONFIG_E;
226	lpc_dmac_write_ch_4(sc, chno, LPC_DMAC_CH_SRCADDR, src);
227	lpc_dmac_write_ch_4(sc, chno, LPC_DMAC_CH_DSTADDR, dst);
228	lpc_dmac_write_ch_4(sc, chno, LPC_DMAC_CH_LLI, 0);
229	lpc_dmac_write_ch_4(sc, chno, LPC_DMAC_CH_CONTROL, ctrl);
230	lpc_dmac_write_ch_4(sc, chno, LPC_DMAC_CH_CONFIG, cfg);
231
232	return 0;
233}
234
235int
236lpc_dmac_enable_channel(device_t dev, int chno)
237{
238	struct lpc_dmac_softc *sc = lpc_dmac_sc;
239	uint32_t cfg;
240
241	if (sc == NULL)
242		return (ENXIO);
243
244	cfg = lpc_dmac_read_ch_4(sc, chno, LPC_DMAC_CH_CONFIG);
245	cfg |= LPC_DMAC_CH_CONFIG_E;
246
247	lpc_dmac_write_ch_4(sc, chno, LPC_DMAC_CH_CONFIG, cfg);
248
249	return 0;
250}
251
252int
253lpc_dmac_disable_channel(device_t dev, int chno)
254{
255	struct lpc_dmac_softc *sc = lpc_dmac_sc;
256	uint32_t cfg;
257
258	if (sc == NULL)
259		return (ENXIO);
260
261	cfg = lpc_dmac_read_ch_4(sc, chno, LPC_DMAC_CH_CONFIG);
262	cfg &= ~LPC_DMAC_CH_CONFIG_E;
263
264	lpc_dmac_write_ch_4(sc, chno, LPC_DMAC_CH_CONFIG, cfg);
265
266	return 0;
267}
268
269int
270lpc_dmac_start_burst(device_t dev, int id)
271{
272	struct lpc_dmac_softc *sc = lpc_dmac_sc;
273
274	lpc_dmac_write_4(sc, LPC_DMAC_SOFTBREQ, (1 << id));
275	return (0);
276}
277
278static device_method_t lpc_dmac_methods[] = {
279	/* Device interface */
280	DEVMETHOD(device_probe,		lpc_dmac_probe),
281	DEVMETHOD(device_attach,	lpc_dmac_attach),
282
283	{ 0, 0 },
284};
285
286static devclass_t lpc_dmac_devclass;
287
288static driver_t lpc_dmac_driver = {
289	"dmac",
290	lpc_dmac_methods,
291	sizeof(struct lpc_dmac_softc),
292};
293
294DRIVER_MODULE(dmac, simplebus, lpc_dmac_driver, lpc_dmac_devclass, 0, 0);
295