imx_i2c.c revision 323931
1/*- 2 * Copyright (C) 2008-2009 Semihalf, Michal Hajduk 3 * Copyright (c) 2012, 2013 The FreeBSD Foundation 4 * Copyright (c) 2015 Ian Lepore <ian@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Portions of this software were developed by Oleksandr Rybalko 8 * under sponsorship from the FreeBSD Foundation. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32/* 33 * I2C driver for Freescale i.MX hardware. 34 * 35 * Note that the hardware is capable of running as both a master and a slave. 36 * This driver currently implements only master-mode operations. 37 * 38 * This driver supports multi-master i2c busses, by detecting bus arbitration 39 * loss and returning IIC_EBUSBSY status. Notably, it does not do any kind of 40 * retries if some other master jumps onto the bus and interrupts one of our 41 * transfer cycles resulting in arbitration loss in mid-transfer. The caller 42 * must handle retries in a way that makes sense for the slave being addressed. 43 */ 44 45#include <sys/cdefs.h> 46__FBSDID("$FreeBSD: stable/11/sys/arm/freescale/imx/imx_i2c.c 323931 2017-09-22 15:53:22Z ian $"); 47 48#include <sys/param.h> 49#include <sys/systm.h> 50#include <sys/bus.h> 51#include <sys/gpio.h> 52#include <sys/kernel.h> 53#include <sys/limits.h> 54#include <sys/module.h> 55#include <sys/resource.h> 56#include <sys/sysctl.h> 57 58#include <machine/bus.h> 59#include <machine/resource.h> 60#include <sys/rman.h> 61 62#include <arm/freescale/imx/imx_ccmvar.h> 63 64#include <dev/iicbus/iiconf.h> 65#include <dev/iicbus/iicbus.h> 66#include <dev/iicbus/iic_recover_bus.h> 67#include "iicbus_if.h" 68 69#include <dev/fdt/fdt_common.h> 70#include <dev/ofw/openfirm.h> 71#include <dev/ofw/ofw_bus.h> 72#include <dev/ofw/ofw_bus_subr.h> 73 74#include <dev/fdt/fdt_pinctrl.h> 75#include <dev/gpio/gpiobusvar.h> 76 77#define I2C_ADDR_REG 0x00 /* I2C slave address register */ 78#define I2C_FDR_REG 0x04 /* I2C frequency divider register */ 79#define I2C_CONTROL_REG 0x08 /* I2C control register */ 80#define I2C_STATUS_REG 0x0C /* I2C status register */ 81#define I2C_DATA_REG 0x10 /* I2C data register */ 82#define I2C_DFSRR_REG 0x14 /* I2C Digital Filter Sampling rate */ 83 84#define I2CCR_MEN (1 << 7) /* Module enable */ 85#define I2CCR_MSTA (1 << 5) /* Master/slave mode */ 86#define I2CCR_MTX (1 << 4) /* Transmit/receive mode */ 87#define I2CCR_TXAK (1 << 3) /* Transfer acknowledge */ 88#define I2CCR_RSTA (1 << 2) /* Repeated START */ 89 90#define I2CSR_MCF (1 << 7) /* Data transfer */ 91#define I2CSR_MASS (1 << 6) /* Addressed as a slave */ 92#define I2CSR_MBB (1 << 5) /* Bus busy */ 93#define I2CSR_MAL (1 << 4) /* Arbitration lost */ 94#define I2CSR_SRW (1 << 2) /* Slave read/write */ 95#define I2CSR_MIF (1 << 1) /* Module interrupt */ 96#define I2CSR_RXAK (1 << 0) /* Received acknowledge */ 97 98#define I2C_BAUD_RATE_FAST 0x31 99#define I2C_BAUD_RATE_DEF 0x3F 100#define I2C_DFSSR_DIV 0x10 101 102/* 103 * A table of available divisors and the associated coded values to put in the 104 * FDR register to achieve that divisor.. There is no algorithmic relationship I 105 * can see between divisors and the codes that go into the register. The table 106 * begins and ends with entries that handle insane configuration values. 107 */ 108struct clkdiv { 109 u_int divisor; 110 u_int regcode; 111}; 112static struct clkdiv clkdiv_table[] = { 113 { 0, 0x20 }, { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, 114 { 28, 0x23 }, { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, 115 { 40, 0x26 }, { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, 116 { 52, 0x05 }, { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2a }, 117 { 72, 0x2b }, { 80, 0x2c }, { 88, 0x09 }, { 96, 0x2d }, 118 { 104, 0x0a }, { 112, 0x2e }, { 128, 0x2f }, { 144, 0x0c }, 119 { 160, 0x30 }, { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0f }, 120 { 256, 0x33 }, { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, 121 { 448, 0x36 }, { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, 122 { 640, 0x38 }, { 768, 0x39 }, { 896, 0x3a }, { 960, 0x17 }, 123 { 1024, 0x3b }, { 1152, 0x18 }, { 1280, 0x3c }, { 1536, 0x3d }, 124 { 1792, 0x3e }, { 1920, 0x1b }, { 2048, 0x3f }, { 2304, 0x1c }, 125 { 2560, 0x1d }, { 3072, 0x1e }, { 3840, 0x1f }, {UINT_MAX, 0x1f} 126}; 127 128static struct ofw_compat_data compat_data[] = { 129 {"fsl,imx6q-i2c", 1}, 130 {"fsl,imx-i2c", 1}, 131 {NULL, 0} 132}; 133 134struct i2c_softc { 135 device_t dev; 136 device_t iicbus; 137 struct resource *res; 138 int rid; 139 sbintime_t byte_time_sbt; 140 int rb_pinctl_idx; 141 gpio_pin_t rb_sclpin; 142 gpio_pin_t rb_sdapin; 143 u_int debug; 144 u_int slave; 145}; 146 147#define DEVICE_DEBUGF(sc, lvl, fmt, args...) \ 148 if ((lvl) <= (sc)->debug) \ 149 device_printf((sc)->dev, fmt, ##args) 150 151#define DEBUGF(sc, lvl, fmt, args...) \ 152 if ((lvl) <= (sc)->debug) \ 153 printf(fmt, ##args) 154 155static phandle_t i2c_get_node(device_t, device_t); 156static int i2c_probe(device_t); 157static int i2c_attach(device_t); 158 159static int i2c_repeated_start(device_t, u_char, int); 160static int i2c_start(device_t, u_char, int); 161static int i2c_stop(device_t); 162static int i2c_reset(device_t, u_char, u_char, u_char *); 163static int i2c_read(device_t, char *, int, int *, int, int); 164static int i2c_write(device_t, const char *, int, int *, int); 165 166static device_method_t i2c_methods[] = { 167 DEVMETHOD(device_probe, i2c_probe), 168 DEVMETHOD(device_attach, i2c_attach), 169 170 /* OFW methods */ 171 DEVMETHOD(ofw_bus_get_node, i2c_get_node), 172 173 DEVMETHOD(iicbus_callback, iicbus_null_callback), 174 DEVMETHOD(iicbus_repeated_start, i2c_repeated_start), 175 DEVMETHOD(iicbus_start, i2c_start), 176 DEVMETHOD(iicbus_stop, i2c_stop), 177 DEVMETHOD(iicbus_reset, i2c_reset), 178 DEVMETHOD(iicbus_read, i2c_read), 179 DEVMETHOD(iicbus_write, i2c_write), 180 DEVMETHOD(iicbus_transfer, iicbus_transfer_gen), 181 182 DEVMETHOD_END 183}; 184 185static driver_t i2c_driver = { 186 "iichb", 187 i2c_methods, 188 sizeof(struct i2c_softc), 189}; 190static devclass_t i2c_devclass; 191 192DRIVER_MODULE(i2c, simplebus, i2c_driver, i2c_devclass, 0, 0); 193DRIVER_MODULE(iicbus, i2c, iicbus_driver, iicbus_devclass, 0, 0); 194 195static phandle_t 196i2c_get_node(device_t bus, device_t dev) 197{ 198 /* 199 * Share controller node with iicbus device 200 */ 201 return ofw_bus_get_node(bus); 202} 203 204static __inline void 205i2c_write_reg(struct i2c_softc *sc, bus_size_t off, uint8_t val) 206{ 207 208 bus_write_1(sc->res, off, val); 209} 210 211static __inline uint8_t 212i2c_read_reg(struct i2c_softc *sc, bus_size_t off) 213{ 214 215 return (bus_read_1(sc->res, off)); 216} 217 218static __inline void 219i2c_flag_set(struct i2c_softc *sc, bus_size_t off, uint8_t mask) 220{ 221 uint8_t status; 222 223 status = i2c_read_reg(sc, off); 224 status |= mask; 225 i2c_write_reg(sc, off, status); 226} 227 228/* Wait for bus to become busy or not-busy. */ 229static int 230wait_for_busbusy(struct i2c_softc *sc, int wantbusy) 231{ 232 int retry, srb; 233 234 retry = 1000; 235 while (retry --) { 236 srb = i2c_read_reg(sc, I2C_STATUS_REG) & I2CSR_MBB; 237 if ((srb && wantbusy) || (!srb && !wantbusy)) 238 return (IIC_NOERR); 239 DELAY(1); 240 } 241 return (IIC_ETIMEOUT); 242} 243 244/* Wait for transfer to complete, optionally check RXAK. */ 245static int 246wait_for_xfer(struct i2c_softc *sc, int checkack) 247{ 248 int retry, sr; 249 250 /* 251 * Sleep for about the time it takes to transfer a byte (with precision 252 * set to tolerate 5% oversleep). We calculate the approximate byte 253 * transfer time when we set the bus speed divisor. Slaves are allowed 254 * to do clock-stretching so the actual transfer time can be larger, but 255 * this gets the bulk of the waiting out of the way without tying up the 256 * processor the whole time. 257 */ 258 pause_sbt("imxi2c", sc->byte_time_sbt, sc->byte_time_sbt / 20, 0); 259 260 retry = 10000; 261 while (retry --) { 262 sr = i2c_read_reg(sc, I2C_STATUS_REG); 263 if (sr & I2CSR_MIF) { 264 if (sr & I2CSR_MAL) 265 return (IIC_EBUSERR); 266 else if (checkack && (sr & I2CSR_RXAK)) 267 return (IIC_ENOACK); 268 else 269 return (IIC_NOERR); 270 } 271 DELAY(1); 272 } 273 return (IIC_ETIMEOUT); 274} 275 276/* 277 * Implement the error handling shown in the state diagram of the imx6 reference 278 * manual. If there was an error, then: 279 * - Clear master mode (MSTA and MTX). 280 * - Wait for the bus to become free or for a timeout to happen. 281 * - Disable the controller. 282 */ 283static int 284i2c_error_handler(struct i2c_softc *sc, int error) 285{ 286 287 if (error != 0) { 288 i2c_write_reg(sc, I2C_STATUS_REG, 0); 289 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN); 290 wait_for_busbusy(sc, false); 291 i2c_write_reg(sc, I2C_CONTROL_REG, 0); 292 } 293 return (error); 294} 295 296static int 297i2c_recover_getsda(void *ctx) 298{ 299 bool active; 300 301 gpio_pin_is_active(((struct i2c_softc *)ctx)->rb_sdapin, &active); 302 return (active); 303} 304 305static void 306i2c_recover_setsda(void *ctx, int value) 307{ 308 309 gpio_pin_set_active(((struct i2c_softc *)ctx)->rb_sdapin, value); 310} 311 312static int 313i2c_recover_getscl(void *ctx) 314{ 315 bool active; 316 317 gpio_pin_is_active(((struct i2c_softc *)ctx)->rb_sclpin, &active); 318 return (active); 319 320} 321 322static void 323i2c_recover_setscl(void *ctx, int value) 324{ 325 326 gpio_pin_set_active(((struct i2c_softc *)ctx)->rb_sclpin, value); 327} 328 329static int 330i2c_recover_bus(struct i2c_softc *sc) 331{ 332 struct iicrb_pin_access pins; 333 int err; 334 335 /* 336 * If we have gpio pinmux config, reconfigure the pins to gpio mode, 337 * invoke iic_recover_bus which checks for a hung bus and bitbangs a 338 * recovery sequence if necessary, then configure the pins back to i2c 339 * mode (idx 0). 340 */ 341 if (sc->rb_pinctl_idx == 0) 342 return (0); 343 344 fdt_pinctrl_configure(sc->dev, sc->rb_pinctl_idx); 345 346 pins.ctx = sc; 347 pins.getsda = i2c_recover_getsda; 348 pins.setsda = i2c_recover_setsda; 349 pins.getscl = i2c_recover_getscl; 350 pins.setscl = i2c_recover_setscl; 351 err = iic_recover_bus(&pins); 352 353 fdt_pinctrl_configure(sc->dev, 0); 354 355 return (err); 356} 357 358static int 359i2c_probe(device_t dev) 360{ 361 362 if (!ofw_bus_status_okay(dev)) 363 return (ENXIO); 364 365 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 366 return (ENXIO); 367 368 device_set_desc(dev, "Freescale i.MX I2C"); 369 370 return (BUS_PROBE_DEFAULT); 371} 372 373static int 374i2c_attach(device_t dev) 375{ 376 char wrkstr[16]; 377 struct i2c_softc *sc; 378 phandle_t node; 379 int err, cfgidx; 380 381 sc = device_get_softc(dev); 382 sc->dev = dev; 383 sc->rid = 0; 384 385 sc->res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->rid, 386 RF_ACTIVE); 387 if (sc->res == NULL) { 388 device_printf(dev, "could not allocate resources"); 389 return (ENXIO); 390 } 391 392 sc->iicbus = device_add_child(dev, "iicbus", -1); 393 if (sc->iicbus == NULL) { 394 device_printf(dev, "could not add iicbus child"); 395 return (ENXIO); 396 } 397 398 /* Set up debug-enable sysctl. */ 399 SYSCTL_ADD_INT(device_get_sysctl_ctx(sc->dev), 400 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), 401 OID_AUTO, "debug", CTLFLAG_RWTUN, &sc->debug, 0, 402 "Enable debug; 1=reads/writes, 2=add starts/stops"); 403 404 /* 405 * Set up for bus recovery using gpio pins, if the pinctrl and gpio 406 * properties are present. This is optional. If all the config data is 407 * not in place, we just don't do gpio bitbang bus recovery. 408 */ 409 node = ofw_bus_get_node(sc->dev); 410 411 err = gpio_pin_get_by_ofw_property(dev, node, "scl-gpios", 412 &sc->rb_sclpin); 413 if (err != 0) 414 goto no_recovery; 415 err = gpio_pin_get_by_ofw_property(dev, node, "sda-gpios", 416 &sc->rb_sdapin); 417 if (err != 0) 418 goto no_recovery; 419 420 /* 421 * Preset the gpio pins to output high (idle bus state). The signal 422 * won't actually appear on the pins until the bus recovery code changes 423 * the pinmux config from i2c to gpio. 424 */ 425 gpio_pin_setflags(sc->rb_sclpin, GPIO_PIN_OUTPUT); 426 gpio_pin_setflags(sc->rb_sdapin, GPIO_PIN_OUTPUT); 427 gpio_pin_set_active(sc->rb_sclpin, true); 428 gpio_pin_set_active(sc->rb_sdapin, true); 429 430 /* 431 * Obtain the index of pinctrl node for bus recovery using gpio pins, 432 * then confirm that pinctrl properties exist for that index and for the 433 * default pinctrl-0. If sc->rb_pinctl_idx is non-zero, the reset code 434 * will also do a bus recovery, so setting this value must be last. 435 */ 436 err = ofw_bus_find_string_index(node, "pinctrl-names", "gpio", &cfgidx); 437 if (err == 0) { 438 snprintf(wrkstr, sizeof(wrkstr), "pinctrl-%d", cfgidx); 439 if (OF_hasprop(node, "pinctrl-0") && OF_hasprop(node, wrkstr)) 440 sc->rb_pinctl_idx = cfgidx; 441 } 442 443no_recovery: 444 445 /* We don't do a hardware reset here because iicbus_attach() does it. */ 446 447 /* Probe and attach the iicbus when interrupts are available. */ 448 config_intrhook_oneshot((ich_func_t)bus_generic_attach, dev); 449 return (0); 450} 451 452static int 453i2c_repeated_start(device_t dev, u_char slave, int timeout) 454{ 455 struct i2c_softc *sc; 456 int error; 457 458 sc = device_get_softc(dev); 459 460 if ((i2c_read_reg(sc, I2C_STATUS_REG) & I2CSR_MBB) == 0) { 461 return (IIC_EBUSERR); 462 } 463 464 /* 465 * Set repeated start condition, delay (per reference manual, min 156nS) 466 * before writing slave address, wait for ack after write. 467 */ 468 i2c_flag_set(sc, I2C_CONTROL_REG, I2CCR_RSTA); 469 DELAY(1); 470 i2c_write_reg(sc, I2C_STATUS_REG, 0x0); 471 i2c_write_reg(sc, I2C_DATA_REG, slave); 472 sc->slave = slave; 473 DEVICE_DEBUGF(sc, 2, "rstart 0x%02x\n", sc->slave); 474 error = wait_for_xfer(sc, true); 475 return (i2c_error_handler(sc, error)); 476} 477 478static int 479i2c_start_ll(device_t dev, u_char slave, int timeout) 480{ 481 struct i2c_softc *sc; 482 int error; 483 484 sc = device_get_softc(dev); 485 486 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN); 487 DELAY(10); /* Delay for controller to sample bus state. */ 488 if (i2c_read_reg(sc, I2C_STATUS_REG) & I2CSR_MBB) { 489 return (i2c_error_handler(sc, IIC_EBUSERR)); 490 } 491 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN | I2CCR_MSTA | I2CCR_MTX); 492 if ((error = wait_for_busbusy(sc, true)) != IIC_NOERR) 493 return (i2c_error_handler(sc, error)); 494 i2c_write_reg(sc, I2C_STATUS_REG, 0); 495 i2c_write_reg(sc, I2C_DATA_REG, slave); 496 sc->slave = slave; 497 DEVICE_DEBUGF(sc, 2, "start 0x%02x\n", sc->slave); 498 error = wait_for_xfer(sc, true); 499 return (i2c_error_handler(sc, error)); 500} 501 502static int 503i2c_start(device_t dev, u_char slave, int timeout) 504{ 505 struct i2c_softc *sc; 506 int error; 507 508 sc = device_get_softc(dev); 509 510 /* 511 * Invoke the low-level code to put the bus into master mode and address 512 * the given slave. If that fails, idle the controller and attempt a 513 * bus recovery, and then try again one time. Signaling a start and 514 * addressing the slave is the only operation that a low-level driver 515 * can safely retry without any help from the upper layers that know 516 * more about the slave device. 517 */ 518 if ((error = i2c_start_ll(dev, slave, timeout)) != 0) { 519 i2c_write_reg(sc, I2C_CONTROL_REG, 0x0); 520 if ((error = i2c_recover_bus(sc)) != 0) 521 return (error); 522 error = i2c_start_ll(dev, slave, timeout); 523 } 524 return (error); 525} 526 527static int 528i2c_stop(device_t dev) 529{ 530 struct i2c_softc *sc; 531 532 sc = device_get_softc(dev); 533 534 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN); 535 wait_for_busbusy(sc, false); 536 i2c_write_reg(sc, I2C_CONTROL_REG, 0); 537 DEVICE_DEBUGF(sc, 2, "stop 0x%02x\n", sc->slave); 538 return (IIC_NOERR); 539} 540 541static int 542i2c_reset(device_t dev, u_char speed, u_char addr, u_char *oldadr) 543{ 544 struct i2c_softc *sc; 545 u_int busfreq, div, i, ipgfreq; 546 547 sc = device_get_softc(dev); 548 549 DEVICE_DEBUGF(sc, 1, "reset\n"); 550 551 /* 552 * Look up the divisor that gives the nearest speed that doesn't exceed 553 * the configured value for the bus. 554 */ 555 ipgfreq = imx_ccm_ipg_hz(); 556 busfreq = IICBUS_GET_FREQUENCY(sc->iicbus, speed); 557 div = howmany(ipgfreq, busfreq); 558 for (i = 0; i < nitems(clkdiv_table); i++) { 559 if (clkdiv_table[i].divisor >= div) 560 break; 561 } 562 563 /* 564 * Calculate roughly how long it will take to transfer a byte (which 565 * requires 9 clock cycles) at the new bus speed. This value is used to 566 * pause() while waiting for transfer-complete. With a 66MHz IPG clock 567 * and the actual i2c bus speeds that leads to, for nominal 100KHz and 568 * 400KHz bus speeds the transfer times are roughly 104uS and 22uS. 569 */ 570 busfreq = ipgfreq / clkdiv_table[i].divisor; 571 sc->byte_time_sbt = SBT_1US * (9000000 / busfreq); 572 573 /* 574 * Disable the controller (do the reset), and set the new clock divisor. 575 */ 576 i2c_write_reg(sc, I2C_STATUS_REG, 0x0); 577 i2c_write_reg(sc, I2C_CONTROL_REG, 0x0); 578 i2c_write_reg(sc, I2C_FDR_REG, (uint8_t)clkdiv_table[i].regcode); 579 580 /* 581 * Now that the controller is idle, perform bus recovery. If the bus 582 * isn't hung, this a fairly fast no-op. 583 */ 584 return (i2c_recover_bus(sc)); 585} 586 587static int 588i2c_read(device_t dev, char *buf, int len, int *read, int last, int delay) 589{ 590 struct i2c_softc *sc; 591 int error, reg; 592 593 sc = device_get_softc(dev); 594 *read = 0; 595 596 DEVICE_DEBUGF(sc, 1, "read 0x%02x len %d: ", sc->slave, len); 597 if (len) { 598 if (len == 1) 599 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN | 600 I2CCR_MSTA | I2CCR_TXAK); 601 else 602 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN | 603 I2CCR_MSTA); 604 /* Dummy read to prime the receiver. */ 605 i2c_write_reg(sc, I2C_STATUS_REG, 0x0); 606 i2c_read_reg(sc, I2C_DATA_REG); 607 } 608 609 error = 0; 610 *read = 0; 611 while (*read < len) { 612 if ((error = wait_for_xfer(sc, false)) != IIC_NOERR) 613 break; 614 i2c_write_reg(sc, I2C_STATUS_REG, 0x0); 615 if (last) { 616 if (*read == len - 2) { 617 /* NO ACK on last byte */ 618 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN | 619 I2CCR_MSTA | I2CCR_TXAK); 620 } else if (*read == len - 1) { 621 /* Transfer done, signal stop. */ 622 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN | 623 I2CCR_TXAK); 624 wait_for_busbusy(sc, false); 625 } 626 } 627 reg = i2c_read_reg(sc, I2C_DATA_REG); 628 DEBUGF(sc, 1, "0x%02x ", reg); 629 *buf++ = reg; 630 (*read)++; 631 } 632 DEBUGF(sc, 1, "\n"); 633 634 return (i2c_error_handler(sc, error)); 635} 636 637static int 638i2c_write(device_t dev, const char *buf, int len, int *sent, int timeout) 639{ 640 struct i2c_softc *sc; 641 int error; 642 643 sc = device_get_softc(dev); 644 645 error = 0; 646 *sent = 0; 647 DEVICE_DEBUGF(sc, 1, "write 0x%02x len %d: ", sc->slave, len); 648 while (*sent < len) { 649 DEBUGF(sc, 1, "0x%02x ", *buf); 650 i2c_write_reg(sc, I2C_STATUS_REG, 0x0); 651 i2c_write_reg(sc, I2C_DATA_REG, *buf++); 652 if ((error = wait_for_xfer(sc, true)) != IIC_NOERR) 653 break; 654 (*sent)++; 655 } 656 DEBUGF(sc, 1, "\n"); 657 return (i2c_error_handler(sc, error)); 658} 659