imx_gpt.c revision 323401
1/*- 2 * Copyright (c) 2012, 2013 The FreeBSD Foundation 3 * All rights reserved. 4 * 5 * This software was developed by Oleksandr Rybalko under sponsorship 6 * from the FreeBSD Foundation. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD: stable/11/sys/arm/freescale/imx/imx_gpt.c 323401 2017-09-10 23:12:07Z ian $"); 32 33#include <sys/param.h> 34#include <sys/systm.h> 35#include <sys/bus.h> 36#include <sys/kernel.h> 37#include <sys/module.h> 38#include <sys/rman.h> 39#include <sys/timeet.h> 40#include <sys/timetc.h> 41#include <machine/bus.h> 42#include <machine/intr.h> 43 44#include <dev/fdt/fdt_common.h> 45#include <dev/ofw/openfirm.h> 46#include <dev/ofw/ofw_bus.h> 47#include <dev/ofw/ofw_bus_subr.h> 48 49#include <arm/freescale/imx/imx_ccmvar.h> 50#include <arm/freescale/imx/imx_gptreg.h> 51 52#define WRITE4(_sc, _r, _v) \ 53 bus_space_write_4((_sc)->sc_iot, (_sc)->sc_ioh, (_r), (_v)) 54#define READ4(_sc, _r) \ 55 bus_space_read_4((_sc)->sc_iot, (_sc)->sc_ioh, (_r)) 56#define SET4(_sc, _r, _m) \ 57 WRITE4((_sc), (_r), READ4((_sc), (_r)) | (_m)) 58#define CLEAR4(_sc, _r, _m) \ 59 WRITE4((_sc), (_r), READ4((_sc), (_r)) & ~(_m)) 60 61static u_int imx_gpt_get_timecount(struct timecounter *); 62static int imx_gpt_timer_start(struct eventtimer *, sbintime_t, 63 sbintime_t); 64static int imx_gpt_timer_stop(struct eventtimer *); 65 66static int imx_gpt_intr(void *); 67static int imx_gpt_probe(device_t); 68static int imx_gpt_attach(device_t); 69 70static struct timecounter imx_gpt_timecounter = { 71 .tc_name = "iMXGPT", 72 .tc_get_timecount = imx_gpt_get_timecount, 73 .tc_counter_mask = ~0u, 74 .tc_frequency = 0, 75 .tc_quality = 1000, 76}; 77 78struct imx_gpt_softc { 79 device_t sc_dev; 80 struct resource * res[2]; 81 bus_space_tag_t sc_iot; 82 bus_space_handle_t sc_ioh; 83 void * sc_ih; /* interrupt handler */ 84 uint32_t sc_period; 85 uint32_t sc_clksrc; 86 uint32_t clkfreq; 87 struct eventtimer et; 88}; 89 90/* Global softc pointer for use in DELAY(). */ 91static struct imx_gpt_softc *imx_gpt_sc; 92 93/* 94 * Hand-calibrated delay-loop counter. This was calibrated on an i.MX6 running 95 * at 792mhz. It will delay a bit too long on slower processors -- that's 96 * better than not delaying long enough. In practice this is unlikely to get 97 * used much since the clock driver is one of the first to start up, and once 98 * we're attached the delay loop switches to using the timer hardware. 99 */ 100static const int imx_gpt_delay_count = 78; 101 102/* Try to divide down an available fast clock to this frequency. */ 103#define TARGET_FREQUENCY 1000000000 104 105/* Don't try to set an event timer period smaller than this. */ 106#define MIN_ET_PERIOD 10LLU 107 108 109static struct resource_spec imx_gpt_spec[] = { 110 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 111 { SYS_RES_IRQ, 0, RF_ACTIVE }, 112 { -1, 0 } 113}; 114 115static struct ofw_compat_data compat_data[] = { 116 {"fsl,imx6dl-gpt", 1}, 117 {"fsl,imx6q-gpt", 1}, 118 {"fsl,imx53-gpt", 1}, 119 {"fsl,imx51-gpt", 1}, 120 {"fsl,imx31-gpt", 1}, 121 {"fsl,imx27-gpt", 1}, 122 {"fsl,imx25-gpt", 1}, 123 {NULL, 0} 124}; 125 126static int 127imx_gpt_probe(device_t dev) 128{ 129 130 if (!ofw_bus_status_okay(dev)) 131 return (ENXIO); 132 133 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data != 0) { 134 device_set_desc(dev, "Freescale i.MX GPT timer"); 135 return (BUS_PROBE_DEFAULT); 136 } 137 138 return (ENXIO); 139} 140 141static int 142imx_gpt_attach(device_t dev) 143{ 144 struct imx_gpt_softc *sc; 145 int ctlreg, err; 146 uint32_t basefreq, prescale; 147 148 sc = device_get_softc(dev); 149 150 if (bus_alloc_resources(dev, imx_gpt_spec, sc->res)) { 151 device_printf(dev, "could not allocate resources\n"); 152 return (ENXIO); 153 } 154 155 sc->sc_dev = dev; 156 sc->sc_iot = rman_get_bustag(sc->res[0]); 157 sc->sc_ioh = rman_get_bushandle(sc->res[0]); 158 159 /* 160 * For now, just automatically choose a good clock for the hardware 161 * we're running on. Eventually we could allow selection from the fdt; 162 * the code in this driver will cope with any clock frequency. 163 */ 164 sc->sc_clksrc = GPT_CR_CLKSRC_IPG; 165 166 ctlreg = 0; 167 168 switch (sc->sc_clksrc) { 169 case GPT_CR_CLKSRC_32K: 170 basefreq = 32768; 171 break; 172 case GPT_CR_CLKSRC_IPG: 173 basefreq = imx_ccm_ipg_hz(); 174 break; 175 case GPT_CR_CLKSRC_IPG_HIGH: 176 basefreq = imx_ccm_ipg_hz() * 2; 177 break; 178 case GPT_CR_CLKSRC_24M: 179 ctlreg |= GPT_CR_24MEN; 180 basefreq = 24000000; 181 break; 182 case GPT_CR_CLKSRC_NONE:/* Can't run without a clock. */ 183 case GPT_CR_CLKSRC_EXT: /* No way to get the freq of an ext clock. */ 184 default: 185 device_printf(dev, "Unsupported clock source '%d'\n", 186 sc->sc_clksrc); 187 return (EINVAL); 188 } 189 190 /* 191 * The following setup sequence is from the I.MX6 reference manual, 192 * "Selecting the clock source". First, disable the clock and 193 * interrupts. This also clears input and output mode bits and in 194 * general completes several of the early steps in the procedure. 195 */ 196 WRITE4(sc, IMX_GPT_CR, 0); 197 WRITE4(sc, IMX_GPT_IR, 0); 198 199 /* Choose the clock and the power-saving behaviors. */ 200 ctlreg |= 201 sc->sc_clksrc | /* Use selected clock */ 202 GPT_CR_FRR | /* Just count (FreeRunner mode) */ 203 GPT_CR_STOPEN | /* Run in STOP mode */ 204 GPT_CR_DOZEEN | /* Run in DOZE mode */ 205 GPT_CR_WAITEN | /* Run in WAIT mode */ 206 GPT_CR_DBGEN; /* Run in DEBUG mode */ 207 WRITE4(sc, IMX_GPT_CR, ctlreg); 208 209 /* 210 * The datasheet says to do the software reset after choosing the clock 211 * source. It says nothing about needing to wait for the reset to 212 * complete, but the register description does document the fact that 213 * the reset isn't complete until the SWR bit reads 0, so let's be safe. 214 * The reset also clears all registers except for a few of the bits in 215 * CR, but we'll rewrite all the CR bits when we start the counter. 216 */ 217 WRITE4(sc, IMX_GPT_CR, ctlreg | GPT_CR_SWR); 218 while (READ4(sc, IMX_GPT_CR) & GPT_CR_SWR) 219 continue; 220 221 /* Set a prescaler value that gets us near the target frequency. */ 222 if (basefreq < TARGET_FREQUENCY) { 223 prescale = 0; 224 sc->clkfreq = basefreq; 225 } else { 226 prescale = basefreq / TARGET_FREQUENCY; 227 sc->clkfreq = basefreq / prescale; 228 prescale -= 1; /* 1..n range is 0..n-1 in hardware. */ 229 } 230 WRITE4(sc, IMX_GPT_PR, prescale); 231 232 /* Clear the status register. */ 233 WRITE4(sc, IMX_GPT_SR, GPT_IR_ALL); 234 235 /* Start the counter. */ 236 WRITE4(sc, IMX_GPT_CR, ctlreg | GPT_CR_EN); 237 238 if (bootverbose) 239 device_printf(dev, "Running on %dKHz clock, base freq %uHz CR=0x%08x, PR=0x%08x\n", 240 sc->clkfreq / 1000, basefreq, READ4(sc, IMX_GPT_CR), READ4(sc, IMX_GPT_PR)); 241 242 /* Setup the timer interrupt. */ 243 err = bus_setup_intr(dev, sc->res[1], INTR_TYPE_CLK, imx_gpt_intr, 244 NULL, sc, &sc->sc_ih); 245 if (err != 0) { 246 bus_release_resources(dev, imx_gpt_spec, sc->res); 247 device_printf(dev, "Unable to setup the clock irq handler, " 248 "err = %d\n", err); 249 return (ENXIO); 250 } 251 252 /* Register as an eventtimer. */ 253 sc->et.et_name = "iMXGPT"; 254 sc->et.et_flags = ET_FLAGS_ONESHOT | ET_FLAGS_PERIODIC; 255 sc->et.et_quality = 800; 256 sc->et.et_frequency = sc->clkfreq; 257 sc->et.et_min_period = (MIN_ET_PERIOD << 32) / sc->et.et_frequency; 258 sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency; 259 sc->et.et_start = imx_gpt_timer_start; 260 sc->et.et_stop = imx_gpt_timer_stop; 261 sc->et.et_priv = sc; 262 et_register(&sc->et); 263 264 /* Register as a timecounter. */ 265 imx_gpt_timecounter.tc_frequency = sc->clkfreq; 266 tc_init(&imx_gpt_timecounter); 267 268 /* If this is the first unit, store the softc for use in DELAY. */ 269 if (device_get_unit(dev) == 0) 270 imx_gpt_sc = sc; 271 272 return (0); 273} 274 275static int 276imx_gpt_timer_start(struct eventtimer *et, sbintime_t first, sbintime_t period) 277{ 278 struct imx_gpt_softc *sc; 279 uint32_t ticks; 280 281 sc = (struct imx_gpt_softc *)et->et_priv; 282 283 if (period != 0) { 284 sc->sc_period = ((uint32_t)et->et_frequency * period) >> 32; 285 /* Set expected value */ 286 WRITE4(sc, IMX_GPT_OCR2, READ4(sc, IMX_GPT_CNT) + sc->sc_period); 287 /* Enable compare register 2 Interrupt */ 288 SET4(sc, IMX_GPT_IR, GPT_IR_OF2); 289 return (0); 290 } else if (first != 0) { 291 ticks = ((uint32_t)et->et_frequency * first) >> 32; 292 /* Do not disturb, otherwise event will be lost */ 293 spinlock_enter(); 294 /* Set expected value */ 295 WRITE4(sc, IMX_GPT_OCR3, READ4(sc, IMX_GPT_CNT) + ticks); 296 /* Enable compare register 1 Interrupt */ 297 SET4(sc, IMX_GPT_IR, GPT_IR_OF3); 298 /* Now everybody can relax */ 299 spinlock_exit(); 300 return (0); 301 } 302 303 return (EINVAL); 304} 305 306static int 307imx_gpt_timer_stop(struct eventtimer *et) 308{ 309 struct imx_gpt_softc *sc; 310 311 sc = (struct imx_gpt_softc *)et->et_priv; 312 313 /* Disable OF2 Interrupt */ 314 CLEAR4(sc, IMX_GPT_IR, GPT_IR_OF2); 315 WRITE4(sc, IMX_GPT_SR, GPT_IR_OF2); 316 sc->sc_period = 0; 317 318 return (0); 319} 320 321static int 322imx_gpt_intr(void *arg) 323{ 324 struct imx_gpt_softc *sc; 325 uint32_t status; 326 327 sc = (struct imx_gpt_softc *)arg; 328 329 status = READ4(sc, IMX_GPT_SR); 330 331 /* 332 * Clear interrupt status before invoking event callbacks. The callback 333 * often sets up a new one-shot timer event and if the interval is short 334 * enough it can fire before we get out of this function. If we cleared 335 * at the bottom we'd miss the interrupt and hang until the clock wraps. 336 */ 337 WRITE4(sc, IMX_GPT_SR, status); 338 339 /* Handle one-shot timer events. */ 340 if (status & GPT_IR_OF3) { 341 if (sc->et.et_active) { 342 sc->et.et_event_cb(&sc->et, sc->et.et_arg); 343 } 344 } 345 346 /* Handle periodic timer events. */ 347 if (status & GPT_IR_OF2) { 348 if (sc->et.et_active) 349 sc->et.et_event_cb(&sc->et, sc->et.et_arg); 350 if (sc->sc_period != 0) 351 WRITE4(sc, IMX_GPT_OCR2, READ4(sc, IMX_GPT_CNT) + 352 sc->sc_period); 353 } 354 355 return (FILTER_HANDLED); 356} 357 358u_int 359imx_gpt_get_timecount(struct timecounter *tc) 360{ 361 362 if (imx_gpt_sc == NULL) 363 return (0); 364 365 return (READ4(imx_gpt_sc, IMX_GPT_CNT)); 366} 367 368static device_method_t imx_gpt_methods[] = { 369 DEVMETHOD(device_probe, imx_gpt_probe), 370 DEVMETHOD(device_attach, imx_gpt_attach), 371 372 DEVMETHOD_END 373}; 374 375static driver_t imx_gpt_driver = { 376 "imx_gpt", 377 imx_gpt_methods, 378 sizeof(struct imx_gpt_softc), 379}; 380 381static devclass_t imx_gpt_devclass; 382 383EARLY_DRIVER_MODULE(imx_gpt, simplebus, imx_gpt_driver, imx_gpt_devclass, 0, 384 0, BUS_PASS_TIMER); 385 386void 387DELAY(int usec) 388{ 389 uint64_t curcnt, endcnt, startcnt, ticks; 390 391 /* If the timer hardware is not accessible, just use a loop. */ 392 if (imx_gpt_sc == NULL) { 393 while (usec-- > 0) 394 for (ticks = 0; ticks < imx_gpt_delay_count; ++ticks) 395 cpufunc_nullop(); 396 return; 397 } 398 399 /* 400 * Calculate the tick count with 64-bit values so that it works for any 401 * clock frequency. Loop until the hardware count reaches start+ticks. 402 * If the 32-bit hardware count rolls over while we're looping, just 403 * manually do a carry into the high bits after each read; don't worry 404 * that doing this on each loop iteration is inefficient -- we're trying 405 * to waste time here. 406 */ 407 ticks = 1 + ((uint64_t)usec * imx_gpt_sc->clkfreq) / 1000000; 408 curcnt = startcnt = READ4(imx_gpt_sc, IMX_GPT_CNT); 409 endcnt = startcnt + ticks; 410 while (curcnt < endcnt) { 411 curcnt = READ4(imx_gpt_sc, IMX_GPT_CNT); 412 if (curcnt < startcnt) 413 curcnt += 1ULL << 32; 414 } 415} 416