imx_gpio.c revision 346520
1/*- 2 * Copyright (c) 2012, 2013 The FreeBSD Foundation 3 * All rights reserved. 4 * 5 * This software was developed by Oleksandr Rybalko under sponsorship 6 * from the FreeBSD Foundation. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30/* 31 * Freescale i.MX515 GPIO driver. 32 */ 33 34#include <sys/cdefs.h> 35__FBSDID("$FreeBSD: stable/11/sys/arm/freescale/imx/imx_gpio.c 346520 2019-04-22 04:07:51Z ian $"); 36 37#include "opt_platform.h" 38 39#include <sys/param.h> 40#include <sys/systm.h> 41#include <sys/bus.h> 42 43#include <sys/kernel.h> 44#include <sys/module.h> 45#include <sys/rman.h> 46#include <sys/lock.h> 47#include <sys/mutex.h> 48#include <sys/gpio.h> 49#include <sys/proc.h> 50 51#include <machine/bus.h> 52#include <machine/intr.h> 53#include <machine/resource.h> 54 55#include <dev/fdt/fdt_common.h> 56#include <dev/gpio/gpiobusvar.h> 57#include <dev/ofw/openfirm.h> 58#include <dev/ofw/ofw_bus.h> 59#include <dev/ofw/ofw_bus_subr.h> 60 61#include "gpio_if.h" 62 63#ifdef INTRNG 64#include "pic_if.h" 65#endif 66 67#define WRITE4(_sc, _r, _v) \ 68 bus_space_write_4((_sc)->sc_iot, (_sc)->sc_ioh, (_r), (_v)) 69#define READ4(_sc, _r) \ 70 bus_space_read_4((_sc)->sc_iot, (_sc)->sc_ioh, (_r)) 71#define SET4(_sc, _r, _m) \ 72 WRITE4((_sc), (_r), READ4((_sc), (_r)) | (_m)) 73#define CLEAR4(_sc, _r, _m) \ 74 WRITE4((_sc), (_r), READ4((_sc), (_r)) & ~(_m)) 75 76/* Registers definition for Freescale i.MX515 GPIO controller */ 77 78#define IMX_GPIO_DR_REG 0x000 /* Pin Data */ 79#define IMX_GPIO_OE_REG 0x004 /* Set Pin Output */ 80#define IMX_GPIO_PSR_REG 0x008 /* Pad Status */ 81#define IMX_GPIO_ICR1_REG 0x00C /* Interrupt Configuration */ 82#define IMX_GPIO_ICR2_REG 0x010 /* Interrupt Configuration */ 83#define GPIO_ICR_COND_LOW 0 84#define GPIO_ICR_COND_HIGH 1 85#define GPIO_ICR_COND_RISE 2 86#define GPIO_ICR_COND_FALL 3 87#define GPIO_ICR_COND_MASK 0x3 88#define IMX_GPIO_IMR_REG 0x014 /* Interrupt Mask Register */ 89#define IMX_GPIO_ISR_REG 0x018 /* Interrupt Status Register */ 90#define IMX_GPIO_EDGE_REG 0x01C /* Edge Detect Register */ 91 92#ifdef INTRNG 93#define DEFAULT_CAPS (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | \ 94 GPIO_INTR_LEVEL_LOW | GPIO_INTR_LEVEL_HIGH | GPIO_INTR_EDGE_RISING | \ 95 GPIO_INTR_EDGE_FALLING | GPIO_INTR_EDGE_BOTH) 96#else 97#define DEFAULT_CAPS (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT) 98#endif 99 100#define NGPIO 32 101 102#ifdef INTRNG 103struct gpio_irqsrc { 104 struct intr_irqsrc gi_isrc; 105 u_int gi_irq; 106 uint32_t gi_mode; 107}; 108#endif 109 110struct imx51_gpio_softc { 111 device_t dev; 112 device_t sc_busdev; 113 struct mtx sc_mtx; 114 struct resource *sc_res[3]; /* 1 x mem, 2 x IRQ */ 115 void *gpio_ih[2]; 116 bus_space_tag_t sc_iot; 117 bus_space_handle_t sc_ioh; 118 int gpio_npins; 119 struct gpio_pin gpio_pins[NGPIO]; 120#ifdef INTRNG 121 struct gpio_irqsrc gpio_pic_irqsrc[NGPIO]; 122#endif 123}; 124 125static struct ofw_compat_data compat_data[] = { 126 {"fsl,imx6q-gpio", 1}, 127 {"fsl,imx53-gpio", 1}, 128 {"fsl,imx51-gpio", 1}, 129 {NULL, 0} 130}; 131 132static struct resource_spec imx_gpio_spec[] = { 133 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 134 { SYS_RES_IRQ, 0, RF_ACTIVE }, 135 { SYS_RES_IRQ, 1, RF_ACTIVE }, 136 { -1, 0 } 137}; 138#define FIRST_IRQRES 1 139#define NUM_IRQRES 2 140 141/* 142 * Helpers 143 */ 144static void imx51_gpio_pin_configure(struct imx51_gpio_softc *, 145 struct gpio_pin *, uint32_t); 146 147/* 148 * Driver stuff 149 */ 150static int imx51_gpio_probe(device_t); 151static int imx51_gpio_attach(device_t); 152static int imx51_gpio_detach(device_t); 153 154/* 155 * GPIO interface 156 */ 157static device_t imx51_gpio_get_bus(device_t); 158static int imx51_gpio_pin_max(device_t, int *); 159static int imx51_gpio_pin_getcaps(device_t, uint32_t, uint32_t *); 160static int imx51_gpio_pin_getflags(device_t, uint32_t, uint32_t *); 161static int imx51_gpio_pin_getname(device_t, uint32_t, char *); 162static int imx51_gpio_pin_setflags(device_t, uint32_t, uint32_t); 163static int imx51_gpio_pin_set(device_t, uint32_t, unsigned int); 164static int imx51_gpio_pin_get(device_t, uint32_t, unsigned int *); 165static int imx51_gpio_pin_toggle(device_t, uint32_t pin); 166 167#ifdef INTRNG 168static int 169gpio_pic_map_fdt(struct imx51_gpio_softc *sc, struct intr_map_data_fdt *daf, 170 u_int *irqp, uint32_t *modep) 171{ 172 u_int irq; 173 uint32_t mode; 174 175 /* 176 * From devicetree/bindings/gpio/fsl-imx-gpio.txt: 177 * #interrupt-cells: 2. The first cell is the GPIO number. The second 178 * cell bits[3:0] is used to specify trigger type and level flags: 179 * 1 = low-to-high edge triggered. 180 * 2 = high-to-low edge triggered. 181 * 4 = active high level-sensitive. 182 * 8 = active low level-sensitive. 183 * We can do any single one of these modes, and also edge low+high 184 * (i.e., trigger on both edges); other combinations are not supported. 185 */ 186 187 if (daf->ncells != 2) { 188 device_printf(sc->dev, "Invalid #interrupt-cells\n"); 189 return (EINVAL); 190 } 191 192 irq = daf->cells[0]; 193 if (irq >= sc->gpio_npins) { 194 device_printf(sc->dev, "Invalid interrupt number %u\n", irq); 195 return (EINVAL); 196 } 197 switch (daf->cells[1]) { 198 case 1: 199 mode = GPIO_INTR_EDGE_RISING; 200 break; 201 case 2: 202 mode = GPIO_INTR_EDGE_FALLING; 203 break; 204 case 3: 205 mode = GPIO_INTR_EDGE_BOTH; 206 break; 207 case 4: 208 mode = GPIO_INTR_LEVEL_HIGH; 209 break; 210 case 8: 211 mode = GPIO_INTR_LEVEL_LOW; 212 break; 213 default: 214 device_printf(sc->dev, "Unsupported interrupt mode 0x%2x\n", 215 daf->cells[1]); 216 return (ENOTSUP); 217 } 218 *irqp = irq; 219 if (modep != NULL) 220 *modep = mode; 221 return (0); 222} 223 224static int 225gpio_pic_map_gpio(struct imx51_gpio_softc *sc, struct intr_map_data_gpio *dag, 226 u_int *irqp, uint32_t *modep) 227{ 228 u_int irq; 229 230 irq = dag->gpio_pin_num; 231 if (irq >= sc->gpio_npins) { 232 device_printf(sc->dev, "Invalid interrupt number %u\n", irq); 233 return (EINVAL); 234 } 235 236 switch (dag->gpio_intr_mode) { 237 case GPIO_INTR_LEVEL_LOW: 238 case GPIO_INTR_LEVEL_HIGH: 239 case GPIO_INTR_EDGE_RISING: 240 case GPIO_INTR_EDGE_FALLING: 241 case GPIO_INTR_EDGE_BOTH: 242 break; 243 default: 244 device_printf(sc->dev, "Unsupported interrupt mode 0x%8x\n", 245 dag->gpio_intr_mode); 246 return (EINVAL); 247 } 248 249 *irqp = irq; 250 if (modep != NULL) 251 *modep = dag->gpio_intr_mode; 252 return (0); 253} 254 255static int 256gpio_pic_map(struct imx51_gpio_softc *sc, struct intr_map_data *data, 257 u_int *irqp, uint32_t *modep) 258{ 259 260 switch (data->type) { 261 case INTR_MAP_DATA_FDT: 262 return (gpio_pic_map_fdt(sc, (struct intr_map_data_fdt *)data, 263 irqp, modep)); 264 case INTR_MAP_DATA_GPIO: 265 return (gpio_pic_map_gpio(sc, (struct intr_map_data_gpio *)data, 266 irqp, modep)); 267 default: 268 return (ENOTSUP); 269 } 270} 271 272static int 273gpio_pic_map_intr(device_t dev, struct intr_map_data *data, 274 struct intr_irqsrc **isrcp) 275{ 276 int error; 277 u_int irq; 278 struct imx51_gpio_softc *sc; 279 280 sc = device_get_softc(dev); 281 error = gpio_pic_map(sc, data, &irq, NULL); 282 if (error == 0) 283 *isrcp = &sc->gpio_pic_irqsrc[irq].gi_isrc; 284 return (error); 285} 286 287static int 288gpio_pic_teardown_intr(device_t dev, struct intr_irqsrc *isrc, 289 struct resource *res, struct intr_map_data *data) 290{ 291 struct imx51_gpio_softc *sc; 292 struct gpio_irqsrc *gi; 293 294 sc = device_get_softc(dev); 295 if (isrc->isrc_handlers == 0) { 296 gi = (struct gpio_irqsrc *)isrc; 297 gi->gi_mode = GPIO_INTR_CONFORM; 298 299 // XXX Not sure this is necessary 300 mtx_lock_spin(&sc->sc_mtx); 301 CLEAR4(sc, IMX_GPIO_IMR_REG, (1U << gi->gi_irq)); 302 WRITE4(sc, IMX_GPIO_ISR_REG, (1U << gi->gi_irq)); 303 mtx_unlock_spin(&sc->sc_mtx); 304 } 305 return (0); 306} 307 308static int 309gpio_pic_setup_intr(device_t dev, struct intr_irqsrc *isrc, 310 struct resource *res, struct intr_map_data *data) 311{ 312 struct imx51_gpio_softc *sc; 313 struct gpio_irqsrc *gi; 314 int error; 315 u_int icfg, irq, reg, shift, wrk; 316 uint32_t mode; 317 318 if (data == NULL) 319 return (ENOTSUP); 320 321 sc = device_get_softc(dev); 322 gi = (struct gpio_irqsrc *)isrc; 323 324 /* Get config for interrupt. */ 325 error = gpio_pic_map(sc, data, &irq, &mode); 326 if (error != 0) 327 return (error); 328 if (gi->gi_irq != irq) 329 return (EINVAL); 330 331 /* Compare config if this is not first setup. */ 332 if (isrc->isrc_handlers != 0) 333 return (gi->gi_mode == mode ? 0 : EINVAL); 334 gi->gi_mode = mode; 335 336 /* 337 * To interrupt on both edges we have to use the EDGE register. The 338 * manual says it only exists for backwards compatibilty with older imx 339 * chips, but it's also the only way to configure interrupting on both 340 * edges. If the EDGE bit is on, the corresponding ICRn bit is ignored. 341 */ 342 mtx_lock_spin(&sc->sc_mtx); 343 if (mode == GPIO_INTR_EDGE_BOTH) { 344 SET4(sc, IMX_GPIO_EDGE_REG, (1u << irq)); 345 } else { 346 CLEAR4(sc, IMX_GPIO_EDGE_REG, (1u << irq)); 347 switch (mode) { 348 default: 349 /* silence warnings; default can't actually happen. */ 350 /* FALLTHROUGH */ 351 case GPIO_INTR_LEVEL_LOW: 352 icfg = GPIO_ICR_COND_LOW; 353 break; 354 case GPIO_INTR_LEVEL_HIGH: 355 icfg = GPIO_ICR_COND_HIGH; 356 break; 357 case GPIO_INTR_EDGE_RISING: 358 icfg = GPIO_ICR_COND_RISE; 359 break; 360 case GPIO_INTR_EDGE_FALLING: 361 icfg = GPIO_ICR_COND_FALL; 362 break; 363 } 364 if (irq < 16) { 365 reg = IMX_GPIO_ICR1_REG; 366 shift = 2 * irq; 367 } else { 368 reg = IMX_GPIO_ICR2_REG; 369 shift = 2 * (irq - 16); 370 } 371 wrk = READ4(sc, reg); 372 wrk &= ~(GPIO_ICR_COND_MASK << shift); 373 wrk |= icfg << shift; 374 WRITE4(sc, reg, wrk); 375 } 376 WRITE4(sc, IMX_GPIO_ISR_REG, (1u << irq)); 377 SET4(sc, IMX_GPIO_IMR_REG, (1u << irq)); 378 mtx_unlock_spin(&sc->sc_mtx); 379 380 return (0); 381} 382 383/* 384 * this is mask_intr 385 */ 386static void 387gpio_pic_disable_intr(device_t dev, struct intr_irqsrc *isrc) 388{ 389 struct imx51_gpio_softc *sc; 390 u_int irq; 391 392 sc = device_get_softc(dev); 393 irq = ((struct gpio_irqsrc *)isrc)->gi_irq; 394 395 mtx_lock_spin(&sc->sc_mtx); 396 CLEAR4(sc, IMX_GPIO_IMR_REG, (1U << irq)); 397 mtx_unlock_spin(&sc->sc_mtx); 398} 399 400/* 401 * this is unmask_intr 402 */ 403static void 404gpio_pic_enable_intr(device_t dev, struct intr_irqsrc *isrc) 405{ 406 struct imx51_gpio_softc *sc; 407 u_int irq; 408 409 sc = device_get_softc(dev); 410 irq = ((struct gpio_irqsrc *)isrc)->gi_irq; 411 412 mtx_lock_spin(&sc->sc_mtx); 413 SET4(sc, IMX_GPIO_IMR_REG, (1U << irq)); 414 mtx_unlock_spin(&sc->sc_mtx); 415} 416 417static void 418gpio_pic_post_filter(device_t dev, struct intr_irqsrc *isrc) 419{ 420 struct imx51_gpio_softc *sc; 421 u_int irq; 422 423 sc = device_get_softc(dev); 424 irq = ((struct gpio_irqsrc *)isrc)->gi_irq; 425 426 arm_irq_memory_barrier(0); 427 /* EOI. W1C reg so no r-m-w, no locking needed. */ 428 WRITE4(sc, IMX_GPIO_ISR_REG, (1U << irq)); 429} 430 431static void 432gpio_pic_post_ithread(device_t dev, struct intr_irqsrc *isrc) 433{ 434 struct imx51_gpio_softc *sc; 435 u_int irq; 436 437 sc = device_get_softc(dev); 438 irq = ((struct gpio_irqsrc *)isrc)->gi_irq; 439 440 arm_irq_memory_barrier(0); 441 /* EOI. W1C reg so no r-m-w, no locking needed. */ 442 WRITE4(sc, IMX_GPIO_ISR_REG, (1U << irq)); 443 gpio_pic_enable_intr(dev, isrc); 444} 445 446static void 447gpio_pic_pre_ithread(device_t dev, struct intr_irqsrc *isrc) 448{ 449 gpio_pic_disable_intr(dev, isrc); 450} 451 452static int 453gpio_pic_filter(void *arg) 454{ 455 struct imx51_gpio_softc *sc; 456 struct intr_irqsrc *isrc; 457 uint32_t i, interrupts; 458 459 sc = arg; 460 mtx_lock_spin(&sc->sc_mtx); 461 interrupts = READ4(sc, IMX_GPIO_ISR_REG) & READ4(sc, IMX_GPIO_IMR_REG); 462 mtx_unlock_spin(&sc->sc_mtx); 463 464 for (i = 0; interrupts != 0; i++, interrupts >>= 1) { 465 if ((interrupts & 0x1) == 0) 466 continue; 467 isrc = &sc->gpio_pic_irqsrc[i].gi_isrc; 468 if (intr_isrc_dispatch(isrc, curthread->td_intr_frame) != 0) { 469 gpio_pic_disable_intr(sc->dev, isrc); 470 gpio_pic_post_filter(sc->dev, isrc); 471 device_printf(sc->dev, "Stray irq %u disabled\n", i); 472 } 473 } 474 475 return (FILTER_HANDLED); 476} 477 478/* 479 * Initialize our isrcs and register them with intrng. 480 */ 481static int 482gpio_pic_register_isrcs(struct imx51_gpio_softc *sc) 483{ 484 int error; 485 uint32_t irq; 486 const char *name; 487 488 name = device_get_nameunit(sc->dev); 489 for (irq = 0; irq < NGPIO; irq++) { 490 sc->gpio_pic_irqsrc[irq].gi_irq = irq; 491 sc->gpio_pic_irqsrc[irq].gi_mode = GPIO_INTR_CONFORM; 492 493 error = intr_isrc_register(&sc->gpio_pic_irqsrc[irq].gi_isrc, 494 sc->dev, 0, "%s,%u", name, irq); 495 if (error != 0) { 496 /* XXX call intr_isrc_deregister() */ 497 device_printf(sc->dev, "%s failed", __func__); 498 return (error); 499 } 500 } 501 return (0); 502} 503#endif 504 505/* 506 * 507 */ 508static void 509imx51_gpio_pin_configure(struct imx51_gpio_softc *sc, struct gpio_pin *pin, 510 unsigned int flags) 511{ 512 u_int newflags, pad; 513 514 mtx_lock_spin(&sc->sc_mtx); 515 516 /* 517 * Manage input/output; other flags not supported yet (maybe not ever, 518 * since we have no connection to the pad config registers from here). 519 * 520 * When setting a pin to output, honor the PRESET_[LOW,HIGH] flags if 521 * present. Otherwise, for glitchless transistions on pins with pulls, 522 * read the current state of the pad and preset the DR register to drive 523 * the current value onto the pin before enabling the pin for output. 524 * 525 * Note that changes to pin->gp_flags must be acccumulated in newflags 526 * and stored with a single writeback to gp_flags at the end, to enable 527 * unlocked reads of that value elsewhere. This is only about unlocked 528 * access to gp_flags from elsewhere; we still use locking in this 529 * function to protect r-m-w access to the hardware registers. 530 */ 531 if (flags & (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT)) { 532 newflags = pin->gp_flags & ~(GPIO_PIN_INPUT | GPIO_PIN_OUTPUT); 533 if (flags & GPIO_PIN_OUTPUT) { 534 if (flags & GPIO_PIN_PRESET_LOW) { 535 pad = 0; 536 } else if (flags & GPIO_PIN_PRESET_HIGH) { 537 pad = 1; 538 } else { 539 if (flags & GPIO_PIN_OPENDRAIN) 540 pad = READ4(sc, IMX_GPIO_PSR_REG); 541 else 542 pad = READ4(sc, IMX_GPIO_DR_REG); 543 pad = (pad >> pin->gp_pin) & 1; 544 } 545 newflags |= GPIO_PIN_OUTPUT; 546 SET4(sc, IMX_GPIO_DR_REG, (pad << pin->gp_pin)); 547 SET4(sc, IMX_GPIO_OE_REG, (1U << pin->gp_pin)); 548 } else { 549 newflags |= GPIO_PIN_INPUT; 550 CLEAR4(sc, IMX_GPIO_OE_REG, (1U << pin->gp_pin)); 551 } 552 pin->gp_flags = newflags; 553 } 554 555 mtx_unlock_spin(&sc->sc_mtx); 556} 557 558static device_t 559imx51_gpio_get_bus(device_t dev) 560{ 561 struct imx51_gpio_softc *sc; 562 563 sc = device_get_softc(dev); 564 565 return (sc->sc_busdev); 566} 567 568static int 569imx51_gpio_pin_max(device_t dev, int *maxpin) 570{ 571 struct imx51_gpio_softc *sc; 572 573 sc = device_get_softc(dev); 574 *maxpin = sc->gpio_npins - 1; 575 576 return (0); 577} 578 579static int 580imx51_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps) 581{ 582 struct imx51_gpio_softc *sc; 583 584 sc = device_get_softc(dev); 585 586 if (pin >= sc->gpio_npins) 587 return (EINVAL); 588 589 *caps = sc->gpio_pins[pin].gp_caps; 590 591 return (0); 592} 593 594static int 595imx51_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags) 596{ 597 struct imx51_gpio_softc *sc; 598 599 sc = device_get_softc(dev); 600 601 if (pin >= sc->gpio_npins) 602 return (EINVAL); 603 604 *flags = sc->gpio_pins[pin].gp_flags; 605 606 return (0); 607} 608 609static int 610imx51_gpio_pin_getname(device_t dev, uint32_t pin, char *name) 611{ 612 struct imx51_gpio_softc *sc; 613 614 sc = device_get_softc(dev); 615 if (pin >= sc->gpio_npins) 616 return (EINVAL); 617 618 mtx_lock_spin(&sc->sc_mtx); 619 memcpy(name, sc->gpio_pins[pin].gp_name, GPIOMAXNAME); 620 mtx_unlock_spin(&sc->sc_mtx); 621 622 return (0); 623} 624 625static int 626imx51_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags) 627{ 628 struct imx51_gpio_softc *sc; 629 630 sc = device_get_softc(dev); 631 632 if (pin >= sc->gpio_npins) 633 return (EINVAL); 634 635 imx51_gpio_pin_configure(sc, &sc->gpio_pins[pin], flags); 636 637 return (0); 638} 639 640static int 641imx51_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value) 642{ 643 struct imx51_gpio_softc *sc; 644 645 sc = device_get_softc(dev); 646 647 if (pin >= sc->gpio_npins) 648 return (EINVAL); 649 650 mtx_lock_spin(&sc->sc_mtx); 651 if (value) 652 SET4(sc, IMX_GPIO_DR_REG, (1U << pin)); 653 else 654 CLEAR4(sc, IMX_GPIO_DR_REG, (1U << pin)); 655 mtx_unlock_spin(&sc->sc_mtx); 656 657 return (0); 658} 659 660static int 661imx51_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val) 662{ 663 struct imx51_gpio_softc *sc; 664 665 sc = device_get_softc(dev); 666 667 if (pin >= sc->gpio_npins) 668 return (EINVAL); 669 670 /* 671 * Normally a pin set for output can be read by reading the DR reg which 672 * indicates what value is being driven to that pin. The exception is 673 * pins configured for open-drain mode, in which case we have to read 674 * the pad status register in case the pin is being driven externally. 675 * Doing so requires that the SION bit be configured in pinmux, which 676 * isn't the case for most normal gpio pins, so only try to read via PSR 677 * if the OPENDRAIN flag is set, and it's the user's job to correctly 678 * configure SION along with open-drain output mode for those pins. 679 */ 680 if (sc->gpio_pins[pin].gp_flags & GPIO_PIN_OPENDRAIN) 681 *val = (READ4(sc, IMX_GPIO_PSR_REG) >> pin) & 1; 682 else 683 *val = (READ4(sc, IMX_GPIO_DR_REG) >> pin) & 1; 684 685 return (0); 686} 687 688static int 689imx51_gpio_pin_toggle(device_t dev, uint32_t pin) 690{ 691 struct imx51_gpio_softc *sc; 692 693 sc = device_get_softc(dev); 694 695 if (pin >= sc->gpio_npins) 696 return (EINVAL); 697 698 mtx_lock_spin(&sc->sc_mtx); 699 WRITE4(sc, IMX_GPIO_DR_REG, 700 (READ4(sc, IMX_GPIO_DR_REG) ^ (1U << pin))); 701 mtx_unlock_spin(&sc->sc_mtx); 702 703 return (0); 704} 705 706static int 707imx51_gpio_pin_access_32(device_t dev, uint32_t first_pin, uint32_t clear_pins, 708 uint32_t change_pins, uint32_t *orig_pins) 709{ 710 struct imx51_gpio_softc *sc; 711 712 if (first_pin != 0) 713 return (EINVAL); 714 715 sc = device_get_softc(dev); 716 717 if (orig_pins != NULL) 718 *orig_pins = READ4(sc, IMX_GPIO_DR_REG); 719 720 if ((clear_pins | change_pins) != 0) { 721 mtx_lock_spin(&sc->sc_mtx); 722 WRITE4(sc, IMX_GPIO_DR_REG, 723 (READ4(sc, IMX_GPIO_DR_REG) & ~clear_pins) ^ change_pins); 724 mtx_unlock_spin(&sc->sc_mtx); 725 } 726 727 return (0); 728} 729 730static int 731imx51_gpio_pin_config_32(device_t dev, uint32_t first_pin, uint32_t num_pins, 732 uint32_t *pin_flags) 733{ 734 struct imx51_gpio_softc *sc; 735 u_int i; 736 uint32_t bit, drclr, drset, flags, oeclr, oeset, pads; 737 738 sc = device_get_softc(dev); 739 740 if (first_pin != 0 || num_pins > sc->gpio_npins) 741 return (EINVAL); 742 743 drclr = drset = oeclr = oeset = 0; 744 pads = READ4(sc, IMX_GPIO_DR_REG); 745 746 for (i = 0; i < num_pins; ++i) { 747 bit = 1u << i; 748 flags = pin_flags[i]; 749 if (flags & GPIO_PIN_INPUT) { 750 oeclr |= bit; 751 } else if (flags & GPIO_PIN_OUTPUT) { 752 oeset |= bit; 753 if (flags & GPIO_PIN_PRESET_LOW) 754 drclr |= bit; 755 else if (flags & GPIO_PIN_PRESET_HIGH) 756 drset |= bit; 757 else /* Drive whatever it's now pulled to. */ 758 drset |= pads & bit; 759 } 760 } 761 762 mtx_lock_spin(&sc->sc_mtx); 763 WRITE4(sc, IMX_GPIO_DR_REG, 764 (READ4(sc, IMX_GPIO_DR_REG) & ~drclr) | drset); 765 WRITE4(sc, IMX_GPIO_OE_REG, 766 (READ4(sc, IMX_GPIO_OE_REG) & ~oeclr) | oeset); 767 mtx_unlock_spin(&sc->sc_mtx); 768 769 return (0); 770} 771 772static int 773imx51_gpio_probe(device_t dev) 774{ 775 776 if (!ofw_bus_status_okay(dev)) 777 return (ENXIO); 778 779 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data != 0) { 780 device_set_desc(dev, "Freescale i.MX GPIO Controller"); 781 return (BUS_PROBE_DEFAULT); 782 } 783 784 return (ENXIO); 785} 786 787static int 788imx51_gpio_attach(device_t dev) 789{ 790 struct imx51_gpio_softc *sc; 791 int i, irq, unit; 792 793 sc = device_get_softc(dev); 794 sc->dev = dev; 795 sc->gpio_npins = NGPIO; 796 797 mtx_init(&sc->sc_mtx, device_get_nameunit(sc->dev), NULL, MTX_SPIN); 798 799 if (bus_alloc_resources(dev, imx_gpio_spec, sc->sc_res)) { 800 device_printf(dev, "could not allocate resources\n"); 801 bus_release_resources(dev, imx_gpio_spec, sc->sc_res); 802 mtx_destroy(&sc->sc_mtx); 803 return (ENXIO); 804 } 805 806 sc->sc_iot = rman_get_bustag(sc->sc_res[0]); 807 sc->sc_ioh = rman_get_bushandle(sc->sc_res[0]); 808 /* 809 * Mask off all interrupts in hardware, then set up interrupt handling. 810 */ 811 WRITE4(sc, IMX_GPIO_IMR_REG, 0); 812 for (irq = 0; irq < 2; irq++) { 813#ifdef INTRNG 814 if ((bus_setup_intr(dev, sc->sc_res[1 + irq], INTR_TYPE_CLK, 815 gpio_pic_filter, NULL, sc, &sc->gpio_ih[irq]))) { 816 device_printf(dev, 817 "WARNING: unable to register interrupt handler\n"); 818 imx51_gpio_detach(dev); 819 return (ENXIO); 820 } 821#endif 822 } 823 824 unit = device_get_unit(dev); 825 for (i = 0; i < sc->gpio_npins; i++) { 826 sc->gpio_pins[i].gp_pin = i; 827 sc->gpio_pins[i].gp_caps = DEFAULT_CAPS; 828 sc->gpio_pins[i].gp_flags = 829 (READ4(sc, IMX_GPIO_OE_REG) & (1U << i)) ? GPIO_PIN_OUTPUT : 830 GPIO_PIN_INPUT; 831 snprintf(sc->gpio_pins[i].gp_name, GPIOMAXNAME, 832 "GPIO%d_IO%02d", unit + 1, i); 833 } 834 835#ifdef INTRNG 836 gpio_pic_register_isrcs(sc); 837 intr_pic_register(dev, OF_xref_from_node(ofw_bus_get_node(dev))); 838#endif 839 sc->sc_busdev = gpiobus_attach_bus(dev); 840 841 if (sc->sc_busdev == NULL) { 842 imx51_gpio_detach(dev); 843 return (ENXIO); 844 } 845 846 return (0); 847} 848 849static int 850imx51_gpio_detach(device_t dev) 851{ 852 int irq; 853 struct imx51_gpio_softc *sc; 854 855 sc = device_get_softc(dev); 856 857 gpiobus_detach_bus(dev); 858 for (irq = 0; irq < NUM_IRQRES; irq++) { 859 if (sc->gpio_ih[irq]) 860 bus_teardown_intr(dev, sc->sc_res[irq + FIRST_IRQRES], 861 sc->gpio_ih[irq]); 862 } 863 bus_release_resources(dev, imx_gpio_spec, sc->sc_res); 864 mtx_destroy(&sc->sc_mtx); 865 866 return(0); 867} 868 869static device_method_t imx51_gpio_methods[] = { 870 DEVMETHOD(device_probe, imx51_gpio_probe), 871 DEVMETHOD(device_attach, imx51_gpio_attach), 872 DEVMETHOD(device_detach, imx51_gpio_detach), 873 874#ifdef INTRNG 875 /* Interrupt controller interface */ 876 DEVMETHOD(pic_disable_intr, gpio_pic_disable_intr), 877 DEVMETHOD(pic_enable_intr, gpio_pic_enable_intr), 878 DEVMETHOD(pic_map_intr, gpio_pic_map_intr), 879 DEVMETHOD(pic_setup_intr, gpio_pic_setup_intr), 880 DEVMETHOD(pic_teardown_intr, gpio_pic_teardown_intr), 881 DEVMETHOD(pic_post_filter, gpio_pic_post_filter), 882 DEVMETHOD(pic_post_ithread, gpio_pic_post_ithread), 883 DEVMETHOD(pic_pre_ithread, gpio_pic_pre_ithread), 884#endif 885 886 /* GPIO protocol */ 887 DEVMETHOD(gpio_get_bus, imx51_gpio_get_bus), 888 DEVMETHOD(gpio_pin_max, imx51_gpio_pin_max), 889 DEVMETHOD(gpio_pin_getname, imx51_gpio_pin_getname), 890 DEVMETHOD(gpio_pin_getflags, imx51_gpio_pin_getflags), 891 DEVMETHOD(gpio_pin_getcaps, imx51_gpio_pin_getcaps), 892 DEVMETHOD(gpio_pin_setflags, imx51_gpio_pin_setflags), 893 DEVMETHOD(gpio_pin_get, imx51_gpio_pin_get), 894 DEVMETHOD(gpio_pin_set, imx51_gpio_pin_set), 895 DEVMETHOD(gpio_pin_toggle, imx51_gpio_pin_toggle), 896 DEVMETHOD(gpio_pin_access_32, imx51_gpio_pin_access_32), 897 DEVMETHOD(gpio_pin_config_32, imx51_gpio_pin_config_32), 898 {0, 0}, 899}; 900 901static driver_t imx51_gpio_driver = { 902 "gpio", 903 imx51_gpio_methods, 904 sizeof(struct imx51_gpio_softc), 905}; 906static devclass_t imx51_gpio_devclass; 907 908EARLY_DRIVER_MODULE(imx51_gpio, simplebus, imx51_gpio_driver, 909 imx51_gpio_devclass, 0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LATE); 910