imx6_ccm.c revision 330897
1/*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2013 Ian Lepore <ian@freebsd.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29#include <sys/cdefs.h> 30__FBSDID("$FreeBSD: stable/11/sys/arm/freescale/imx/imx6_ccm.c 330897 2018-03-14 03:19:51Z eadler $"); 31 32/* 33 * Clocks and power control driver for Freescale i.MX6 family of SoCs. 34 */ 35 36#include <sys/param.h> 37#include <sys/systm.h> 38#include <sys/kernel.h> 39#include <sys/module.h> 40#include <sys/bus.h> 41#include <sys/rman.h> 42 43#include <dev/ofw/ofw_bus.h> 44#include <dev/ofw/ofw_bus_subr.h> 45 46#include <machine/bus.h> 47 48#include <arm/freescale/imx/imx6_anatopreg.h> 49#include <arm/freescale/imx/imx6_anatopvar.h> 50#include <arm/freescale/imx/imx6_ccmreg.h> 51#include <arm/freescale/imx/imx_machdep.h> 52#include <arm/freescale/imx/imx_ccmvar.h> 53 54#ifndef CCGR_CLK_MODE_ALWAYS 55#define CCGR_CLK_MODE_OFF 0 56#define CCGR_CLK_MODE_RUNMODE 1 57#define CCGR_CLK_MODE_ALWAYS 3 58#endif 59 60struct ccm_softc { 61 device_t dev; 62 struct resource *mem_res; 63}; 64 65static struct ccm_softc *ccm_sc; 66 67static inline uint32_t 68RD4(struct ccm_softc *sc, bus_size_t off) 69{ 70 71 return (bus_read_4(sc->mem_res, off)); 72} 73 74static inline void 75WR4(struct ccm_softc *sc, bus_size_t off, uint32_t val) 76{ 77 78 bus_write_4(sc->mem_res, off, val); 79} 80 81/* 82 * Until we have a fully functional ccm driver which implements the fdt_clock 83 * interface, use the age-old workaround of unconditionally enabling the clocks 84 * for devices we might need to use. The SoC defaults to most clocks enabled, 85 * but the rom boot code and u-boot disable a few of them. We turn on only 86 * what's needed to run the chip plus devices we have drivers for, and turn off 87 * devices we don't yet have drivers for. (Note that USB is not turned on here 88 * because that is one we do when the driver asks for it.) 89 */ 90static void 91ccm_init_gates(struct ccm_softc *sc) 92{ 93 uint32_t reg; 94 95 /* ahpbdma, aipstz 1 & 2 busses */ 96 reg = CCGR0_AIPS_TZ1 | CCGR0_AIPS_TZ2 | CCGR0_ABPHDMA; 97 WR4(sc, CCM_CCGR0, reg); 98 99 /* enet, epit, gpt */ 100 reg = CCGR1_ENET | CCGR1_EPIT1 | CCGR1_GPT; 101 WR4(sc, CCM_CCGR1, reg); 102 103 /* ipmux & ipsync (bridges), iomux, i2c */ 104 reg = CCGR2_I2C1 | CCGR2_I2C2 | CCGR2_I2C3 | CCGR2_IIM | 105 CCGR2_IOMUX_IPT | CCGR2_IPMUX1 | CCGR2_IPMUX2 | CCGR2_IPMUX3 | 106 CCGR2_IPSYNC_IP2APB_TZASC1 | CCGR2_IPSYNC_IP2APB_TZASC2 | 107 CCGR2_IPSYNC_VDOA; 108 WR4(sc, CCM_CCGR2, reg); 109 110 /* DDR memory controller */ 111 reg = CCGR3_OCRAM | CCGR3_MMDC_CORE_IPG | 112 CCGR3_MMDC_CORE_ACLK_FAST | CCGR3_CG11 | CCGR3_CG13; 113 WR4(sc, CCM_CCGR3, reg); 114 115 /* pl301 bus crossbar */ 116 reg = CCGR4_PL301_MX6QFAST1_S133 | 117 CCGR4_PL301_MX6QPER1_BCH | CCGR4_PL301_MX6QPER2_MAIN; 118 WR4(sc, CCM_CCGR4, reg); 119 120 /* uarts, ssi, sdma */ 121 reg = CCGR5_SDMA | CCGR5_SSI1 | CCGR5_SSI2 | CCGR5_SSI3 | 122 CCGR5_UART | CCGR5_UART_SERIAL; 123 WR4(sc, CCM_CCGR5, reg); 124 125 /* usdhc 1-4, usboh3 */ 126 reg = CCGR6_USBOH3 | CCGR6_USDHC1 | CCGR6_USDHC2 | 127 CCGR6_USDHC3 | CCGR6_USDHC4; 128 WR4(sc, CCM_CCGR6, reg); 129} 130 131static int 132ccm_detach(device_t dev) 133{ 134 struct ccm_softc *sc; 135 136 sc = device_get_softc(dev); 137 138 if (sc->mem_res != NULL) 139 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res); 140 141 return (0); 142} 143 144static int 145ccm_attach(device_t dev) 146{ 147 struct ccm_softc *sc; 148 int err, rid; 149 uint32_t reg; 150 151 sc = device_get_softc(dev); 152 err = 0; 153 154 /* Allocate bus_space resources. */ 155 rid = 0; 156 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 157 RF_ACTIVE); 158 if (sc->mem_res == NULL) { 159 device_printf(dev, "Cannot allocate memory resources\n"); 160 err = ENXIO; 161 goto out; 162 } 163 164 ccm_sc = sc; 165 166 /* 167 * Configure the Low Power Mode setting to leave the ARM core power on 168 * when a WFI instruction is executed. This lets the MPCore timers and 169 * GIC continue to run, which is helpful when the only thing that can 170 * wake you up is an MPCore Private Timer interrupt delivered via GIC. 171 * 172 * XXX Based on the docs, setting CCM_CGPR_INT_MEM_CLK_LPM shouldn't be 173 * required when the LPM bits are set to LPM_RUN. But experimentally 174 * I've experienced a fairly rare lockup when not setting it. I was 175 * unable to prove conclusively that the lockup was related to power 176 * management or that this definitively fixes it. Revisit this. 177 */ 178 reg = RD4(sc, CCM_CGPR); 179 reg |= CCM_CGPR_INT_MEM_CLK_LPM; 180 WR4(sc, CCM_CGPR, reg); 181 reg = RD4(sc, CCM_CLPCR); 182 reg = (reg & ~CCM_CLPCR_LPM_MASK) | CCM_CLPCR_LPM_RUN; 183 WR4(sc, CCM_CLPCR, reg); 184 185 ccm_init_gates(sc); 186 187 err = 0; 188 189out: 190 191 if (err != 0) 192 ccm_detach(dev); 193 194 return (err); 195} 196 197static int 198ccm_probe(device_t dev) 199{ 200 201 if (!ofw_bus_status_okay(dev)) 202 return (ENXIO); 203 204 if (ofw_bus_is_compatible(dev, "fsl,imx6q-ccm") == 0) 205 return (ENXIO); 206 207 device_set_desc(dev, "Freescale i.MX6 Clock Control Module"); 208 209 return (BUS_PROBE_DEFAULT); 210} 211 212void 213imx_ccm_ssi_configure(device_t _ssidev) 214{ 215 struct ccm_softc *sc; 216 uint32_t reg; 217 218 sc = ccm_sc; 219 220 /* 221 * Select PLL4 (Audio PLL) clock multiplexer as source. 222 * PLL output frequency = Fref * (DIV_SELECT + NUM/DENOM). 223 */ 224 225 reg = RD4(sc, CCM_CSCMR1); 226 reg &= ~(SSI_CLK_SEL_M << SSI1_CLK_SEL_S); 227 reg |= (SSI_CLK_SEL_PLL4 << SSI1_CLK_SEL_S); 228 reg &= ~(SSI_CLK_SEL_M << SSI2_CLK_SEL_S); 229 reg |= (SSI_CLK_SEL_PLL4 << SSI2_CLK_SEL_S); 230 reg &= ~(SSI_CLK_SEL_M << SSI3_CLK_SEL_S); 231 reg |= (SSI_CLK_SEL_PLL4 << SSI3_CLK_SEL_S); 232 WR4(sc, CCM_CSCMR1, reg); 233 234 /* 235 * Ensure we have set hardware-default values 236 * for pre and post dividers. 237 */ 238 239 /* SSI1 and SSI3 */ 240 reg = RD4(sc, CCM_CS1CDR); 241 /* Divide by 2 */ 242 reg &= ~(SSI_CLK_PODF_MASK << SSI1_CLK_PODF_SHIFT); 243 reg &= ~(SSI_CLK_PODF_MASK << SSI3_CLK_PODF_SHIFT); 244 reg |= (0x1 << SSI1_CLK_PODF_SHIFT); 245 reg |= (0x1 << SSI3_CLK_PODF_SHIFT); 246 /* Divide by 4 */ 247 reg &= ~(SSI_CLK_PRED_MASK << SSI1_CLK_PRED_SHIFT); 248 reg &= ~(SSI_CLK_PRED_MASK << SSI3_CLK_PRED_SHIFT); 249 reg |= (0x3 << SSI1_CLK_PRED_SHIFT); 250 reg |= (0x3 << SSI3_CLK_PRED_SHIFT); 251 WR4(sc, CCM_CS1CDR, reg); 252 253 /* SSI2 */ 254 reg = RD4(sc, CCM_CS2CDR); 255 /* Divide by 2 */ 256 reg &= ~(SSI_CLK_PODF_MASK << SSI2_CLK_PODF_SHIFT); 257 reg |= (0x1 << SSI2_CLK_PODF_SHIFT); 258 /* Divide by 4 */ 259 reg &= ~(SSI_CLK_PRED_MASK << SSI2_CLK_PRED_SHIFT); 260 reg |= (0x3 << SSI2_CLK_PRED_SHIFT); 261 WR4(sc, CCM_CS2CDR, reg); 262} 263 264void 265imx_ccm_usb_enable(device_t _usbdev) 266{ 267 268 /* 269 * For imx6, the USBOH3 clock gate is bits 0-1 of CCGR6, so no need for 270 * shifting and masking here, just set the low-order two bits to ALWAYS. 271 */ 272 WR4(ccm_sc, CCM_CCGR6, RD4(ccm_sc, CCM_CCGR6) | CCGR_CLK_MODE_ALWAYS); 273} 274 275void 276imx_ccm_usbphy_enable(device_t _phydev) 277{ 278 /* 279 * XXX Which unit? 280 * Right now it's not clear how to figure from fdt data which phy unit 281 * we're supposed to operate on. Until this is worked out, just enable 282 * both PHYs. 283 */ 284#if 0 285 int phy_num, regoff; 286 287 phy_num = 0; /* XXX */ 288 289 switch (phy_num) { 290 case 0: 291 regoff = 0; 292 break; 293 case 1: 294 regoff = 0x10; 295 break; 296 default: 297 device_printf(ccm_sc->dev, "Bad PHY number %u,\n", 298 phy_num); 299 return; 300 } 301 302 imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_USB1 + regoff, 303 IMX6_ANALOG_CCM_PLL_USB_ENABLE | 304 IMX6_ANALOG_CCM_PLL_USB_POWER | 305 IMX6_ANALOG_CCM_PLL_USB_EN_USB_CLKS); 306#else 307 imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_USB1 + 0, 308 IMX6_ANALOG_CCM_PLL_USB_ENABLE | 309 IMX6_ANALOG_CCM_PLL_USB_POWER | 310 IMX6_ANALOG_CCM_PLL_USB_EN_USB_CLKS); 311 312 imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_USB1 + 0x10, 313 IMX6_ANALOG_CCM_PLL_USB_ENABLE | 314 IMX6_ANALOG_CCM_PLL_USB_POWER | 315 IMX6_ANALOG_CCM_PLL_USB_EN_USB_CLKS); 316#endif 317} 318 319int 320imx6_ccm_sata_enable(void) 321{ 322 uint32_t v; 323 int timeout; 324 325 /* Un-gate the sata controller. */ 326 WR4(ccm_sc, CCM_CCGR5, RD4(ccm_sc, CCM_CCGR5) | CCGR5_SATA); 327 328 /* Power up the PLL that feeds ENET/SATA/PCI phys, wait for lock. */ 329 v = RD4(ccm_sc, CCM_ANALOG_PLL_ENET); 330 v &= ~CCM_ANALOG_PLL_ENET_POWERDOWN; 331 WR4(ccm_sc, CCM_ANALOG_PLL_ENET, v); 332 333 for (timeout = 100000; timeout > 0; timeout--) { 334 if (RD4(ccm_sc, CCM_ANALOG_PLL_ENET) & 335 CCM_ANALOG_PLL_ENET_LOCK) { 336 break; 337 } 338 } 339 if (timeout <= 0) { 340 return ETIMEDOUT; 341 } 342 343 /* Enable the PLL, and enable its 100mhz output. */ 344 v |= CCM_ANALOG_PLL_ENET_ENABLE; 345 v &= ~CCM_ANALOG_PLL_ENET_BYPASS; 346 WR4(ccm_sc, CCM_ANALOG_PLL_ENET, v); 347 348 v |= CCM_ANALOG_PLL_ENET_ENABLE_100M; 349 WR4(ccm_sc, CCM_ANALOG_PLL_ENET, v); 350 351 return 0; 352} 353 354uint32_t 355imx_ccm_ipg_hz(void) 356{ 357 358 return (66000000); 359} 360 361uint32_t 362imx_ccm_perclk_hz(void) 363{ 364 365 return (66000000); 366} 367 368uint32_t 369imx_ccm_sdhci_hz(void) 370{ 371 372 return (200000000); 373} 374 375uint32_t 376imx_ccm_uart_hz(void) 377{ 378 379 return (80000000); 380} 381 382uint32_t 383imx_ccm_ahb_hz(void) 384{ 385 return (132000000); 386} 387 388void 389imx_ccm_ipu_enable(int ipu) 390{ 391 struct ccm_softc *sc; 392 uint32_t reg; 393 394 sc = ccm_sc; 395 reg = RD4(sc, CCM_CCGR3); 396 if (ipu == 1) 397 reg |= CCGR3_IPU1_IPU | CCGR3_IPU1_DI0; 398 else 399 reg |= CCGR3_IPU2_IPU | CCGR3_IPU2_DI0; 400 WR4(sc, CCM_CCGR3, reg); 401} 402 403void 404imx_ccm_hdmi_enable(void) 405{ 406 struct ccm_softc *sc; 407 uint32_t reg; 408 409 sc = ccm_sc; 410 reg = RD4(sc, CCM_CCGR2); 411 reg |= CCGR2_HDMI_TX | CCGR2_HDMI_TX_ISFR; 412 WR4(sc, CCM_CCGR2, reg); 413 414 /* Set HDMI clock to 280MHz */ 415 reg = RD4(sc, CCM_CHSCCDR); 416 reg &= ~(CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK | 417 CHSCCDR_IPU1_DI0_PODF_MASK | CHSCCDR_IPU1_DI0_CLK_SEL_MASK); 418 reg |= (CHSCCDR_PODF_DIVIDE_BY_3 << CHSCCDR_IPU1_DI0_PODF_SHIFT); 419 reg |= (CHSCCDR_IPU_PRE_CLK_540M_PFD << CHSCCDR_IPU1_DI0_PRE_CLK_SEL_SHIFT); 420 WR4(sc, CCM_CHSCCDR, reg); 421 reg |= (CHSCCDR_CLK_SEL_LDB_DI0 << CHSCCDR_IPU1_DI0_CLK_SEL_SHIFT); 422 WR4(sc, CCM_CHSCCDR, reg); 423} 424 425uint32_t 426imx_ccm_get_cacrr(void) 427{ 428 429 return (RD4(ccm_sc, CCM_CACCR)); 430} 431 432void 433imx_ccm_set_cacrr(uint32_t divisor) 434{ 435 436 WR4(ccm_sc, CCM_CACCR, divisor); 437} 438 439static device_method_t ccm_methods[] = { 440 /* Device interface */ 441 DEVMETHOD(device_probe, ccm_probe), 442 DEVMETHOD(device_attach, ccm_attach), 443 DEVMETHOD(device_detach, ccm_detach), 444 445 DEVMETHOD_END 446}; 447 448static driver_t ccm_driver = { 449 "ccm", 450 ccm_methods, 451 sizeof(struct ccm_softc) 452}; 453 454static devclass_t ccm_devclass; 455 456EARLY_DRIVER_MODULE(ccm, simplebus, ccm_driver, ccm_devclass, 0, 0, 457 BUS_PASS_CPU + BUS_PASS_ORDER_EARLY); 458 459