imx6_ahci.c revision 323468 
1/*-
2 * Copyright (c) 2017 Rogiel Sulzbach <rogiel@allogica.com>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27#include <sys/cdefs.h>
28
29__FBSDID("$FreeBSD: stable/11/sys/arm/freescale/imx/imx6_ahci.c 323468 2017-09-11 22:28:38Z ian $");
30
31#include <sys/param.h>
32#include <sys/systm.h>
33#include <sys/bus.h>
34#include <sys/rman.h>
35#include <sys/kernel.h>
36#include <sys/module.h>
37
38#include <machine/bus.h>
39#include <dev/ofw/ofw_bus.h>
40#include <dev/ofw/ofw_bus_subr.h>
41
42#include <dev/ahci/ahci.h>
43#include <arm/freescale/imx/imx_iomuxreg.h>
44#include <arm/freescale/imx/imx_iomuxvar.h>
45#include <arm/freescale/imx/imx_ccmvar.h>
46
47#define	SATA_TIMER1MS				0x000000e0
48
49#define	SATA_P0PHYCR				0x00000178
50#define	  SATA_P0PHYCR_CR_READ			  (1 << 19)
51#define	  SATA_P0PHYCR_CR_WRITE			  (1 << 18)
52#define	  SATA_P0PHYCR_CR_CAP_DATA		  (1 << 17)
53#define	  SATA_P0PHYCR_CR_CAP_ADDR		  (1 << 16)
54#define	  SATA_P0PHYCR_CR_DATA_IN(v)		  ((v) & 0xffff)
55
56#define	SATA_P0PHYSR				0x0000017c
57#define	  SATA_P0PHYSR_CR_ACK			  (1 << 18)
58#define	  SATA_P0PHYSR_CR_DATA_OUT(v)		  ((v) & 0xffff)
59
60/* phy registers */
61#define	SATA_PHY_CLOCK_RESET			0x7f3f
62#define	  SATA_PHY_CLOCK_RESET_RST		  (1 << 0)
63
64#define	SATA_PHY_LANE0_OUT_STAT			0x2003
65#define	  SATA_PHY_LANE0_OUT_STAT_RX_PLL_STATE	  (1 << 1)
66
67static int
68imx6_ahci_phy_ctrl(struct ahci_controller* sc, uint32_t bitmask, bool on)
69{
70	uint32_t v;
71	int timeout;
72	bool state;
73
74	v = ATA_INL(sc->r_mem, SATA_P0PHYCR);
75	if (on) {
76		v |= bitmask;
77	} else {
78		v &= ~bitmask;
79	}
80	ATA_OUTL(sc->r_mem, SATA_P0PHYCR, v);
81
82	for (timeout = 5000; timeout > 0; --timeout) {
83		v = ATA_INL(sc->r_mem, SATA_P0PHYSR);
84		state = (v & SATA_P0PHYSR_CR_ACK) == SATA_P0PHYSR_CR_ACK;
85		if(state == on) {
86			break;
87		}
88		DELAY(100);
89	}
90
91	if (timeout > 0) {
92		return (0);
93	}
94
95	return (ETIMEDOUT);
96}
97
98static int
99imx6_ahci_phy_addr(struct ahci_controller* sc, uint32_t addr)
100{
101	int error;
102
103	DELAY(100);
104
105	ATA_OUTL(sc->r_mem, SATA_P0PHYCR, addr);
106
107	error = imx6_ahci_phy_ctrl(sc, SATA_P0PHYCR_CR_CAP_ADDR, true);
108	if (error != 0) {
109		device_printf(sc->dev,
110		    "%s: timeout on SATA_P0PHYCR_CR_CAP_ADDR=1\n",
111		    __FUNCTION__);
112		return (error);
113	}
114
115	error = imx6_ahci_phy_ctrl(sc, SATA_P0PHYCR_CR_CAP_ADDR, false);
116	if (error != 0) {
117		device_printf(sc->dev,
118		    "%s: timeout on SATA_P0PHYCR_CR_CAP_ADDR=0\n",
119		    __FUNCTION__);
120		return (error);
121	}
122
123	return (0);
124}
125
126static int
127imx6_ahci_phy_write(struct ahci_controller* sc, uint32_t addr,
128		    uint16_t data)
129{
130	int error;
131
132	error = imx6_ahci_phy_addr(sc, addr);
133	if (error != 0) {
134		device_printf(sc->dev, "%s: error on imx6_ahci_phy_addr\n",
135		    __FUNCTION__);
136		return (error);
137	}
138
139	ATA_OUTL(sc->r_mem, SATA_P0PHYCR, data);
140
141	error = imx6_ahci_phy_ctrl(sc, SATA_P0PHYCR_CR_CAP_DATA, true);
142	if (error != 0) {
143		device_printf(sc->dev,
144		    "%s: error on SATA_P0PHYCR_CR_CAP_DATA=1\n", __FUNCTION__);
145		return (error);
146	}
147	if (imx6_ahci_phy_ctrl(sc, SATA_P0PHYCR_CR_CAP_DATA, false) != 0) {
148		device_printf(sc->dev,
149		    "%s: error on SATA_P0PHYCR_CR_CAP_DATA=0\n", __FUNCTION__);
150		return (error);
151	}
152
153	if ((addr == SATA_PHY_CLOCK_RESET) && data) {
154		/* we can't check ACK after RESET */
155		ATA_OUTL(sc->r_mem, SATA_P0PHYCR,
156		    SATA_P0PHYCR_CR_DATA_IN(data) | SATA_P0PHYCR_CR_WRITE);
157		return (0);
158	}
159
160	error = imx6_ahci_phy_ctrl(sc, SATA_P0PHYCR_CR_WRITE, true);
161	if (error != 0) {
162		device_printf(sc->dev, "%s: error on SATA_P0PHYCR_CR_WRITE=1\n",
163		    __FUNCTION__);
164		return (error);
165	}
166
167	error = imx6_ahci_phy_ctrl(sc, SATA_P0PHYCR_CR_WRITE, false);
168	if (error != 0) {
169		device_printf(sc->dev, "%s: error on SATA_P0PHYCR_CR_WRITE=0\n",
170		    __FUNCTION__);
171		return (error);
172	}
173
174	return (0);
175}
176
177static int
178imx6_ahci_phy_read(struct ahci_controller* sc, uint32_t addr, uint16_t* val)
179{
180	int error;
181	uint32_t v;
182
183	error = imx6_ahci_phy_addr(sc, addr);
184	if (error != 0) {
185		device_printf(sc->dev, "%s: error on imx6_ahci_phy_addr\n",
186		    __FUNCTION__);
187		return (error);
188	}
189
190	error = imx6_ahci_phy_ctrl(sc, SATA_P0PHYCR_CR_READ, true);
191	if (error != 0) {
192		device_printf(sc->dev, "%s: error on SATA_P0PHYCR_CR_READ=1\n",
193		    __FUNCTION__);
194		return (error);
195	}
196
197	v = ATA_INL(sc->r_mem, SATA_P0PHYSR);
198
199	error = imx6_ahci_phy_ctrl(sc, SATA_P0PHYCR_CR_READ, false);
200	if (error != 0) {
201		device_printf(sc->dev, "%s: error on SATA_P0PHYCR_CR_READ=0\n",
202		    __FUNCTION__);
203		return (error);
204	}
205
206	*val = SATA_P0PHYSR_CR_DATA_OUT(v);
207	return (0);
208}
209
210static int
211imx6_ahci_probe(device_t dev)
212{
213
214	if (!ofw_bus_status_okay(dev)) {
215		return (ENXIO);
216	}
217
218	if (!ofw_bus_is_compatible(dev, "fsl,imx6q-ahci")) {
219		return (ENXIO);
220	}
221	device_set_desc(dev, "i.MX6 Integrated AHCI controller");
222
223	return (BUS_PROBE_DEFAULT);
224}
225
226static int
227imx6_ahci_attach(device_t dev)
228{
229	struct ahci_controller* ctlr;
230	uint16_t pllstat;
231	uint32_t v;
232	int error, timeout;
233
234	ctlr = device_get_softc(dev);
235
236	/* Power up the controller and phy. */
237	error = imx6_ccm_sata_enable();
238	if (error != 0) {
239		device_printf(dev, "error enabling controller and phy\n");
240		return (error);
241	}
242
243	ctlr->vendorid = 0;
244	ctlr->deviceid = 0;
245	ctlr->subvendorid = 0;
246	ctlr->subdeviceid = 0;
247	ctlr->numirqs = 1;
248	ctlr->r_rid = 0;
249	if ((ctlr->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
250	    &ctlr->r_rid, RF_ACTIVE)) == NULL) {
251		return (ENXIO);
252	}
253
254	v = imx_iomux_gpr_get(IOMUX_GPR13);
255	/* Clear out existing values; these numbers are bitmasks. */
256	v &= ~(IOMUX_GPR13_SATA_PHY_8(7) 	|
257	       IOMUX_GPR13_SATA_PHY_7(0x1f) 	|
258	       IOMUX_GPR13_SATA_PHY_6(7) 	|
259	       IOMUX_GPR13_SATA_SPEED(1) 	|
260	       IOMUX_GPR13_SATA_PHY_5(1) 	|
261	       IOMUX_GPR13_SATA_PHY_4(7) 	|
262	       IOMUX_GPR13_SATA_PHY_3(0xf) 	|
263	       IOMUX_GPR13_SATA_PHY_2(0x1f) 	|
264	       IOMUX_GPR13_SATA_PHY_1(1) 	|
265	       IOMUX_GPR13_SATA_PHY_0(1));
266	/* setting */
267	v |= IOMUX_GPR13_SATA_PHY_8(5) 		|     /* Rx 3.0db */
268	     IOMUX_GPR13_SATA_PHY_7(0x12) 	|     /* Rx SATA2m */
269	     IOMUX_GPR13_SATA_PHY_6(3) 		|     /* Rx DPLL mode */
270	     IOMUX_GPR13_SATA_SPEED(1) 		|     /* 3.0GHz */
271	     IOMUX_GPR13_SATA_PHY_5(0) 		|     /* SpreadSpectram */
272	     IOMUX_GPR13_SATA_PHY_4(4) 		|     /* Tx Attenuation 9/16 */
273	     IOMUX_GPR13_SATA_PHY_3(0) 		|     /* Tx Boost 0db */
274	     IOMUX_GPR13_SATA_PHY_2(0x11) 	|     /* Tx Level 1.104V */
275	     IOMUX_GPR13_SATA_PHY_1(1);               /* PLL clock enable */
276	imx_iomux_gpr_set(IOMUX_GPR13, v);
277
278	/* phy reset */
279	error = imx6_ahci_phy_write(ctlr, SATA_PHY_CLOCK_RESET,
280	    SATA_PHY_CLOCK_RESET_RST);
281	if (error != 0) {
282		device_printf(dev, "cannot reset PHY\n");
283		goto fail;
284	}
285
286	for (timeout = 50; timeout > 0; --timeout) {
287		DELAY(100);
288		error = imx6_ahci_phy_read(ctlr, SATA_PHY_LANE0_OUT_STAT,
289		    &pllstat);
290		if (error != 0) {
291			device_printf(dev, "cannot read LANE0 status\n");
292			goto fail;
293		}
294		if (pllstat & SATA_PHY_LANE0_OUT_STAT_RX_PLL_STATE) {
295			break;
296		}
297	}
298	if (timeout <= 0) {
299		device_printf(dev, "time out reading LANE0 status\n");
300		error = ETIMEDOUT;
301		goto fail;
302	}
303
304	/* Support Staggered Spin-up */
305	v = ATA_INL(ctlr->r_mem, AHCI_CAP);
306	ATA_OUTL(ctlr->r_mem, AHCI_CAP, v | AHCI_CAP_SSS);
307
308	/* Ports Implemented. must set 1 */
309	v = ATA_INL(ctlr->r_mem, AHCI_PI);
310	ATA_OUTL(ctlr->r_mem, AHCI_PI, v | (1 << 0));
311
312	/* set 1ms-timer = AHB clock / 1000 */
313	ATA_OUTL(ctlr->r_mem, SATA_TIMER1MS,
314		 imx_ccm_ahb_hz() / 1000);
315
316	/*
317	 * Note: ahci_attach will release ctlr->r_mem on errors automatically
318	 */
319	return (ahci_attach(dev));
320
321fail:
322	bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem);
323	return (error);
324}
325
326static int
327imx6_ahci_detach(device_t dev)
328{
329
330	return (ahci_detach(dev));
331}
332
333devclass_t ahci_devclass;
334
335static device_method_t imx6_ahci_ata_methods[] = {
336	/* device probe, attach and detach methods */
337	DEVMETHOD(device_probe,  imx6_ahci_probe),
338	DEVMETHOD(device_attach, imx6_ahci_attach),
339	DEVMETHOD(device_detach, imx6_ahci_detach),
340
341	/* ahci bus methods */
342	DEVMETHOD(bus_print_child,        ahci_print_child),
343	DEVMETHOD(bus_alloc_resource,     ahci_alloc_resource),
344	DEVMETHOD(bus_release_resource,   ahci_release_resource),
345	DEVMETHOD(bus_setup_intr,         ahci_setup_intr),
346	DEVMETHOD(bus_teardown_intr,      ahci_teardown_intr),
347	DEVMETHOD(bus_child_location_str, ahci_child_location_str),
348
349	DEVMETHOD_END
350};
351
352static driver_t ahci_ata_driver = {
353	"ahci",
354	imx6_ahci_ata_methods,
355	sizeof(struct ahci_controller)
356};
357
358DRIVER_MODULE(ahci, simplebus, ahci_ata_driver, ahci_devclass, 0, 0);
359