imx51_sdmareg.h revision 330897 
1/*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2012, 2013 The FreeBSD Foundation
5 * All rights reserved.
6 *
7 * This software was developed by Oleksandr Rybalko under sponsorship
8 * from the FreeBSD Foundation.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1.	Redistributions of source code must retain the above copyright
14 *	notice, this list of conditions and the following disclaimer.
15 * 2.	Redistributions in binary form must reproduce the above copyright
16 *	notice, this list of conditions and the following disclaimer in the
17 *	documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 *
31 * $FreeBSD: stable/11/sys/arm/freescale/imx/imx51_sdmareg.h 330897 2018-03-14 03:19:51Z eadler $
32 */
33
34/* Internal Registers definition for Freescale i.MX515 SDMA Core */
35
36/* SDMA Core Instruction Memory Space */
37#define	SDMA_IBUS_ROM_ADDR_BASE	0x0000
38#define	SDMA_IBUS_ROM_ADDR_SIZE	0x07ff
39#define	SDMA_IBUS_RAM_ADDR_BASE	0x1000
40#define	SDMA_IBUS_RAM_ADDR_SIZE	0x1fff
41
42/* SDMA Core Internal Registers */
43#define	SDMA_MC0PTR	0x7000 /* AP (MCU) Channel 0 Pointer R */
44
45#define	SDMA_CCPTR	0x7002 /* Current Channel Pointer R */
46#define		SDMA_ECTL_CCPTR_MASK	0x0000ffff
47#define		SDMA_ECTL_CCPTR_SHIFT	0
48
49#define	SDMA_CCR	0x7003 /* Current Channel Register R */
50#define		SDMA_ECTL_CCR_MASK	0x0000001f
51#define		SDMA_ECTL_CCR_SHIFT	0
52
53#define	SDMA_NCR	0x7004 /* Highest Pending Channel Register R */
54#define		SDMA_ECTL_NCR_MASK	0x0000001f
55#define		SDMA_ECTL_NCR_SHIFT	0
56
57#define	SDMA_EVENTS	0x7005 /* External DMA Requests Mirror R */
58
59#define	SDMA_CCPRI	0x7006 /* Current Channel Priority R */
60#define		SDMA_ECTL_CCPRI_MASK	0x00000007
61#define		SDMA_ECTL_CCPRI_SHIFT	0
62
63#define	SDMA_NCPRI	0x7007 /* Next Channel Priority R */
64#define		SDMA_ECTL_NCPRI_MASK	0x00000007
65#define		SDMA_ECTL_NCPRI_SHIFT	0
66
67#define	SDMA_ECOUNT	0x7009 /* OnCE Event Cell Counter R/W */
68#define		SDMA_ECTL_ECOUNT_MASK	0x0000ffff
69#define		SDMA_ECTL_ECOUNT_SHIFT	0
70
71#define	SDMA_ECTL	0x700A /* OnCE Event Cell Control Register R/W */
72#define		SDMA_ECTL_EN		(1 << 13)
73#define		SDMA_ECTL_CNT		(1 << 12)
74#define		SDMA_ECTL_ECTC_MASK	0x00000c00
75#define		SDMA_ECTL_ECTC_SHIFT	10
76#define		SDMA_ECTL_DTC_MASK	0x00000300
77#define		SDMA_ECTL_DTC_SHIFT	8
78#define		SDMA_ECTL_ATC_MASK	0x000000c0
79#define		SDMA_ECTL_ATC_SHIFT	6
80#define		SDMA_ECTL_ABTC_MASK	0x00000030
81#define		SDMA_ECTL_ABTC_SHIFT	4
82#define		SDMA_ECTL_AATC_MASK	0x0000000c
83#define		SDMA_ECTL_AATC_SHIFT	2
84#define		SDMA_ECTL_ATS_MASK	0x00000003
85#define		SDMA_ECTL_ATS_SHIFT	0
86
87#define	SDMA_EAA	0x700B /* OnCE Event Address Register A R/W */
88#define		SDMA_ECTL_EAA_MASK	0x0000ffff
89#define		SDMA_ECTL_EAA_SHIFT	0
90
91#define	SDMA_EAB	0x700C /* OnCE Event Cell Address Register B R/W */
92#define		SDMA_ECTL_EAB_MASK	0x0000ffff
93#define		SDMA_ECTL_EAB_SHIFT	0
94
95#define	SDMA_EAM	0x700D /* OnCE Event Cell Address Mask R/W */
96#define		SDMA_ECTL_EAM_MASK	0x0000ffff
97#define		SDMA_ECTL_EAM_SHIFT	0
98
99#define	SDMA_ED		0x700E /* OnCE Event Cell Data Register R/W */
100#define	SDMA_EDM	0x700F /* OnCE Event Cell Data Mask R/W */
101#define	SDMA_RTB	0x7018 /* OnCE Real-Time Buffer R/W */
102
103#define	SDMA_TB		0x7019 /* OnCE Trace Buffer R */
104#define		SDMA_TB_TBF		(1 << 28)
105#define		SDMA_TB_TADDR_MASK	0x0fffc000
106#define		SDMA_TB_TADDR_SHIFT	14
107#define		SDMA_TB_CHFADDR_MASK	0x00003fff
108#define		SDMA_TB_CHFADDR_SHIFT	0
109
110#define	SDMA_OSTAT	0x701A /* OnCE Status R */
111#define		SDMA_OSTAT_PST_MASK	0x0000f000
112#define		SDMA_OSTAT_PST_SHIFT	12
113#define		SDMA_OSTAT_RCV		(1 << 11)
114#define		SDMA_OSTAT_EDR		(1 << 10)
115#define		SDMA_OSTAT_ODR		(1 << 9)
116#define		SDMA_OSTAT_SWB		(1 << 8)
117#define		SDMA_OSTAT_MST		(1 << 7)
118#define		SDMA_OSTAT_ECDR_MASK	0x00000007
119#define		SDMA_OSTAT_ECDR_SHIFT	0
120
121#define	SDMA_MCHN0ADDR	0x701C /* Channel 0 Boot Address R */
122#define		SDMA_MCHN0ADDR_SMS_Z	(1 << 14)
123#define		SDMA_MCHN0ADDR_CHN0ADDR_MASK 0x00003fff
124#define		SDMA_MCHN0ADDR_CHN0ADDR_SHIFT 0
125
126#define	SDMA_MODE	0x701D /* Mode Status Register R */
127#define		SDMA_MODE_DSPCtrl	(1 << 3)
128#define		SDMA_MODE_AP_END	(1 << 0)
129
130#define	SDMA_LOCK	0x701E /* Lock Status Register R */
131#define		SDMA_LOCK_LOCK		(1 << 0)
132
133#define	SDMA_EVENTS2	0x701F /* External DMA Requests Mirror #2 R */
134
135#define	SDMA_HE		0x7020 /* AP Enable Register R */
136#define	SDMA_PRIV	0x7022 /* Current Channel BP Privilege Register R */
137#define		SDMA_PRIV_BPPRIV	(1 << 0)
138#define	SDMA_PRF_CNT	0x7023 /* Profile Free Running Register R/W */
139#define		SDMA_PRF_CNT_SEL_MASK	0xc0000000
140#define		SDMA_PRF_CNT_SEL_SHIFT	30
141#define		SDMA_PRF_CNT_EN		(1 << 29)
142#define		SDMA_PRF_CNT_OFL	(1 << 22)
143#define		SDMA_PRF_CNT_COUNTER_MASK 0x003fffff
144#define		SDMA_PRF_CNT_COUNTER_SHIFT 0
145