bcm2836_mp.c revision 323471 
1/*-
2 * Copyright (C) 2015 Daisuke Aoyama <aoyama@peach.ne.jp>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 *
29 */
30
31#include <sys/cdefs.h>
32__FBSDID("$FreeBSD: stable/11/sys/arm/broadcom/bcm2835/bcm2836_mp.c 323471 2017-09-11 22:35:20Z ian $");
33
34#include <sys/param.h>
35#include <sys/systm.h>
36#include <sys/kernel.h>
37#include <sys/bus.h>
38#include <sys/smp.h>
39
40#include <vm/vm.h>
41#include <vm/pmap.h>
42
43#include <machine/cpu.h>
44#include <machine/smp.h>
45#include <machine/bus.h>
46#include <machine/fdt.h>
47#include <machine/intr.h>
48
49#ifdef DEBUG
50#define	DPRINTF(fmt, ...) do {			\
51	printf("%s:%u: ", __func__, __LINE__);	\
52	printf(fmt, ##__VA_ARGS__);		\
53} while (0)
54#else
55#define	DPRINTF(fmt, ...)
56#endif
57
58#define	ARM_LOCAL_BASE		0x40000000
59#define	ARM_LOCAL_SIZE		0x00001000
60
61/* mailbox registers */
62#define	MBOXINTRCTRL_CORE(n)	(0x00000050 + (0x04 * (n)))
63#define	MBOX0SET_CORE(n)	(0x00000080 + (0x10 * (n)))
64#define	MBOX1SET_CORE(n)	(0x00000084 + (0x10 * (n)))
65#define	MBOX2SET_CORE(n)	(0x00000088 + (0x10 * (n)))
66#define	MBOX3SET_CORE(n)	(0x0000008C + (0x10 * (n)))
67#define	MBOX0CLR_CORE(n)	(0x000000C0 + (0x10 * (n)))
68#define	MBOX1CLR_CORE(n)	(0x000000C4 + (0x10 * (n)))
69#define	MBOX2CLR_CORE(n)	(0x000000C8 + (0x10 * (n)))
70#define	MBOX3CLR_CORE(n)	(0x000000CC + (0x10 * (n)))
71
72static bus_space_handle_t bs_periph;
73
74#define	BSRD4(addr) \
75	bus_space_read_4(fdtbus_bs_tag, bs_periph, (addr))
76#define	BSWR4(addr, val) \
77	bus_space_write_4(fdtbus_bs_tag, bs_periph, (addr), (val))
78
79void
80platform_mp_setmaxid(void)
81{
82
83	DPRINTF("platform_mp_setmaxid\n");
84	if (mp_ncpus != 0)
85		return;
86
87	mp_ncpus = 4;
88	mp_maxid = mp_ncpus - 1;
89	DPRINTF("mp_maxid=%d\n", mp_maxid);
90}
91
92void
93platform_mp_start_ap(void)
94{
95	uint32_t val;
96	int i, retry;
97
98	DPRINTF("platform_mp_start_ap\n");
99
100	/* initialize */
101	if (bus_space_map(fdtbus_bs_tag, ARM_LOCAL_BASE, ARM_LOCAL_SIZE,
102	    0, &bs_periph) != 0)
103		panic("can't map local peripheral\n");
104	for (i = 0; i < mp_ncpus; i++) {
105		/* clear mailbox 0/3 */
106		BSWR4(MBOX0CLR_CORE(i), 0xffffffff);
107		BSWR4(MBOX3CLR_CORE(i), 0xffffffff);
108	}
109	wmb();
110	dcache_wbinv_poc_all();
111
112	/* boot secondary CPUs */
113	for (i = 1; i < mp_ncpus; i++) {
114		/* set entry point to mailbox 3 */
115		BSWR4(MBOX3SET_CORE(i),
116		    (uint32_t)pmap_kextract((vm_offset_t)mpentry));
117		/* Firmware put cores in WFE state, need SEV to wake up. */
118		dsb();
119		sev();
120
121		/* wait for bootup */
122		retry = 1000;
123		do {
124			/* check entry point */
125			val = BSRD4(MBOX3CLR_CORE(i));
126			if (val == 0)
127				break;
128			DELAY(100);
129			retry--;
130			if (retry <= 0) {
131				printf("can't start for CPU%d\n", i);
132				break;
133			}
134		} while (1);
135
136		/* dsb and sev */
137		dsb();
138		sev();
139
140		/* recode AP in CPU map */
141		CPU_SET(i, &all_cpus);
142	}
143}
144
145#ifndef INTRNG
146void
147pic_ipi_send(cpuset_t cpus, u_int ipi)
148{
149	int i;
150
151	dsb();
152	for (i = 0; i < mp_ncpus; i++) {
153		if (CPU_ISSET(i, &cpus))
154			BSWR4(MBOX0SET_CORE(i), 1 << ipi);
155	}
156	wmb();
157}
158
159int
160pic_ipi_read(int i)
161{
162	uint32_t val;
163	int cpu, ipi;
164
165	cpu = PCPU_GET(cpuid);
166	dsb();
167	if (i != -1) {
168		val = BSRD4(MBOX0CLR_CORE(cpu));
169		if (val == 0)
170			return (0);
171		ipi = ffs(val) - 1;
172		BSWR4(MBOX0CLR_CORE(cpu), 1 << ipi);
173		dsb();
174		return (ipi);
175	}
176	return (0x3ff);
177}
178
179void
180pic_ipi_clear(int ipi)
181{
182}
183#endif
184