bcm2835_spi.c revision 307575
1/*- 2 * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org> 3 * Copyright (c) 2013 Luiz Otavio O Souza <loos@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 */ 28#include <sys/cdefs.h> 29__FBSDID("$FreeBSD: stable/11/sys/arm/broadcom/bcm2835/bcm2835_spi.c 307575 2016-10-18 19:15:43Z gonzo $"); 30 31#include <sys/param.h> 32#include <sys/systm.h> 33#include <sys/bus.h> 34 35#include <sys/kernel.h> 36#include <sys/module.h> 37#include <sys/rman.h> 38#include <sys/lock.h> 39#include <sys/mutex.h> 40#include <sys/sysctl.h> 41 42#include <machine/bus.h> 43#include <machine/cpu.h> 44#include <machine/cpufunc.h> 45#include <machine/resource.h> 46#include <machine/intr.h> 47 48#include <dev/fdt/fdt_common.h> 49#include <dev/ofw/ofw_bus.h> 50#include <dev/ofw/ofw_bus_subr.h> 51 52#include <dev/spibus/spi.h> 53#include <dev/spibus/spibusvar.h> 54 55#include <arm/broadcom/bcm2835/bcm2835_gpio.h> 56#include <arm/broadcom/bcm2835/bcm2835_spireg.h> 57#include <arm/broadcom/bcm2835/bcm2835_spivar.h> 58 59#include "spibus_if.h" 60 61static struct ofw_compat_data compat_data[] = { 62 {"broadcom,bcm2835-spi", 1}, 63 {"brcm,bcm2835-spi", 1}, 64 {NULL, 0} 65}; 66 67static void bcm_spi_intr(void *); 68 69#ifdef BCM_SPI_DEBUG 70static void 71bcm_spi_printr(device_t dev) 72{ 73 struct bcm_spi_softc *sc; 74 uint32_t reg; 75 76 sc = device_get_softc(dev); 77 reg = BCM_SPI_READ(sc, SPI_CS); 78 device_printf(dev, "CS=%b\n", reg, 79 "\20\1CS0\2CS1\3CPHA\4CPOL\7CSPOL" 80 "\10TA\11DMAEN\12INTD\13INTR\14ADCS\15REN\16LEN" 81 "\21DONE\22RXD\23TXD\24RXR\25RXF\26CSPOL0\27CSPOL1" 82 "\30CSPOL2\31DMA_LEN\32LEN_LONG"); 83 reg = BCM_SPI_READ(sc, SPI_CLK) & SPI_CLK_MASK; 84 if (reg % 2) 85 reg--; 86 if (reg == 0) 87 reg = 65536; 88 device_printf(dev, "CLK=%uMhz/%d=%luhz\n", 89 SPI_CORE_CLK / 1000000, reg, SPI_CORE_CLK / reg); 90 reg = BCM_SPI_READ(sc, SPI_DLEN) & SPI_DLEN_MASK; 91 device_printf(dev, "DLEN=%d\n", reg); 92 reg = BCM_SPI_READ(sc, SPI_LTOH) & SPI_LTOH_MASK; 93 device_printf(dev, "LTOH=%d\n", reg); 94 reg = BCM_SPI_READ(sc, SPI_DC); 95 device_printf(dev, "DC=RPANIC=%#x RDREQ=%#x TPANIC=%#x TDREQ=%#x\n", 96 (reg & SPI_DC_RPANIC_MASK) >> SPI_DC_RPANIC_SHIFT, 97 (reg & SPI_DC_RDREQ_MASK) >> SPI_DC_RDREQ_SHIFT, 98 (reg & SPI_DC_TPANIC_MASK) >> SPI_DC_TPANIC_SHIFT, 99 (reg & SPI_DC_TDREQ_MASK) >> SPI_DC_TDREQ_SHIFT); 100} 101#endif 102 103static void 104bcm_spi_modifyreg(struct bcm_spi_softc *sc, uint32_t off, uint32_t mask, 105 uint32_t value) 106{ 107 uint32_t reg; 108 109 mtx_assert(&sc->sc_mtx, MA_OWNED); 110 reg = BCM_SPI_READ(sc, off); 111 reg &= ~mask; 112 reg |= value; 113 BCM_SPI_WRITE(sc, off, reg); 114} 115 116static int 117bcm_spi_clock_proc(SYSCTL_HANDLER_ARGS) 118{ 119 struct bcm_spi_softc *sc; 120 uint32_t clk; 121 int error; 122 123 sc = (struct bcm_spi_softc *)arg1; 124 125 BCM_SPI_LOCK(sc); 126 clk = BCM_SPI_READ(sc, SPI_CLK); 127 BCM_SPI_UNLOCK(sc); 128 clk &= 0xffff; 129 if (clk == 0) 130 clk = 65536; 131 clk = SPI_CORE_CLK / clk; 132 133 error = sysctl_handle_int(oidp, &clk, sizeof(clk), req); 134 if (error != 0 || req->newptr == NULL) 135 return (error); 136 137 clk = SPI_CORE_CLK / clk; 138 if (clk <= 1) 139 clk = 2; 140 else if (clk % 2) 141 clk--; 142 if (clk > 0xffff) 143 clk = 0; 144 BCM_SPI_LOCK(sc); 145 BCM_SPI_WRITE(sc, SPI_CLK, clk); 146 BCM_SPI_UNLOCK(sc); 147 148 return (0); 149} 150 151static int 152bcm_spi_cs_bit_proc(SYSCTL_HANDLER_ARGS, uint32_t bit) 153{ 154 struct bcm_spi_softc *sc; 155 uint32_t reg; 156 int error; 157 158 sc = (struct bcm_spi_softc *)arg1; 159 BCM_SPI_LOCK(sc); 160 reg = BCM_SPI_READ(sc, SPI_CS); 161 BCM_SPI_UNLOCK(sc); 162 reg = (reg & bit) ? 1 : 0; 163 164 error = sysctl_handle_int(oidp, ®, sizeof(reg), req); 165 if (error != 0 || req->newptr == NULL) 166 return (error); 167 168 if (reg) 169 reg = bit; 170 BCM_SPI_LOCK(sc); 171 bcm_spi_modifyreg(sc, SPI_CS, bit, reg); 172 BCM_SPI_UNLOCK(sc); 173 174 return (0); 175} 176 177static int 178bcm_spi_cpol_proc(SYSCTL_HANDLER_ARGS) 179{ 180 181 return (bcm_spi_cs_bit_proc(oidp, arg1, arg2, req, SPI_CS_CPOL)); 182} 183 184static int 185bcm_spi_cpha_proc(SYSCTL_HANDLER_ARGS) 186{ 187 188 return (bcm_spi_cs_bit_proc(oidp, arg1, arg2, req, SPI_CS_CPHA)); 189} 190 191static int 192bcm_spi_cspol0_proc(SYSCTL_HANDLER_ARGS) 193{ 194 195 return (bcm_spi_cs_bit_proc(oidp, arg1, arg2, req, SPI_CS_CSPOL0)); 196} 197 198static int 199bcm_spi_cspol1_proc(SYSCTL_HANDLER_ARGS) 200{ 201 202 return (bcm_spi_cs_bit_proc(oidp, arg1, arg2, req, SPI_CS_CSPOL1)); 203} 204 205static void 206bcm_spi_sysctl_init(struct bcm_spi_softc *sc) 207{ 208 struct sysctl_ctx_list *ctx; 209 struct sysctl_oid *tree_node; 210 struct sysctl_oid_list *tree; 211 212 /* 213 * Add system sysctl tree/handlers. 214 */ 215 ctx = device_get_sysctl_ctx(sc->sc_dev); 216 tree_node = device_get_sysctl_tree(sc->sc_dev); 217 tree = SYSCTL_CHILDREN(tree_node); 218 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "clock", 219 CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc), 220 bcm_spi_clock_proc, "IU", "SPI BUS clock frequency"); 221 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "cpol", 222 CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc), 223 bcm_spi_cpol_proc, "IU", "SPI BUS clock polarity"); 224 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "cpha", 225 CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc), 226 bcm_spi_cpha_proc, "IU", "SPI BUS clock phase"); 227 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "cspol0", 228 CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc), 229 bcm_spi_cspol0_proc, "IU", "SPI BUS chip select 0 polarity"); 230 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "cspol1", 231 CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc), 232 bcm_spi_cspol1_proc, "IU", "SPI BUS chip select 1 polarity"); 233} 234 235static int 236bcm_spi_probe(device_t dev) 237{ 238 239 if (!ofw_bus_status_okay(dev)) 240 return (ENXIO); 241 242 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 243 return (ENXIO); 244 245 device_set_desc(dev, "BCM2708/2835 SPI controller"); 246 247 return (BUS_PROBE_DEFAULT); 248} 249 250static int 251bcm_spi_attach(device_t dev) 252{ 253 struct bcm_spi_softc *sc; 254 device_t gpio; 255 int i, rid; 256 257 if (device_get_unit(dev) != 0) { 258 device_printf(dev, "only one SPI controller supported\n"); 259 return (ENXIO); 260 } 261 262 sc = device_get_softc(dev); 263 sc->sc_dev = dev; 264 265 /* Configure the GPIO pins to ALT0 function to enable SPI the pins. */ 266 gpio = devclass_get_device(devclass_find("gpio"), 0); 267 if (!gpio) { 268 device_printf(dev, "cannot find gpio0\n"); 269 return (ENXIO); 270 } 271 for (i = 0; i < nitems(bcm_spi_pins); i++) 272 bcm_gpio_set_alternate(gpio, bcm_spi_pins[i], BCM_GPIO_ALT0); 273 274 rid = 0; 275 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 276 RF_ACTIVE); 277 if (!sc->sc_mem_res) { 278 device_printf(dev, "cannot allocate memory window\n"); 279 return (ENXIO); 280 } 281 282 sc->sc_bst = rman_get_bustag(sc->sc_mem_res); 283 sc->sc_bsh = rman_get_bushandle(sc->sc_mem_res); 284 285 rid = 0; 286 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 287 RF_ACTIVE); 288 if (!sc->sc_irq_res) { 289 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 290 device_printf(dev, "cannot allocate interrupt\n"); 291 return (ENXIO); 292 } 293 294 /* Hook up our interrupt handler. */ 295 if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 296 NULL, bcm_spi_intr, sc, &sc->sc_intrhand)) { 297 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); 298 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 299 device_printf(dev, "cannot setup the interrupt handler\n"); 300 return (ENXIO); 301 } 302 303 mtx_init(&sc->sc_mtx, "bcm_spi", NULL, MTX_DEF); 304 305 /* Add sysctl nodes. */ 306 bcm_spi_sysctl_init(sc); 307 308#ifdef BCM_SPI_DEBUG 309 bcm_spi_printr(dev); 310#endif 311 312 /* 313 * Enable the SPI controller. Clear the rx and tx FIFO. 314 * Defaults to SPI mode 0. 315 */ 316 BCM_SPI_WRITE(sc, SPI_CS, SPI_CS_CLEAR_RXFIFO | SPI_CS_CLEAR_TXFIFO); 317 318 /* Set the SPI clock to 500Khz. */ 319 BCM_SPI_WRITE(sc, SPI_CLK, SPI_CORE_CLK / 500000); 320 321#ifdef BCM_SPI_DEBUG 322 bcm_spi_printr(dev); 323#endif 324 325 device_add_child(dev, "spibus", -1); 326 327 return (bus_generic_attach(dev)); 328} 329 330static int 331bcm_spi_detach(device_t dev) 332{ 333 struct bcm_spi_softc *sc; 334 335 bus_generic_detach(dev); 336 337 sc = device_get_softc(dev); 338 mtx_destroy(&sc->sc_mtx); 339 if (sc->sc_intrhand) 340 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intrhand); 341 if (sc->sc_irq_res) 342 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); 343 if (sc->sc_mem_res) 344 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 345 346 return (0); 347} 348 349static void 350bcm_spi_fill_fifo(struct bcm_spi_softc *sc) 351{ 352 struct spi_command *cmd; 353 uint32_t cs, written; 354 uint8_t *data; 355 356 cmd = sc->sc_cmd; 357 cs = BCM_SPI_READ(sc, SPI_CS) & (SPI_CS_TA | SPI_CS_TXD); 358 while (sc->sc_written < sc->sc_len && 359 cs == (SPI_CS_TA | SPI_CS_TXD)) { 360 data = (uint8_t *)cmd->tx_cmd; 361 written = sc->sc_written++; 362 if (written >= cmd->tx_cmd_sz) { 363 data = (uint8_t *)cmd->tx_data; 364 written -= cmd->tx_cmd_sz; 365 } 366 BCM_SPI_WRITE(sc, SPI_FIFO, data[written]); 367 cs = BCM_SPI_READ(sc, SPI_CS) & (SPI_CS_TA | SPI_CS_TXD); 368 } 369} 370 371static void 372bcm_spi_drain_fifo(struct bcm_spi_softc *sc) 373{ 374 struct spi_command *cmd; 375 uint32_t cs, read; 376 uint8_t *data; 377 378 cmd = sc->sc_cmd; 379 cs = BCM_SPI_READ(sc, SPI_CS) & SPI_CS_RXD; 380 while (sc->sc_read < sc->sc_len && cs == SPI_CS_RXD) { 381 data = (uint8_t *)cmd->rx_cmd; 382 read = sc->sc_read++; 383 if (read >= cmd->rx_cmd_sz) { 384 data = (uint8_t *)cmd->rx_data; 385 read -= cmd->rx_cmd_sz; 386 } 387 data[read] = BCM_SPI_READ(sc, SPI_FIFO) & 0xff; 388 cs = BCM_SPI_READ(sc, SPI_CS) & SPI_CS_RXD; 389 } 390} 391 392static void 393bcm_spi_intr(void *arg) 394{ 395 struct bcm_spi_softc *sc; 396 397 sc = (struct bcm_spi_softc *)arg; 398 BCM_SPI_LOCK(sc); 399 400 /* Filter stray interrupts. */ 401 if ((sc->sc_flags & BCM_SPI_BUSY) == 0) { 402 BCM_SPI_UNLOCK(sc); 403 return; 404 } 405 406 /* TX - Fill up the FIFO. */ 407 bcm_spi_fill_fifo(sc); 408 409 /* RX - Drain the FIFO. */ 410 bcm_spi_drain_fifo(sc); 411 412 /* Check for end of transfer. */ 413 if (sc->sc_written == sc->sc_len && sc->sc_read == sc->sc_len) { 414 /* Disable interrupts and the SPI engine. */ 415 bcm_spi_modifyreg(sc, SPI_CS, 416 SPI_CS_TA | SPI_CS_INTR | SPI_CS_INTD, 0); 417 wakeup(sc->sc_dev); 418 } 419 420 BCM_SPI_UNLOCK(sc); 421} 422 423static int 424bcm_spi_transfer(device_t dev, device_t child, struct spi_command *cmd) 425{ 426 struct bcm_spi_softc *sc; 427 int cs, err; 428 429 sc = device_get_softc(dev); 430 431 KASSERT(cmd->tx_cmd_sz == cmd->rx_cmd_sz, 432 ("TX/RX command sizes should be equal")); 433 KASSERT(cmd->tx_data_sz == cmd->rx_data_sz, 434 ("TX/RX data sizes should be equal")); 435 436 /* Get the proper chip select for this child. */ 437 spibus_get_cs(child, &cs); 438 if (cs < 0 || cs > 2) { 439 device_printf(dev, 440 "Invalid chip select %d requested by %s\n", cs, 441 device_get_nameunit(child)); 442 return (EINVAL); 443 } 444 445 BCM_SPI_LOCK(sc); 446 447 /* If the controller is in use wait until it is available. */ 448 while (sc->sc_flags & BCM_SPI_BUSY) 449 mtx_sleep(dev, &sc->sc_mtx, 0, "bcm_spi", 0); 450 451 /* Now we have control over SPI controller. */ 452 sc->sc_flags = BCM_SPI_BUSY; 453 454 /* Clear the FIFO. */ 455 bcm_spi_modifyreg(sc, SPI_CS, 456 SPI_CS_CLEAR_RXFIFO | SPI_CS_CLEAR_TXFIFO, 457 SPI_CS_CLEAR_RXFIFO | SPI_CS_CLEAR_TXFIFO); 458 459 /* Save a pointer to the SPI command. */ 460 sc->sc_cmd = cmd; 461 sc->sc_read = 0; 462 sc->sc_written = 0; 463 sc->sc_len = cmd->tx_cmd_sz + cmd->tx_data_sz; 464 465 /* 466 * Set the CS for this transaction, enable interrupts and announce 467 * we're ready to tx. This will kick off the first interrupt. 468 */ 469 bcm_spi_modifyreg(sc, SPI_CS, 470 SPI_CS_MASK | SPI_CS_TA | SPI_CS_INTR | SPI_CS_INTD, 471 cs | SPI_CS_TA | SPI_CS_INTR | SPI_CS_INTD); 472 473 /* Wait for the transaction to complete. */ 474 err = mtx_sleep(dev, &sc->sc_mtx, 0, "bcm_spi", hz * 2); 475 476 /* Make sure the SPI engine and interrupts are disabled. */ 477 bcm_spi_modifyreg(sc, SPI_CS, SPI_CS_TA | SPI_CS_INTR | SPI_CS_INTD, 0); 478 479 /* Release the controller and wakeup the next thread waiting for it. */ 480 sc->sc_flags = 0; 481 wakeup_one(dev); 482 BCM_SPI_UNLOCK(sc); 483 484 /* 485 * Check for transfer timeout. The SPI controller doesn't 486 * return errors. 487 */ 488 if (err == EWOULDBLOCK) { 489 device_printf(sc->sc_dev, "SPI error\n"); 490 err = EIO; 491 } 492 493 return (err); 494} 495 496static phandle_t 497bcm_spi_get_node(device_t bus, device_t dev) 498{ 499 500 /* We only have one child, the SPI bus, which needs our own node. */ 501 return (ofw_bus_get_node(bus)); 502} 503 504static device_method_t bcm_spi_methods[] = { 505 /* Device interface */ 506 DEVMETHOD(device_probe, bcm_spi_probe), 507 DEVMETHOD(device_attach, bcm_spi_attach), 508 DEVMETHOD(device_detach, bcm_spi_detach), 509 510 /* SPI interface */ 511 DEVMETHOD(spibus_transfer, bcm_spi_transfer), 512 513 /* ofw_bus interface */ 514 DEVMETHOD(ofw_bus_get_node, bcm_spi_get_node), 515 516 DEVMETHOD_END 517}; 518 519static devclass_t bcm_spi_devclass; 520 521static driver_t bcm_spi_driver = { 522 "spi", 523 bcm_spi_methods, 524 sizeof(struct bcm_spi_softc), 525}; 526 527DRIVER_MODULE(bcm2835_spi, simplebus, bcm_spi_driver, bcm_spi_devclass, 0, 0); 528