bcm2835_bsc.c revision 330897
11553Srgrimes/*- 274532Sru * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 31553Srgrimes * 41553Srgrimes * Copyright (c) 2001 Tsubai Masanari. 580029Sobrien * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org> 674816Sru * Copyright (c) 2013 Luiz Otavio O Souza <loos@freebsd.org> 71553Srgrimes * Copyright (c) 2017 Ian Lepore <ian@freebsd.org> 81553Srgrimes * All rights reserved. 9207736Smckusick * 10207736Smckusick * Redistribution and use in source and binary forms, with or without 11207736Smckusick * modification, are permitted provided that the following conditions 121553Srgrimes * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 */ 32#include <sys/cdefs.h> 33__FBSDID("$FreeBSD: stable/11/sys/arm/broadcom/bcm2835/bcm2835_bsc.c 330897 2018-03-14 03:19:51Z eadler $"); 34 35/* 36 * Driver for bcm2835 i2c-compatible two-wire bus, named 'BSC' on this SoC. 37 * 38 * This controller can only perform complete transfers, it does not provide 39 * low-level control over sending start/repeat-start/stop sequences on the bus. 40 * In addition, bugs in the silicon make it somewhat difficult to perform a 41 * repeat-start, and limit the repeat-start to a read following a write on 42 * the same slave device. (The i2c protocol allows a repeat start to change 43 * direction or not, and change slave address or not at any time.) 44 * 45 * The repeat-start bug and workaround are described in a problem report at 46 * https://github.com/raspberrypi/linux/issues/254 with the crucial part being 47 * in a comment block from a fragment of a GPU i2c driver, containing this: 48 * 49 * ----------------------------------------------------------------------------- 50 * - See i2c.v: The I2C peripheral samples the values for rw_bit and xfer_count 51 * - in the IDLE state if start is set. 52 * - 53 * - We want to generate a ReSTART not a STOP at the end of the TX phase. In 54 * - order to do that we must ensure the state machine goes RACK1 -> RACK2 -> 55 * - SRSTRT1 (not RACK1 -> RACK2 -> SSTOP1). 56 * - 57 * - So, in the RACK2 state when (TX) xfer_count==0 we must therefore have 58 * - already set, ready to be sampled: 59 * - READ ; rw_bit <= I2CC bit 0 -- must be "read" 60 * - ST; start <= I2CC bit 7 -- must be "Go" in order to not issue STOP 61 * - DLEN; xfer_count <= I2CDLEN -- must be equal to our read amount 62 * - 63 * - The plan to do this is: 64 * - 1. Start the sub-address write, but don't let it finish 65 * - (keep xfer_count > 0) 66 * - 2. Populate READ, DLEN and ST in preparation for ReSTART read sequence 67 * - 3. Let TX finish (write the rest of the data) 68 * - 4. Read back data as it arrives 69 * ----------------------------------------------------------------------------- 70 * 71 * The transfer function below scans the list of messages passed to it, looking 72 * for a read following a write to the same slave. When it finds that, it 73 * starts the write without prefilling the tx fifo, which holds xfer_count>0, 74 * then presets the direction, length, and start command for the following read, 75 * as described above. Then the tx fifo is filled and the rest of the transfer 76 * proceeds as normal, with the controller automatically supplying a 77 * repeat-start on the bus when the write operation finishes. 78 * 79 * XXX I suspect the controller may be able to do a repeat-start on any 80 * write->read or write->write transition, even when the slave addresses differ. 81 * It's unclear whether the slave address can be prestaged along with the 82 * direction and length while the write xfer_count is being held at zero. In 83 * fact, if it can't do this, then it couldn't be used to read EDID data. 84 */ 85 86#include <sys/param.h> 87#include <sys/systm.h> 88#include <sys/kernel.h> 89#include <sys/lock.h> 90#include <sys/module.h> 91#include <sys/mutex.h> 92#include <sys/bus.h> 93#include <machine/resource.h> 94#include <machine/bus.h> 95#include <sys/rman.h> 96#include <sys/sysctl.h> 97 98#include <dev/iicbus/iicbus.h> 99#include <dev/iicbus/iiconf.h> 100#include <dev/ofw/ofw_bus.h> 101#include <dev/ofw/ofw_bus_subr.h> 102 103#include <arm/broadcom/bcm2835/bcm2835_gpio.h> 104#include <arm/broadcom/bcm2835/bcm2835_bscreg.h> 105#include <arm/broadcom/bcm2835/bcm2835_bscvar.h> 106 107#include "iicbus_if.h" 108 109static struct ofw_compat_data compat_data[] = { 110 {"broadcom,bcm2835-bsc", 1}, 111 {"brcm,bcm2708-i2c", 1}, 112 {NULL, 0} 113}; 114 115#define DEVICE_DEBUGF(sc, lvl, fmt, args...) \ 116 if ((lvl) <= (sc)->sc_debug) \ 117 device_printf((sc)->sc_dev, fmt, ##args) 118 119#define DEBUGF(sc, lvl, fmt, args...) \ 120 if ((lvl) <= (sc)->sc_debug) \ 121 printf(fmt, ##args) 122 123static void bcm_bsc_intr(void *); 124static int bcm_bsc_detach(device_t); 125 126static void 127bcm_bsc_modifyreg(struct bcm_bsc_softc *sc, uint32_t off, uint32_t mask, 128 uint32_t value) 129{ 130 uint32_t reg; 131 132 mtx_assert(&sc->sc_mtx, MA_OWNED); 133 reg = BCM_BSC_READ(sc, off); 134 reg &= ~mask; 135 reg |= value; 136 BCM_BSC_WRITE(sc, off, reg); 137} 138 139static int 140bcm_bsc_clock_proc(SYSCTL_HANDLER_ARGS) 141{ 142 struct bcm_bsc_softc *sc; 143 uint32_t clk; 144 145 sc = (struct bcm_bsc_softc *)arg1; 146 BCM_BSC_LOCK(sc); 147 clk = BCM_BSC_READ(sc, BCM_BSC_CLOCK); 148 BCM_BSC_UNLOCK(sc); 149 clk &= 0xffff; 150 if (clk == 0) 151 clk = 32768; 152 clk = BCM_BSC_CORE_CLK / clk; 153 154 return (sysctl_handle_int(oidp, &clk, 0, req)); 155} 156 157static int 158bcm_bsc_clkt_proc(SYSCTL_HANDLER_ARGS) 159{ 160 struct bcm_bsc_softc *sc; 161 uint32_t clkt; 162 int error; 163 164 sc = (struct bcm_bsc_softc *)arg1; 165 166 BCM_BSC_LOCK(sc); 167 clkt = BCM_BSC_READ(sc, BCM_BSC_CLKT); 168 BCM_BSC_UNLOCK(sc); 169 clkt &= 0xffff; 170 error = sysctl_handle_int(oidp, &clkt, sizeof(clkt), req); 171 if (error != 0 || req->newptr == NULL) 172 return (error); 173 174 BCM_BSC_LOCK(sc); 175 BCM_BSC_WRITE(sc, BCM_BSC_CLKT, clkt & 0xffff); 176 BCM_BSC_UNLOCK(sc); 177 178 return (0); 179} 180 181static int 182bcm_bsc_fall_proc(SYSCTL_HANDLER_ARGS) 183{ 184 struct bcm_bsc_softc *sc; 185 uint32_t clk, reg; 186 int error; 187 188 sc = (struct bcm_bsc_softc *)arg1; 189 190 BCM_BSC_LOCK(sc); 191 reg = BCM_BSC_READ(sc, BCM_BSC_DELAY); 192 BCM_BSC_UNLOCK(sc); 193 reg >>= 16; 194 error = sysctl_handle_int(oidp, ®, sizeof(reg), req); 195 if (error != 0 || req->newptr == NULL) 196 return (error); 197 198 BCM_BSC_LOCK(sc); 199 clk = BCM_BSC_READ(sc, BCM_BSC_CLOCK); 200 clk = BCM_BSC_CORE_CLK / clk; 201 if (reg > clk / 2) 202 reg = clk / 2 - 1; 203 bcm_bsc_modifyreg(sc, BCM_BSC_DELAY, 0xffff0000, reg << 16); 204 BCM_BSC_UNLOCK(sc); 205 206 return (0); 207} 208 209static int 210bcm_bsc_rise_proc(SYSCTL_HANDLER_ARGS) 211{ 212 struct bcm_bsc_softc *sc; 213 uint32_t clk, reg; 214 int error; 215 216 sc = (struct bcm_bsc_softc *)arg1; 217 218 BCM_BSC_LOCK(sc); 219 reg = BCM_BSC_READ(sc, BCM_BSC_DELAY); 220 BCM_BSC_UNLOCK(sc); 221 reg &= 0xffff; 222 error = sysctl_handle_int(oidp, ®, sizeof(reg), req); 223 if (error != 0 || req->newptr == NULL) 224 return (error); 225 226 BCM_BSC_LOCK(sc); 227 clk = BCM_BSC_READ(sc, BCM_BSC_CLOCK); 228 clk = BCM_BSC_CORE_CLK / clk; 229 if (reg > clk / 2) 230 reg = clk / 2 - 1; 231 bcm_bsc_modifyreg(sc, BCM_BSC_DELAY, 0xffff, reg); 232 BCM_BSC_UNLOCK(sc); 233 234 return (0); 235} 236 237static void 238bcm_bsc_sysctl_init(struct bcm_bsc_softc *sc) 239{ 240 struct sysctl_ctx_list *ctx; 241 struct sysctl_oid *tree_node; 242 struct sysctl_oid_list *tree; 243 244 /* 245 * Add system sysctl tree/handlers. 246 */ 247 ctx = device_get_sysctl_ctx(sc->sc_dev); 248 tree_node = device_get_sysctl_tree(sc->sc_dev); 249 tree = SYSCTL_CHILDREN(tree_node); 250 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "frequency", 251 CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc), 252 bcm_bsc_clock_proc, "IU", "I2C BUS clock frequency"); 253 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "clock_stretch", 254 CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc), 255 bcm_bsc_clkt_proc, "IU", "I2C BUS clock stretch timeout"); 256 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "fall_edge_delay", 257 CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc), 258 bcm_bsc_fall_proc, "IU", "I2C BUS falling edge delay"); 259 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "rise_edge_delay", 260 CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc), 261 bcm_bsc_rise_proc, "IU", "I2C BUS rising edge delay"); 262 SYSCTL_ADD_INT(ctx, tree, OID_AUTO, "debug", 263 CTLFLAG_RWTUN, &sc->sc_debug, 0, 264 "Enable debug; 1=reads/writes, 2=add starts/stops"); 265} 266 267static void 268bcm_bsc_reset(struct bcm_bsc_softc *sc) 269{ 270 271 /* Enable the BSC Controller, disable interrupts. */ 272 BCM_BSC_WRITE(sc, BCM_BSC_CTRL, BCM_BSC_CTRL_I2CEN); 273 /* Clear pending interrupts. */ 274 BCM_BSC_WRITE(sc, BCM_BSC_STATUS, BCM_BSC_STATUS_CLKT | 275 BCM_BSC_STATUS_ERR | BCM_BSC_STATUS_DONE); 276 /* Clear the FIFO. */ 277 bcm_bsc_modifyreg(sc, BCM_BSC_CTRL, BCM_BSC_CTRL_CLEAR0, 278 BCM_BSC_CTRL_CLEAR0); 279} 280 281static int 282bcm_bsc_probe(device_t dev) 283{ 284 285 if (!ofw_bus_status_okay(dev)) 286 return (ENXIO); 287 288 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 289 return (ENXIO); 290 291 device_set_desc(dev, "BCM2708/2835 BSC controller"); 292 293 return (BUS_PROBE_DEFAULT); 294} 295 296static int 297bcm_bsc_attach(device_t dev) 298{ 299 struct bcm_bsc_softc *sc; 300 unsigned long start; 301 device_t gpio; 302 int i, rid; 303 304 sc = device_get_softc(dev); 305 sc->sc_dev = dev; 306 307 rid = 0; 308 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 309 RF_ACTIVE); 310 if (!sc->sc_mem_res) { 311 device_printf(dev, "cannot allocate memory window\n"); 312 return (ENXIO); 313 } 314 315 sc->sc_bst = rman_get_bustag(sc->sc_mem_res); 316 sc->sc_bsh = rman_get_bushandle(sc->sc_mem_res); 317 318 /* Check the unit we are attaching by its base address. */ 319 start = rman_get_start(sc->sc_mem_res); 320 for (i = 0; i < nitems(bcm_bsc_pins); i++) { 321 if (bcm_bsc_pins[i].start == (start & BCM_BSC_BASE_MASK)) 322 break; 323 } 324 if (i == nitems(bcm_bsc_pins)) { 325 device_printf(dev, "only bsc0 and bsc1 are supported\n"); 326 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 327 return (ENXIO); 328 } 329 330 /* 331 * Configure the GPIO pins to ALT0 function to enable BSC control 332 * over the pins. 333 */ 334 gpio = devclass_get_device(devclass_find("gpio"), 0); 335 if (!gpio) { 336 device_printf(dev, "cannot find gpio0\n"); 337 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 338 return (ENXIO); 339 } 340 bcm_gpio_set_alternate(gpio, bcm_bsc_pins[i].sda, BCM_GPIO_ALT0); 341 bcm_gpio_set_alternate(gpio, bcm_bsc_pins[i].scl, BCM_GPIO_ALT0); 342 343 rid = 0; 344 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 345 RF_ACTIVE | RF_SHAREABLE); 346 if (!sc->sc_irq_res) { 347 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 348 device_printf(dev, "cannot allocate interrupt\n"); 349 return (ENXIO); 350 } 351 352 /* Hook up our interrupt handler. */ 353 if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 354 NULL, bcm_bsc_intr, sc, &sc->sc_intrhand)) { 355 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); 356 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 357 device_printf(dev, "cannot setup the interrupt handler\n"); 358 return (ENXIO); 359 } 360 361 mtx_init(&sc->sc_mtx, "bcm_bsc", NULL, MTX_DEF); 362 363 bcm_bsc_sysctl_init(sc); 364 365 /* Enable the BSC controller. Flush the FIFO. */ 366 BCM_BSC_LOCK(sc); 367 bcm_bsc_reset(sc); 368 BCM_BSC_UNLOCK(sc); 369 370 sc->sc_iicbus = device_add_child(dev, "iicbus", -1); 371 if (sc->sc_iicbus == NULL) { 372 bcm_bsc_detach(dev); 373 return (ENXIO); 374 } 375 376 /* Probe and attach the iicbus when interrupts are available. */ 377 config_intrhook_oneshot((ich_func_t)bus_generic_attach, dev); 378 379 return (0); 380} 381 382static int 383bcm_bsc_detach(device_t dev) 384{ 385 struct bcm_bsc_softc *sc; 386 387 bus_generic_detach(dev); 388 389 sc = device_get_softc(dev); 390 if (sc->sc_iicbus != NULL) 391 device_delete_child(dev, sc->sc_iicbus); 392 mtx_destroy(&sc->sc_mtx); 393 if (sc->sc_intrhand) 394 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intrhand); 395 if (sc->sc_irq_res) 396 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); 397 if (sc->sc_mem_res) 398 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 399 400 return (0); 401} 402 403static void 404bcm_bsc_empty_rx_fifo(struct bcm_bsc_softc *sc) 405{ 406 uint32_t status; 407 408 /* Assumes sc_totlen > 0 and BCM_BSC_STATUS_RXD is asserted on entry. */ 409 do { 410 if (sc->sc_resid == 0) { 411 sc->sc_data = sc->sc_curmsg->buf; 412 sc->sc_dlen = sc->sc_curmsg->len; 413 sc->sc_resid = sc->sc_dlen; 414 ++sc->sc_curmsg; 415 } 416 do { 417 *sc->sc_data = BCM_BSC_READ(sc, BCM_BSC_DATA); 418 DEBUGF(sc, 1, "0x%02x ", *sc->sc_data); 419 ++sc->sc_data; 420 --sc->sc_resid; 421 --sc->sc_totlen; 422 status = BCM_BSC_READ(sc, BCM_BSC_STATUS); 423 } while (sc->sc_resid > 0 && (status & BCM_BSC_STATUS_RXD)); 424 } while (sc->sc_totlen > 0 && (status & BCM_BSC_STATUS_RXD)); 425} 426 427static void 428bcm_bsc_fill_tx_fifo(struct bcm_bsc_softc *sc) 429{ 430 uint32_t status; 431 432 /* Assumes sc_totlen > 0 and BCM_BSC_STATUS_TXD is asserted on entry. */ 433 do { 434 if (sc->sc_resid == 0) { 435 sc->sc_data = sc->sc_curmsg->buf; 436 sc->sc_dlen = sc->sc_curmsg->len; 437 sc->sc_resid = sc->sc_dlen; 438 ++sc->sc_curmsg; 439 } 440 do { 441 BCM_BSC_WRITE(sc, BCM_BSC_DATA, *sc->sc_data); 442 DEBUGF(sc, 1, "0x%02x ", *sc->sc_data); 443 ++sc->sc_data; 444 --sc->sc_resid; 445 --sc->sc_totlen; 446 status = BCM_BSC_READ(sc, BCM_BSC_STATUS); 447 } while (sc->sc_resid > 0 && (status & BCM_BSC_STATUS_TXD)); 448 /* 449 * If a repeat-start was pending and we just hit the end of a tx 450 * buffer, see if it's also the end of the writes that preceeded 451 * the repeat-start. If so, log the repeat-start and the start 452 * of the following read, and return because we're not writing 453 * anymore (and TXD will be true because there's room to write 454 * in the fifo). 455 */ 456 if (sc->sc_replen > 0 && sc->sc_resid == 0) { 457 sc->sc_replen -= sc->sc_dlen; 458 if (sc->sc_replen == 0) { 459 DEBUGF(sc, 1, " err=0\n"); 460 DEVICE_DEBUGF(sc, 2, "rstart 0x%02x\n", 461 sc->sc_curmsg->slave | 0x01); 462 DEVICE_DEBUGF(sc, 1, 463 "read 0x%02x len %d: ", 464 sc->sc_curmsg->slave | 0x01, 465 sc->sc_totlen); 466 sc->sc_flags |= BCM_I2C_READ; 467 return; 468 } 469 } 470 } while (sc->sc_totlen > 0 && (status & BCM_BSC_STATUS_TXD)); 471} 472 473static void 474bcm_bsc_intr(void *arg) 475{ 476 struct bcm_bsc_softc *sc; 477 uint32_t status; 478 479 sc = (struct bcm_bsc_softc *)arg; 480 481 BCM_BSC_LOCK(sc); 482 483 /* The I2C interrupt is shared among all the BSC controllers. */ 484 if ((sc->sc_flags & BCM_I2C_BUSY) == 0) { 485 BCM_BSC_UNLOCK(sc); 486 return; 487 } 488 489 status = BCM_BSC_READ(sc, BCM_BSC_STATUS); 490 DEBUGF(sc, 4, " <intrstatus=0x%08x> ", status); 491 492 /* RXD and DONE can assert together, empty fifo before checking done. */ 493 if ((sc->sc_flags & BCM_I2C_READ) && (status & BCM_BSC_STATUS_RXD)) 494 bcm_bsc_empty_rx_fifo(sc); 495 496 /* Check for completion. */ 497 if (status & (BCM_BSC_STATUS_ERRBITS | BCM_BSC_STATUS_DONE)) { 498 sc->sc_flags |= BCM_I2C_DONE; 499 if (status & BCM_BSC_STATUS_ERRBITS) 500 sc->sc_flags |= BCM_I2C_ERROR; 501 /* Disable interrupts. */ 502 bcm_bsc_reset(sc); 503 wakeup(sc); 504 } else if (!(sc->sc_flags & BCM_I2C_READ)) { 505 /* 506 * Don't check for TXD until after determining whether the 507 * transfer is complete; TXD will be asserted along with ERR or 508 * DONE if there is room in the fifo. 509 */ 510 if ((status & BCM_BSC_STATUS_TXD) && sc->sc_totlen > 0) 511 bcm_bsc_fill_tx_fifo(sc); 512 } 513 514 BCM_BSC_UNLOCK(sc); 515} 516 517static int 518bcm_bsc_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs) 519{ 520 struct bcm_bsc_softc *sc; 521 struct iic_msg *endmsgs, *nxtmsg; 522 uint32_t readctl, status; 523 int err; 524 uint16_t curlen; 525 uint8_t curisread, curslave, nxtisread, nxtslave; 526 527 sc = device_get_softc(dev); 528 BCM_BSC_LOCK(sc); 529 530 /* If the controller is busy wait until it is available. */ 531 while (sc->sc_flags & BCM_I2C_BUSY) 532 mtx_sleep(dev, &sc->sc_mtx, 0, "bscbusw", 0); 533 534 /* Now we have control over the BSC controller. */ 535 sc->sc_flags = BCM_I2C_BUSY; 536 537 DEVICE_DEBUGF(sc, 3, "Transfer %d msgs\n", nmsgs); 538 539 /* Clear the FIFO and the pending interrupts. */ 540 bcm_bsc_reset(sc); 541 542 /* 543 * Perform all the transfers requested in the array of msgs. Note that 544 * it is bcm_bsc_empty_rx_fifo() and bcm_bsc_fill_tx_fifo() that advance 545 * sc->sc_curmsg through the array of messages, as the data from each 546 * message is fully consumed, but it is this loop that notices when we 547 * have no more messages to process. 548 */ 549 err = 0; 550 sc->sc_resid = 0; 551 sc->sc_curmsg = msgs; 552 endmsgs = &msgs[nmsgs]; 553 while (sc->sc_curmsg < endmsgs) { 554 readctl = 0; 555 curslave = sc->sc_curmsg->slave >> 1; 556 curisread = sc->sc_curmsg->flags & IIC_M_RD; 557 sc->sc_replen = 0; 558 sc->sc_totlen = sc->sc_curmsg->len; 559 /* 560 * Scan for scatter/gather IO (same slave and direction) or 561 * repeat-start (read following write for the same slave). 562 */ 563 for (nxtmsg = sc->sc_curmsg + 1; nxtmsg < endmsgs; ++nxtmsg) { 564 nxtslave = nxtmsg->slave >> 1; 565 if (curslave == nxtslave) { 566 nxtisread = nxtmsg->flags & IIC_M_RD; 567 if (curisread == nxtisread) { 568 /* 569 * Same slave and direction, this 570 * message will be part of the same 571 * transfer as the previous one. 572 */ 573 sc->sc_totlen += nxtmsg->len; 574 continue; 575 } else if (curisread == IIC_M_WR) { 576 /* 577 * Read after write to same slave means 578 * repeat-start, remember how many bytes 579 * come before the repeat-start, switch 580 * the direction to IIC_M_RD, and gather 581 * up following reads to the same slave. 582 */ 583 curisread = IIC_M_RD; 584 sc->sc_replen = sc->sc_totlen; 585 sc->sc_totlen += nxtmsg->len; 586 continue; 587 } 588 } 589 break; 590 } 591 592 /* 593 * curslave and curisread temporaries from above may refer to 594 * the after-repstart msg, reset them to reflect sc_curmsg. 595 */ 596 curisread = (sc->sc_curmsg->flags & IIC_M_RD) ? 1 : 0; 597 curslave = sc->sc_curmsg->slave | curisread; 598 599 /* Write the slave address. */ 600 BCM_BSC_WRITE(sc, BCM_BSC_SLAVE, curslave >> 1); 601 602 DEVICE_DEBUGF(sc, 2, "start 0x%02x\n", curslave); 603 604 /* 605 * Either set up read length and direction variables for a 606 * simple transfer or get the hardware started on the first 607 * piece of a transfer that involves a repeat-start and set up 608 * the read length and direction vars for the second piece. 609 */ 610 if (sc->sc_replen == 0) { 611 DEVICE_DEBUGF(sc, 1, "%-6s 0x%02x len %d: ", 612 (curisread) ? "read" : "write", curslave, 613 sc->sc_totlen); 614 curlen = sc->sc_totlen; 615 if (curisread) { 616 readctl = BCM_BSC_CTRL_READ; 617 sc->sc_flags |= BCM_I2C_READ; 618 } else { 619 readctl = 0; 620 sc->sc_flags &= ~BCM_I2C_READ; 621 } 622 } else { 623 DEVICE_DEBUGF(sc, 1, "%-6s 0x%02x len %d: ", 624 (curisread) ? "read" : "write", curslave, 625 sc->sc_replen); 626 627 /* 628 * Start the write transfer with an empty fifo and wait 629 * for the 'transfer active' status bit to light up; 630 * that indicates that the hardware has latched the 631 * direction and length for the write, and we can safely 632 * reload those registers and issue the start for the 633 * following read; interrupts are not enabled here. 634 */ 635 BCM_BSC_WRITE(sc, BCM_BSC_DLEN, sc->sc_replen); 636 BCM_BSC_WRITE(sc, BCM_BSC_CTRL, BCM_BSC_CTRL_I2CEN | 637 BCM_BSC_CTRL_ST); 638 do { 639 status = BCM_BSC_READ(sc, BCM_BSC_STATUS); 640 if (status & BCM_BSC_STATUS_ERR) { 641 /* no ACK on slave addr */ 642 err = EIO; 643 goto xfer_done; 644 } 645 } while ((status & BCM_BSC_STATUS_TA) == 0); 646 /* 647 * Set curlen and readctl for the repeat-start read that 648 * we need to set up below, but set sc_flags to write, 649 * because that is the operation in progress right now. 650 */ 651 curlen = sc->sc_totlen - sc->sc_replen; 652 readctl = BCM_BSC_CTRL_READ; 653 sc->sc_flags &= ~BCM_I2C_READ; 654 } 655 656 /* 657 * Start the transfer with interrupts enabled, then if doing a 658 * write, fill the tx fifo. Not prefilling the fifo until after 659 * this start command is the key workaround for making 660 * repeat-start work, and it's harmless to do it in this order 661 * for a regular write too. 662 */ 663 BCM_BSC_WRITE(sc, BCM_BSC_DLEN, curlen); 664 BCM_BSC_WRITE(sc, BCM_BSC_CTRL, readctl | BCM_BSC_CTRL_I2CEN | 665 BCM_BSC_CTRL_ST | BCM_BSC_CTRL_INT_ALL); 666 667 if (!(sc->sc_curmsg->flags & IIC_M_RD)) { 668 bcm_bsc_fill_tx_fifo(sc); 669 } 670 671 /* Wait for the transaction to complete. */ 672 while (err == 0 && !(sc->sc_flags & BCM_I2C_DONE)) { 673 err = mtx_sleep(sc, &sc->sc_mtx, 0, "bsciow", hz); 674 } 675 /* Check for errors. */ 676 if (err == 0 && (sc->sc_flags & BCM_I2C_ERROR)) 677 err = EIO; 678xfer_done: 679 DEBUGF(sc, 1, " err=%d\n", err); 680 DEVICE_DEBUGF(sc, 2, "stop\n"); 681 if (err != 0) 682 break; 683 } 684 685 /* Disable interrupts, clean fifo, etc. */ 686 bcm_bsc_reset(sc); 687 688 /* Clean the controller flags. */ 689 sc->sc_flags = 0; 690 691 /* Wake up the threads waiting for bus. */ 692 wakeup(dev); 693 694 BCM_BSC_UNLOCK(sc); 695 696 return (err); 697} 698 699static int 700bcm_bsc_iicbus_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr) 701{ 702 struct bcm_bsc_softc *sc; 703 uint32_t busfreq; 704 705 sc = device_get_softc(dev); 706 BCM_BSC_LOCK(sc); 707 bcm_bsc_reset(sc); 708 if (sc->sc_iicbus == NULL) 709 busfreq = 100000; 710 else 711 busfreq = IICBUS_GET_FREQUENCY(sc->sc_iicbus, speed); 712 BCM_BSC_WRITE(sc, BCM_BSC_CLOCK, BCM_BSC_CORE_CLK / busfreq); 713 BCM_BSC_UNLOCK(sc); 714 715 return (IIC_ENOADDR); 716} 717 718static phandle_t 719bcm_bsc_get_node(device_t bus, device_t dev) 720{ 721 722 /* We only have one child, the I2C bus, which needs our own node. */ 723 return (ofw_bus_get_node(bus)); 724} 725 726static device_method_t bcm_bsc_methods[] = { 727 /* Device interface */ 728 DEVMETHOD(device_probe, bcm_bsc_probe), 729 DEVMETHOD(device_attach, bcm_bsc_attach), 730 DEVMETHOD(device_detach, bcm_bsc_detach), 731 732 /* iicbus interface */ 733 DEVMETHOD(iicbus_reset, bcm_bsc_iicbus_reset), 734 DEVMETHOD(iicbus_callback, iicbus_null_callback), 735 DEVMETHOD(iicbus_transfer, bcm_bsc_transfer), 736 737 /* ofw_bus interface */ 738 DEVMETHOD(ofw_bus_get_node, bcm_bsc_get_node), 739 740 DEVMETHOD_END 741}; 742 743static devclass_t bcm_bsc_devclass; 744 745static driver_t bcm_bsc_driver = { 746 "iichb", 747 bcm_bsc_methods, 748 sizeof(struct bcm_bsc_softc), 749}; 750 751DRIVER_MODULE(iicbus, bcm2835_bsc, iicbus_driver, iicbus_devclass, 0, 0); 752DRIVER_MODULE(bcm2835_bsc, simplebus, bcm_bsc_driver, bcm_bsc_devclass, 0, 0); 753