at91rm92reg.h revision 330897
1/*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2005 Olivier Houchard. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28/* $FreeBSD: stable/11/sys/arm/at91/at91rm92reg.h 330897 2018-03-14 03:19:51Z eadler $ */ 29 30#ifndef AT91RM92REG_H_ 31#define AT91RM92REG_H_ 32 33/* Chip Specific limits */ 34#define RM9200_PLL_A_MIN_IN_FREQ 1000000 /* 1 MHz */ 35#define RM9200_PLL_A_MAX_IN_FREQ 32000000 /* 32 MHz */ 36#define RM9200_PLL_A_MIN_OUT_FREQ 80000000 /* 80 MHz */ 37#define RM9200_PLL_A_MAX_OUT_FREQ 180000000 /* 180 MHz */ 38#define RM9200_PLL_A_MUL_SHIFT 16 39#define RM9200_PLL_A_MUL_MASK 0x7FF 40#define RM9200_PLL_A_DIV_SHIFT 0 41#define RM9200_PLL_A_DIV_MASK 0xFF 42 43/* 44 * PLL B input frequency spec sheet says it must be between 1MHz and 32MHz, 45 * but it works down as low as 100kHz, a frequency necessary for some 46 * output frequencies to work. 47 * 48 * PLL Max output frequency is 240MHz. The errata says 180MHz is the max 49 * for some revisions of this part. Be more permissive and optimistic. 50 */ 51#define RM9200_PLL_B_MIN_IN_FREQ 100000 /* 100 KHz */ 52#define RM9200_PLL_B_MAX_IN_FREQ 32000000 /* 32 MHz */ 53#define RM9200_PLL_B_MIN_OUT_FREQ 30000000 /* 30 MHz */ 54#define RM9200_PLL_B_MAX_OUT_FREQ 240000000 /* 240 MHz */ 55#define RM9200_PLL_B_MUL_SHIFT 16 56#define RM9200_PLL_B_MUL_MASK 0x7FF 57#define RM9200_PLL_B_DIV_SHIFT 0 58#define RM9200_PLL_B_DIV_MASK 0xFF 59 60/* 61 * Memory map, from datasheet : 62 * 0x00000000 - 0x0ffffffff : Internal Memories 63 * 0x10000000 - 0x1ffffffff : Chip Select 0 64 * 0x20000000 - 0x2ffffffff : Chip Select 1 65 * 0x30000000 - 0x3ffffffff : Chip Select 2 66 * 0x40000000 - 0x4ffffffff : Chip Select 3 67 * 0x50000000 - 0x5ffffffff : Chip Select 4 68 * 0x60000000 - 0x6ffffffff : Chip Select 5 69 * 0x70000000 - 0x7ffffffff : Chip Select 6 70 * 0x80000000 - 0x8ffffffff : Chip Select 7 71 * 0x90000000 - 0xeffffffff : Undefined (Abort) 72 * 0xf0000000 - 0xfffffffff : Peripherals 73 */ 74 75/* Usart */ 76 77#define AT91RM92_USART_SIZE 0x4000 78#define AT91RM92_USART0_BASE 0xffc0000 79#define AT91RM92_USART0_PDC 0xffc0100 80#define AT91RM92_USART0_SIZE AT91RM92_USART_SIZE 81#define AT91RM92_USART1_BASE 0xffc4000 82#define AT91RM92_USART1_PDC 0xffc4100 83#define AT91RM92_USART1_SIZE AT91RM92_USART_SIZE 84#define AT91RM92_USART2_BASE 0xffc8000 85#define AT91RM92_USART2_PDC 0xffc8100 86#define AT91RM92_USART2_SIZE AT91RM92_USART_SIZE 87#define AT91RM92_USART3_BASE 0xffcc000 88#define AT91RM92_USART3_PDC 0xffcc100 89#define AT91RM92_USART3_SIZE AT91RM92_USART_SIZE 90 91/* System Registers */ 92 93#define AT91RM92_SYS_BASE 0xffff000 94#define AT91RM92_SYS_SIZE 0x1000 95 96/* 97 * PIO 98 */ 99#define AT91RM92_PIO_SIZE 0x200 100#define AT91RM92_PIOA_BASE 0xffff400 101#define AT91RM92_PIOA_SIZE AT91RM92_PIO_SIZE 102#define AT91RM92_PIOB_BASE 0xffff600 103#define AT91RM92_PIOB_SIZE AT91RM92_PIO_SIZE 104#define AT91RM92_PIOC_BASE 0xffff800 105#define AT91RM92_PIOC_SIZE AT91RM92_PIO_SIZE 106#define AT91RM92_PIOD_BASE 0xffffa00 107#define AT91RM92_PIOD_SIZE AT91RM92_PIO_SIZE 108 109/* 110 * PMC 111 */ 112#define AT91RM92_PMC_BASE 0xffffc00 113#define AT91RM92_PMC_SIZE 0x100 114 115/* IRQs : */ 116/* 117 * 0: AIC 118 * 1: System peripheral (System timer, RTC, DBGU) 119 * 2: PIO Controller A 120 * 3: PIO Controller B 121 * 4: PIO Controller C 122 * 5: PIO Controller D 123 * 6: USART 0 124 * 7: USART 1 125 * 8: USART 2 126 * 9: USART 3 127 * 10: MMC Interface 128 * 11: USB device port 129 * 12: Two-wire interface 130 * 13: SPI 131 * 14: SSC 132 * 15: SSC 133 * 16: SSC 134 * 17: Timer Counter 0 135 * 18: Timer Counter 1 136 * 19: Timer Counter 2 137 * 20: Timer Counter 3 138 * 21: Timer Counter 4 139 * 22: Timer Counter 5 140 * 23: USB Host port 141 * 24: Ethernet 142 * 25: AIC 143 * 26: AIC 144 * 27: AIC 145 * 28: AIC 146 * 29: AIC 147 * 30: AIC 148 * 31: AIC 149 */ 150 151#define AT91RM92_IRQ_SYSTEM 1 152#define AT91RM92_IRQ_PIOA 2 153#define AT91RM92_IRQ_PIOB 3 154#define AT91RM92_IRQ_PIOC 4 155#define AT91RM92_IRQ_PIOD 5 156#define AT91RM92_IRQ_USART0 6 157#define AT91RM92_IRQ_USART1 7 158#define AT91RM92_IRQ_USART2 8 159#define AT91RM92_IRQ_USART3 9 160#define AT91RM92_IRQ_MCI 10 161#define AT91RM92_IRQ_UDP 11 162#define AT91RM92_IRQ_TWI 12 163#define AT91RM92_IRQ_SPI 13 164#define AT91RM92_IRQ_SSC0 14 165#define AT91RM92_IRQ_SSC1 15 166#define AT91RM92_IRQ_SSC2 16 167#define AT91RM92_IRQ_TC0 17,18,19 168#define AT91RM92_IRQ_TC0C0 17 169#define AT91RM92_IRQ_TC0C1 18 170#define AT91RM92_IRQ_TC0C2 19 171#define AT91RM92_IRQ_TC1 20,21,22 172#define AT91RM92_IRQ_TC1C1 20 173#define AT91RM92_IRQ_TC1C2 21 174#define AT91RM92_IRQ_TC1C3 22 175#define AT91RM92_IRQ_UHP 23 176#define AT91RM92_IRQ_EMAC 24 177#define AT91RM92_IRQ_AIC_IRQ0 25 178#define AT91RM92_IRQ_AIC_IRQ1 26 179#define AT91RM92_IRQ_AIC_IRQ2 27 180#define AT91RM92_IRQ_AIC_IRQ3 28 181#define AT91RM92_IRQ_AIC_IRQ4 29 182#define AT91RM92_IRQ_AIC_IRQ5 30 183#define AT91RM92_IRQ_AIC_IRQ6 31 184 185/* Alias */ 186#define AT91RM92_IRQ_DBGU AT91RM92_IRQ_SYSTEM 187#define AT91RM92_IRQ_PMC AT91RM92_IRQ_SYSTEM 188#define AT91RM92_IRQ_ST AT91RM92_IRQ_SYSTEM 189#define AT91RM92_IRQ_RTC AT91RM92_IRQ_SYSTEM 190#define AT91RM92_IRQ_MC AT91RM92_IRQ_SYSTEM 191#define AT91RM92_IRQ_OHCI AT91RM92_IRQ_UHP 192#define AT91RM92_IRQ_AIC -1 193#define AT91RM92_IRQ_CF -1 194 195/* Timer */ 196 197#define AT91RM92_AIC_BASE 0xffff000 198#define AT91RM92_AIC_SIZE 0x200 199 200/* DBGU */ 201#define AT91RM92_DBGU_BASE 0xffff200 202#define AT91RM92_DBGU_SIZE 0x200 203 204#define AT91RM92_RTC_BASE 0xffffe00 205#define AT91RM92_RTC_SIZE 0x100 206 207#define AT91RM92_MC_BASE 0xfffff00 208#define AT91RM92_MC_SIZE 0x100 209 210#define AT91RM92_ST_BASE 0xffffd00 211#define AT91RM92_ST_SIZE 0x100 212 213#define AT91RM92_SPI_BASE 0xffe0000 214#define AT91RM92_SPI_SIZE 0x4000 215#define AT91RM92_SPI_PDC 0xffe0100 216 217#define AT91RM92_SSC_SIZE 0x4000 218#define AT91RM92_SSC0_BASE 0xffd0000 219#define AT91RM92_SSC0_PDC 0xffd0100 220#define AT91RM92_SSC0_SIZE AT91RM92_SSC_SIZE 221 222#define AT91RM92_SSC1_BASE 0xffd4000 223#define AT91RM92_SSC1_PDC 0xffd4100 224#define AT91RM92_SSC1_SIZE AT91RM92_SSC_SIZE 225 226#define AT91RM92_SSC2_BASE 0xffd8000 227#define AT91RM92_SSC2_PDC 0xffd8100 228#define AT91RM92_SSC2_SIZE AT91RM92_SSC_SIZE 229 230#define AT91RM92_EMAC_BASE 0xffbc000 231#define AT91RM92_EMAC_SIZE 0x4000 232 233#define AT91RM92_TWI_BASE 0xffb8000 234#define AT91RM92_TWI_SIZE 0x4000 235 236#define AT91RM92_MCI_BASE 0xffb4000 237#define AT91RM92_MCI_PDC 0xffb4100 238#define AT91RM92_MCI_SIZE 0x4000 239 240#define AT91RM92_UDP_BASE 0xffb0000 241#define AT91RM92_UDP_SIZE 0x4000 242 243#define AT91RM92_TC_SIZE 0x4000 244#define AT91RM92_TC0_BASE 0xffa0000 245#define AT91RM92_TC0_SIZE AT91RM92_TC_SIZE 246#define AT91RM92_TC0C0_BASE 0xffa0000 247#define AT91RM92_TC0C1_BASE 0xffa0040 248#define AT91RM92_TC0C2_BASE 0xffa0080 249 250#define AT91RM92_TC1_BASE 0xffa4000 251#define AT91RM92_TC1_SIZE AT91RM92_TC_SIZE 252#define AT91RM92_TC1C0_BASE 0xffa4000 253#define AT91RM92_TC1C1_BASE 0xffa4040 254#define AT91RM92_TC1C2_BASE 0xffa4080 255 256/* XXX Needs to be carfully coordinated with 257 * other * soc's so phyical and vm address 258 * mapping are unique. XXX 259 */ 260#define AT91RM92_OHCI_VA_BASE 0xdfe00000 261#define AT91RM92_OHCI_BASE 0x00300000 262#define AT91RM92_OHCI_SIZE 0x00100000 263 264#define AT91RM92_CF_VA_BASE 0xdfd00000 265#define AT91RM92_CF_BASE 0x51400000 266#define AT91RM92_CF_SIZE 0x00100000 267 268/* SDRAMC */ 269 270#define AT91RM92_SDRAMC_BASE 0xfffff90 271#define AT91RM92_SDRAMC_MR 0x00 272#define AT91RM92_SDRAMC_MR_MODE_NORMAL 0 273#define AT91RM92_SDRAMC_MR_MODE_NOP 1 274#define AT91RM92_SDRAMC_MR_MODE_PRECHARGE 2 275#define AT91RM92_SDRAMC_MR_MODE_LOAD_MODE_REGISTER 3 276#define AT91RM92_SDRAMC_MR_MODE_REFRESH 4 277#define AT91RM92_SDRAMC_MR_DBW_16 0x10 278#define AT91RM92_SDRAMC_TR 0x04 279#define AT91RM92_SDRAMC_CR 0x08 280#define AT91RM92_SDRAMC_CR_NC_8 0x0 281#define AT91RM92_SDRAMC_CR_NC_9 0x1 282#define AT91RM92_SDRAMC_CR_NC_10 0x2 283#define AT91RM92_SDRAMC_CR_NC_11 0x3 284#define AT91RM92_SDRAMC_CR_NC_MASK 0x00000003 285#define AT91RM92_SDRAMC_CR_NR_11 0x0 286#define AT91RM92_SDRAMC_CR_NR_12 0x4 287#define AT91RM92_SDRAMC_CR_NR_13 0x8 288#define AT91RM92_SDRAMC_CR_NR_RES 0xc 289#define AT91RM92_SDRAMC_CR_NR_MASK 0x0000000c 290#define AT91RM92_SDRAMC_CR_NB_2 0x00 291#define AT91RM92_SDRAMC_CR_NB_4 0x10 292#define AT91RM92_SDRAMC_CR_NB_MASK 0x00000010 293#define AT91RM92_SDRAMC_CR_NCAS_MASK 0x00000060 294#define AT91RM92_SDRAMC_CR_TWR_MASK 0x00000780 295#define AT91RM92_SDRAMC_CR_TRC_MASK 0x00007800 296#define AT91RM92_SDRAMC_CR_TRP_MASK 0x00078000 297#define AT91RM92_SDRAMC_CR_TRCD_MASK 0x00780000 298#define AT91RM92_SDRAMC_CR_TRAS_MASK 0x07800000 299#define AT91RM92_SDRAMC_CR_TXSR_MASK 0x78000000 300#define AT91RM92_SDRAMC_SRR 0x0c 301#define AT91RM92_SDRAMC_LPR 0x10 302#define AT91RM92_SDRAMC_IER 0x14 303#define AT91RM92_SDRAMC_IDR 0x18 304#define AT91RM92_SDRAMC_IMR 0x1c 305#define AT91RM92_SDRAMC_ISR 0x20 306#define AT91RM92_SDRAMC_IER_RES 0x1 307 308#endif /* AT91RM92REG_H_ */ 309