at91_streg.h revision 330897 
1/*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2005 M. Warner Losh.  All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 *    notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 *    notice, this list of conditions and the following disclaimer in the
13 *    documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28/* $FreeBSD: stable/11/sys/arm/at91/at91_streg.h 330897 2018-03-14 03:19:51Z eadler $ */
29
30#ifndef ARM_AT91_AT91STREG_H
31#define ARM_AT91_AT91STREG_H
32
33#define ST_CR		0x00 /* Control register */
34#define ST_PIMR		0x04 /* Period interval mode register */
35#define ST_WDMR		0x08 /* Watchdog mode register */
36#define ST_RTMR		0x0c /* Real-time mode register */
37#define ST_SR		0x10 /* Status register */
38#define ST_IER		0x14 /* Interrupt enable register */
39#define ST_IDR		0x18 /* Interrupt disable register */
40#define ST_IMR		0x1c /* Interrupt mask register */
41#define ST_RTAR		0x20 /* Real-time alarm register */
42#define	ST_CRTR		0x24 /* Current real-time register */
43
44/* ST_CR */
45#define ST_CR_WDRST	(1U << 0) /* WDRST: Watchdog Timer Restart */
46
47/* ST_WDMR */
48#define ST_WDMR_EXTEN	(1U << 17) /* EXTEN: External Signal Assert Enable */
49#define ST_WDMR_RSTEN	(1U << 16) /* RSTEN: Reset Enable */
50
51/* ST_SR, ST_IER, ST_IDR, ST_IMR */
52#define ST_SR_PITS	(1U << 0) /* PITS: Period Interval Timer Status */
53#define ST_SR_WDOVF	(1U << 1) /* WDOVF: Watchdog Overflow */
54#define ST_SR_RTTINC	(1U << 2) /* RTTINC: Real-time Timer Increment */
55#define ST_SR_ALMS	(1U << 3) /* ALMS: Alarm Status */
56
57/* ST_CRTR */
58#define ST_CRTR_MASK	0xfffff /* 20-bit counter */
59
60void at91_st_delay(int n);
61void at91_st_cpu_reset(void);
62
63#endif /* ARM_AT91_AT91STREG_H */
64