at91_spi.c revision 330897
1/*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2006 M. Warner Losh. 5 * Copyright (c) 2011-2012 Ian Lepore. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30#include "opt_platform.h" 31 32#include <sys/cdefs.h> 33__FBSDID("$FreeBSD: stable/11/sys/arm/at91/at91_spi.c 330897 2018-03-14 03:19:51Z eadler $"); 34 35#include <sys/param.h> 36#include <sys/systm.h> 37#include <sys/bus.h> 38#include <sys/conf.h> 39#include <sys/kernel.h> 40#include <sys/lock.h> 41#include <sys/mbuf.h> 42#include <sys/malloc.h> 43#include <sys/module.h> 44#include <sys/rman.h> 45#include <sys/sx.h> 46 47#include <machine/bus.h> 48 49#include <arm/at91/at91var.h> 50#include <arm/at91/at91_spireg.h> 51#include <arm/at91/at91_pdcreg.h> 52 53#include <dev/spibus/spi.h> 54#include <dev/spibus/spibusvar.h> 55 56#ifdef FDT 57#include <dev/fdt/fdt_common.h> 58#include <dev/ofw/ofw_bus.h> 59#include <dev/ofw/ofw_bus_subr.h> 60#endif 61 62#include "spibus_if.h" 63 64struct at91_spi_softc 65{ 66 device_t dev; /* Myself */ 67 void *intrhand; /* Interrupt handle */ 68 struct resource *irq_res; /* IRQ resource */ 69 struct resource *mem_res; /* Memory resource */ 70 bus_dma_tag_t dmatag; /* bus dma tag for transfers */ 71 bus_dmamap_t map[4]; /* Maps for the transaction */ 72 struct sx xfer_mtx; /* Enforce one transfer at a time */ 73 uint32_t xfer_done; /* interrupt<->mainthread signaling */ 74}; 75 76#define CS_TO_MR(cs) ((~(1 << (cs)) & 0x0f) << 16) 77 78static inline uint32_t 79RD4(struct at91_spi_softc *sc, bus_size_t off) 80{ 81 82 return (bus_read_4(sc->mem_res, off)); 83} 84 85static inline void 86WR4(struct at91_spi_softc *sc, bus_size_t off, uint32_t val) 87{ 88 89 bus_write_4(sc->mem_res, off, val); 90} 91 92/* bus entry points */ 93static int at91_spi_attach(device_t dev); 94static int at91_spi_detach(device_t dev); 95static int at91_spi_probe(device_t dev); 96static int at91_spi_transfer(device_t dev, device_t child, 97 struct spi_command *cmd); 98 99/* helper routines */ 100static void at91_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, 101 int error); 102static int at91_spi_activate(device_t dev); 103static void at91_spi_deactivate(device_t dev); 104static void at91_spi_intr(void *arg); 105 106static int 107at91_spi_probe(device_t dev) 108{ 109#ifdef FDT 110 if (!ofw_bus_is_compatible(dev, "atmel,at91rm9200-spi")) 111 return (ENXIO); 112#endif 113 device_set_desc(dev, "AT91 SPI"); 114 return (0); 115} 116 117static int 118at91_spi_attach(device_t dev) 119{ 120 struct at91_spi_softc *sc; 121 int err; 122 uint32_t csr; 123 124 sc = device_get_softc(dev); 125 126 sc->dev = dev; 127 sx_init(&sc->xfer_mtx, device_get_nameunit(dev)); 128 129 /* 130 * Allocate resources. 131 */ 132 err = at91_spi_activate(dev); 133 if (err) 134 goto out; 135 136#ifdef FDT 137 /* 138 * Disable devices need to hold their resources, so return now and not attach 139 * the spibus, setup interrupt handlers, etc. 140 */ 141 if (!ofw_bus_status_okay(dev)) 142 return 0; 143#endif 144 145 /* 146 * Set up the hardware. 147 */ 148 149 WR4(sc, SPI_CR, SPI_CR_SWRST); 150 /* "Software Reset must be Written Twice" erratum */ 151 WR4(sc, SPI_CR, SPI_CR_SWRST); 152 WR4(sc, SPI_IDR, 0xffffffff); 153 154 WR4(sc, SPI_MR, (0xf << 24) | SPI_MR_MSTR | SPI_MR_MODFDIS | 155 CS_TO_MR(0)); 156 157 /* 158 * For now, run the bus at the slowest speed possible as otherwise we 159 * may encounter data corruption on transmit as seen with ETHERNUT5 160 * and AT45DB321D even though both board and slave device can take 161 * more. 162 * This also serves as a work-around for the "NPCSx rises if no data 163 * data is to be transmitted" erratum. The ideal workaround for the 164 * latter is to take the chip select control away from the peripheral 165 * and manage it directly as a GPIO line. The easy solution is to 166 * slow down the bus so dramatically that it just never gets starved 167 * as may be seen when the OCHI controller is running and consuming 168 * memory and APB bandwidth. 169 * Also, currently we lack a way for lettting both the board and the 170 * slave devices take their maximum supported SPI clocks into account. 171 * Also, we hard-wire SPI mode to 3. 172 */ 173 csr = SPI_CSR_CPOL | (4 << 16) | (0xff << 8); 174 WR4(sc, SPI_CSR0, csr); 175 WR4(sc, SPI_CSR1, csr); 176 WR4(sc, SPI_CSR2, csr); 177 WR4(sc, SPI_CSR3, csr); 178 179 WR4(sc, SPI_CR, SPI_CR_SPIEN); 180 181 WR4(sc, PDC_PTCR, PDC_PTCR_TXTDIS); 182 WR4(sc, PDC_PTCR, PDC_PTCR_RXTDIS); 183 WR4(sc, PDC_RNPR, 0); 184 WR4(sc, PDC_RNCR, 0); 185 WR4(sc, PDC_TNPR, 0); 186 WR4(sc, PDC_TNCR, 0); 187 WR4(sc, PDC_RPR, 0); 188 WR4(sc, PDC_RCR, 0); 189 WR4(sc, PDC_TPR, 0); 190 WR4(sc, PDC_TCR, 0); 191 RD4(sc, SPI_RDR); 192 RD4(sc, SPI_SR); 193 194 device_add_child(dev, "spibus", -1); 195 bus_generic_attach(dev); 196out: 197 if (err) 198 at91_spi_deactivate(dev); 199 return (err); 200} 201 202static int 203at91_spi_detach(device_t dev) 204{ 205 206 return (EBUSY); /* XXX */ 207} 208 209static int 210at91_spi_activate(device_t dev) 211{ 212 struct at91_spi_softc *sc; 213 int err, i, rid; 214 215 sc = device_get_softc(dev); 216 err = ENOMEM; 217 218 rid = 0; 219 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 220 RF_ACTIVE); 221 if (sc->mem_res == NULL) 222 goto out; 223 224 rid = 0; 225 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 226 RF_ACTIVE); 227 if (sc->irq_res == NULL) 228 goto out; 229 err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 230 NULL, at91_spi_intr, sc, &sc->intrhand); 231 if (err != 0) 232 goto out; 233 234 err = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 235 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 2048, 1, 236 2048, BUS_DMA_ALLOCNOW, NULL, NULL, &sc->dmatag); 237 if (err != 0) 238 goto out; 239 240 for (i = 0; i < 4; i++) { 241 err = bus_dmamap_create(sc->dmatag, 0, &sc->map[i]); 242 if (err != 0) 243 goto out; 244 } 245out: 246 if (err != 0) 247 at91_spi_deactivate(dev); 248 return (err); 249} 250 251static void 252at91_spi_deactivate(device_t dev) 253{ 254 struct at91_spi_softc *sc; 255 int i; 256 257 sc = device_get_softc(dev); 258 bus_generic_detach(dev); 259 260 for (i = 0; i < 4; i++) 261 if (sc->map[i]) 262 bus_dmamap_destroy(sc->dmatag, sc->map[i]); 263 264 if (sc->dmatag) 265 bus_dma_tag_destroy(sc->dmatag); 266 267 if (sc->intrhand) 268 bus_teardown_intr(dev, sc->irq_res, sc->intrhand); 269 sc->intrhand = NULL; 270 if (sc->irq_res) 271 bus_release_resource(dev, SYS_RES_IRQ, 272 rman_get_rid(sc->irq_res), sc->irq_res); 273 sc->irq_res = NULL; 274 275 if (sc->mem_res) 276 bus_release_resource(dev, SYS_RES_MEMORY, 277 rman_get_rid(sc->mem_res), sc->mem_res); 278 sc->mem_res = NULL; 279} 280 281static void 282at91_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs __unused, 283 int error) 284{ 285 286 if (error != 0) 287 return; 288 *(bus_addr_t *)arg = segs[0].ds_addr; 289} 290 291static int 292at91_spi_transfer(device_t dev, device_t child, struct spi_command *cmd) 293{ 294 struct at91_spi_softc *sc; 295 bus_addr_t addr; 296 int err, i, j, mode[4]; 297 uint32_t cs; 298 299 KASSERT(cmd->tx_cmd_sz == cmd->rx_cmd_sz, 300 ("%s: TX/RX command sizes should be equal", __func__)); 301 KASSERT(cmd->tx_data_sz == cmd->rx_data_sz, 302 ("%s: TX/RX data sizes should be equal", __func__)); 303 304 /* get the proper chip select */ 305 spibus_get_cs(child, &cs); 306 307 sc = device_get_softc(dev); 308 i = 0; 309 310 sx_xlock(&sc->xfer_mtx); 311 312 /* 313 * Disable transfers while we set things up. 314 */ 315 WR4(sc, PDC_PTCR, PDC_PTCR_TXTDIS | PDC_PTCR_RXTDIS); 316 317 /* 318 * PSCDEC = 0 has a range of 0..3 for chip select. We 319 * don't support PSCDEC = 1 which has a range of 0..15. 320 */ 321 if (cs > 3) { 322 device_printf(dev, 323 "Invalid chip select %d requested by %s\n", cs, 324 device_get_nameunit(child)); 325 err = EINVAL; 326 goto out; 327 } 328 329#ifdef SPI_CHIP_SELECT_HIGH_SUPPORT 330 /* 331 * The AT91RM9200 couldn't do CS high for CS 0. Other chips can, but we 332 * don't support that yet, or other spi modes. 333 */ 334 if (at91_is_rm92() && cs == 0 && 335 (cmd->flags & SPI_CHIP_SELECT_HIGH) != 0) { 336 device_printf(dev, 337 "Invalid chip select high requested by %s for cs 0.\n", 338 device_get_nameunit(child)); 339 err = EINVAL; 340 goto out; 341 } 342#endif 343 err = (RD4(sc, SPI_MR) & ~0x000f0000) | CS_TO_MR(cs); 344 WR4(sc, SPI_MR, err); 345 346 /* 347 * Set up the TX side of the transfer. 348 */ 349 if ((err = bus_dmamap_load(sc->dmatag, sc->map[i], cmd->tx_cmd, 350 cmd->tx_cmd_sz, at91_getaddr, &addr, 0)) != 0) 351 goto out; 352 WR4(sc, PDC_TPR, addr); 353 WR4(sc, PDC_TCR, cmd->tx_cmd_sz); 354 bus_dmamap_sync(sc->dmatag, sc->map[i], BUS_DMASYNC_PREWRITE); 355 mode[i++] = BUS_DMASYNC_POSTWRITE; 356 if (cmd->tx_data_sz > 0) { 357 if ((err = bus_dmamap_load(sc->dmatag, sc->map[i], 358 cmd->tx_data, cmd->tx_data_sz, at91_getaddr, &addr, 0)) != 359 0) 360 goto out; 361 WR4(sc, PDC_TNPR, addr); 362 WR4(sc, PDC_TNCR, cmd->tx_data_sz); 363 bus_dmamap_sync(sc->dmatag, sc->map[i], BUS_DMASYNC_PREWRITE); 364 mode[i++] = BUS_DMASYNC_POSTWRITE; 365 } 366 367 /* 368 * Set up the RX side of the transfer. 369 */ 370 if ((err = bus_dmamap_load(sc->dmatag, sc->map[i], cmd->rx_cmd, 371 cmd->rx_cmd_sz, at91_getaddr, &addr, 0)) != 0) 372 goto out; 373 WR4(sc, PDC_RPR, addr); 374 WR4(sc, PDC_RCR, cmd->rx_cmd_sz); 375 bus_dmamap_sync(sc->dmatag, sc->map[i], BUS_DMASYNC_PREREAD); 376 mode[i++] = BUS_DMASYNC_POSTREAD; 377 if (cmd->rx_data_sz > 0) { 378 if ((err = bus_dmamap_load(sc->dmatag, sc->map[i], 379 cmd->rx_data, cmd->rx_data_sz, at91_getaddr, &addr, 0)) != 380 0) 381 goto out; 382 WR4(sc, PDC_RNPR, addr); 383 WR4(sc, PDC_RNCR, cmd->rx_data_sz); 384 bus_dmamap_sync(sc->dmatag, sc->map[i], BUS_DMASYNC_PREREAD); 385 mode[i++] = BUS_DMASYNC_POSTREAD; 386 } 387 388 /* 389 * Start the transfer, wait for it to complete. 390 */ 391 sc->xfer_done = 0; 392 WR4(sc, SPI_IER, SPI_SR_RXBUFF); 393 WR4(sc, PDC_PTCR, PDC_PTCR_TXTEN | PDC_PTCR_RXTEN); 394 do 395 err = tsleep(&sc->xfer_done, PCATCH | PZERO, "at91_spi", hz); 396 while (sc->xfer_done == 0 && err != EINTR); 397 398 /* 399 * Stop the transfer and clean things up. 400 */ 401 WR4(sc, PDC_PTCR, PDC_PTCR_TXTDIS | PDC_PTCR_RXTDIS); 402 if (err == 0) 403 for (j = 0; j < i; j++) 404 bus_dmamap_sync(sc->dmatag, sc->map[j], mode[j]); 405out: 406 for (j = 0; j < i; j++) 407 bus_dmamap_unload(sc->dmatag, sc->map[j]); 408 409 sx_xunlock(&sc->xfer_mtx); 410 411 return (err); 412} 413 414static void 415at91_spi_intr(void *arg) 416{ 417 struct at91_spi_softc *sc; 418 uint32_t sr; 419 420 sc = (struct at91_spi_softc*)arg; 421 422 sr = RD4(sc, SPI_SR) & RD4(sc, SPI_IMR); 423 if ((sr & SPI_SR_RXBUFF) != 0) { 424 sc->xfer_done = 1; 425 WR4(sc, SPI_IDR, SPI_SR_RXBUFF); 426 wakeup(&sc->xfer_done); 427 } 428 if ((sr & ~SPI_SR_RXBUFF) != 0) { 429 device_printf(sc->dev, "Unexpected ISR %#x\n", sr); 430 WR4(sc, SPI_IDR, sr & ~SPI_SR_RXBUFF); 431 } 432} 433 434static devclass_t at91_spi_devclass; 435 436static device_method_t at91_spi_methods[] = { 437 /* Device interface */ 438 DEVMETHOD(device_probe, at91_spi_probe), 439 DEVMETHOD(device_attach, at91_spi_attach), 440 DEVMETHOD(device_detach, at91_spi_detach), 441 442 /* spibus interface */ 443 DEVMETHOD(spibus_transfer, at91_spi_transfer), 444 445 DEVMETHOD_END 446}; 447 448static driver_t at91_spi_driver = { 449 "spi", 450 at91_spi_methods, 451 sizeof(struct at91_spi_softc), 452}; 453 454#ifdef FDT 455DRIVER_MODULE(at91_spi, simplebus, at91_spi_driver, at91_spi_devclass, NULL, 456 NULL); 457#else 458DRIVER_MODULE(at91_spi, atmelarm, at91_spi_driver, at91_spi_devclass, NULL, 459 NULL); 460#endif 461