at91_smc.h revision 330897 
1/*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2014 M. Warner Losh.  All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 *    notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 *    notice, this list of conditions and the following disclaimer in the
13 *    documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28/* $FreeBSD: stable/11/sys/arm/at91/at91_smc.h 330897 2018-03-14 03:19:51Z eadler $ */
29
30#ifndef ARM_AT91_AT91_SMC_H
31#define ARM_AT91_AT91_SMC_H
32
33/* Registers */
34#define	SMC_SETUP	0x00
35#define SMC_PULSE	0x04
36#define SMC_CYCLE	0x08
37#define	SMC_MODE	0x0C
38
39#define	SMC_CS_OFF(cs)	(0x10 * (cs))
40
41/* Setup */
42#define	SMC_SETUP_NCS_RD_SETUP(x)	((x) << 24)
43#define	SMC_SETUP_NRD_SETUP(x)		((x) << 16)
44#define	SMC_SETUP_NCS_WR_SETUP(x)	((x) << 8)
45#define	SMC_SETUP_NWE_SETUP(x)		(x)
46
47/* Pulse */
48#define	SMC_PULSE_NCS_RD_PULSE(x)	((x) << 24)
49#define	SMC_PULSE_NRD_PULSE(x)		((x) << 16)
50#define	SMC_PULSE_NCS_WR_PULSE(x)	((x) << 8)
51#define	SMC_PULSE_NWE_PULSE(x)		(x)
52
53/* Cycle */
54#define	SMC_CYCLE_NRD_CYCLE(x)		((x) << 16)
55#define	SMC_CYCLE_NWE_CYCLE(x)		(x)
56
57/* Mode */
58#define	SMC_MODE_READ			(1 << 0)
59#define	SMC_MODE_WRITE			(1 << 1)
60#define	SMC_MODE_EXNW_DISABLED		(0 << 4)
61#define	SMC_MODE_EXNW_FROZEN_MODE	(2 << 4)
62#define	SMC_MODE_EXNW_READY_MODE	(3 << 4)
63#define	SMC_MODE_BAT			(1 << 8)
64#define	SMC_MODE_DBW_8BIT		(0 << 12)
65#define	SMC_MODE_DBW_16BIT		(1 << 12)
66#define	SMC_MODE_DBW_32_BIT		(2 << 12)
67#define	SMC_MODE_TDF_CYCLES(x)		((x) << 16)
68#define	SMC_MODE_TDF_MODE		(1 << 20)
69#define	SMC_MODE_PMEN			(1 << 24)
70#define SMC_PS_4BYTE			(0 << 28)
71#define SMC_PS_8BYTE			(1 << 28)
72#define SMC_PS_16BYTE			(2 << 28)
73#define SMC_PS_32BYTE			(3 << 28)
74
75/*
76 * structure to ease init. See the SMC chapter in the datasheet for
77 * the appropriate SoC you are using for details.
78 */
79struct at91_smc_init
80{
81	/* Setup register */
82	uint8_t	ncs_rd_setup;
83	uint8_t nrd_setup;
84	uint8_t ncs_wr_setup;
85	uint8_t nwe_setup;
86
87	/* Pulse register */
88	uint8_t	ncs_rd_pulse;
89	uint8_t nrd_pulse;
90	uint8_t ncs_wr_pulse;
91	uint8_t nwe_pulse;
92
93	/* Cycle register */
94	uint16_t nrd_cycle;
95	uint16_t nwe_cycle;
96
97	/* Mode register */
98	uint8_t mode;		/* Combo of READ/WRITE/EXNW fields */
99	uint8_t bat;
100	uint8_t dwb;
101	uint8_t tdf_cycles;
102	uint8_t tdf_mode;
103	uint8_t pmen;
104	uint8_t ps;
105};
106
107/*
108 * Convenience routine to fill in SMC registers for a given chip select.
109 */
110void at91_smc_setup(int id, int cs, const struct at91_smc_init *smc);
111
112/*
113 * Disable/Enable different External Bus Interfaces (EBI)
114 */
115void at91_ebi_enable(int cs);
116void at91_ebi_disable(int cs);
117
118#endif /* ARM_AT91_AT91_SMC_H */
119