at91_pmc.c revision 331722
1/*- 2 * Copyright (c) 2006 M. Warner Losh. All rights reserved. 3 * Copyright (c) 2010 Greg Ansley. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27#include "opt_platform.h" 28 29#include <sys/cdefs.h> 30__FBSDID("$FreeBSD: stable/11/sys/arm/at91/at91_pmc.c 331722 2018-03-29 02:50:57Z eadler $"); 31 32#include <sys/param.h> 33#include <sys/systm.h> 34#include <sys/kernel.h> 35#include <sys/malloc.h> 36#include <sys/module.h> 37#include <sys/time.h> 38#include <sys/bus.h> 39#include <sys/resource.h> 40#include <sys/rman.h> 41#include <sys/timetc.h> 42 43#include <machine/bus.h> 44#include <machine/resource.h> 45#include <machine/intr.h> 46#include <arm/at91/at91reg.h> 47#include <arm/at91/at91var.h> 48 49#include <arm/at91/at91_pmcreg.h> 50#include <arm/at91/at91_pmcvar.h> 51 52#ifdef FDT 53#include <dev/fdt/fdt_common.h> 54#include <dev/ofw/ofw_bus.h> 55#include <dev/ofw/ofw_bus_subr.h> 56#endif 57 58static struct at91_pmc_softc { 59 bus_space_tag_t sc_st; 60 bus_space_handle_t sc_sh; 61 struct resource *mem_res; /* Memory resource */ 62 device_t dev; 63} *pmc_softc; 64 65static uint32_t pllb_init; 66 67MALLOC_DECLARE(M_PMC); 68MALLOC_DEFINE(M_PMC, "at91_pmc_clocks", "AT91 PMC Clock descriptors"); 69 70#define AT91_PMC_BASE 0xffffc00 71 72static void at91_pmc_set_pllb_mode(struct at91_pmc_clock *, int); 73static void at91_pmc_set_upll_mode(struct at91_pmc_clock *, int); 74static void at91_pmc_set_sys_mode(struct at91_pmc_clock *, int); 75static void at91_pmc_set_periph_mode(struct at91_pmc_clock *, int); 76static void at91_pmc_clock_alias(const char *name, const char *alias); 77 78static struct at91_pmc_clock slck = { 79 .name = "slck", /* 32,768 Hz slow clock */ 80 .hz = 32768, 81 .refcnt = 1, 82 .id = 0, 83 .primary = 1, 84}; 85 86/* 87 * NOTE: Clocks for "ordinary peripheral" devices e.g. spi0, udp0, uhp0 etc. 88 * are now created automatically. Only "system" clocks need be defined here. 89 */ 90static struct at91_pmc_clock main_ck = { 91 .name = "main", /* Main clock */ 92 .refcnt = 0, 93 .id = 1, 94 .primary = 1, 95 .pmc_mask = PMC_IER_MOSCS, 96}; 97 98static struct at91_pmc_clock plla = { 99 .name = "plla", /* PLLA Clock, used for CPU clocking */ 100 .parent = &main_ck, 101 .refcnt = 1, 102 .id = 0, 103 .primary = 1, 104 .pll = 1, 105 .pmc_mask = PMC_IER_LOCKA, 106}; 107 108static struct at91_pmc_clock pllb = { 109 .name = "pllb", /* PLLB Clock, used for USB functions */ 110 .parent = &main_ck, 111 .refcnt = 0, 112 .id = 0, 113 .primary = 1, 114 .pll = 1, 115 .pmc_mask = PMC_IER_LOCKB, 116 .set_mode = &at91_pmc_set_pllb_mode, 117}; 118 119/* Used by USB on at91sam9g45 */ 120static struct at91_pmc_clock upll = { 121 .name = "upll", /* UTMI PLL, used for USB functions on 9G45 family */ 122 .parent = &main_ck, 123 .refcnt = 0, 124 .id = 0, 125 .primary = 1, 126 .pll = 1, 127 .pmc_mask = (1 << 6), 128 .set_mode = &at91_pmc_set_upll_mode, 129}; 130 131static struct at91_pmc_clock udpck = { 132 .name = "udpck", 133 .parent = &pllb, 134 .pmc_mask = PMC_SCER_UDP, 135 .set_mode = at91_pmc_set_sys_mode 136}; 137 138static struct at91_pmc_clock uhpck = { 139 .name = "uhpck", 140 .parent = &pllb, 141 .pmc_mask = PMC_SCER_UHP, 142 .set_mode = at91_pmc_set_sys_mode 143}; 144 145static struct at91_pmc_clock mck = { 146 .name = "mck", /* Master (Peripheral) Clock */ 147 .pmc_mask = PMC_IER_MCKRDY, 148 .refcnt = 0, 149}; 150 151static struct at91_pmc_clock cpu = { 152 .name = "cpu", /* CPU Clock */ 153 .parent = &plla, 154 .pmc_mask = PMC_SCER_PCK, 155 .refcnt = 0, 156}; 157 158/* "+32" or the automatic peripheral clocks */ 159static struct at91_pmc_clock *clock_list[16+32] = { 160 &slck, 161 &main_ck, 162 &plla, 163 &pllb, 164 &upll, 165 &udpck, 166 &uhpck, 167 &mck, 168 &cpu 169}; 170 171static inline uint32_t 172RD4(struct at91_pmc_softc *sc, bus_size_t off) 173{ 174 175 if (sc == NULL) { 176 uint32_t *p = (uint32_t *)(AT91_BASE + AT91_PMC_BASE + off); 177 178 return *p; 179 } 180 return (bus_read_4(sc->mem_res, off)); 181} 182 183static inline void 184WR4(struct at91_pmc_softc *sc, bus_size_t off, uint32_t val) 185{ 186 187 if (sc == NULL) { 188 uint32_t *p = (uint32_t *)(AT91_BASE + AT91_PMC_BASE + off); 189 190 *p = val; 191 } else 192 bus_write_4(sc->mem_res, off, val); 193} 194 195/* 196 * The following is unused currently since we don't ever set the PLLA 197 * frequency of the device. If we did, we'd have to also pay attention 198 * to the ICPLLA bit in the PMC_PLLICPR register for frequencies lower 199 * than ~600MHz, which the PMC code doesn't do right now. 200 */ 201uint32_t 202at91_pmc_800mhz_plla_outb(int freq) 203{ 204 uint32_t outa; 205 206 /* 207 * Set OUTA, per the data sheet. See Table 46-16 titled 208 * PLLA Frequency Regarding ICPLLA and OUTA in the SAM9X25 doc, 209 * Table 46-17 in the SAM9G20 doc, or Table 46-16 in the SAM9G45 doc. 210 * Note: the frequencies overlap by 5MHz, so we add 3 here to 211 * center shoot the transition. 212 */ 213 214 freq /= 1000000; /* MHz */ 215 if (freq >= 800) 216 freq = 800; 217 freq += 3; /* Allow for overlap. */ 218 outa = 3 - ((freq / 50) & 3); /* 750 / 50 = 7, see table */ 219 return (1 << 29)| (outa << 14); 220} 221 222uint32_t 223at91_pmc_800mhz_pllb_outb(int freq) 224{ 225 226 return (0); 227} 228 229void 230at91_pmc_set_pllb_mode(struct at91_pmc_clock *clk, int on) 231{ 232 struct at91_pmc_softc *sc = pmc_softc; 233 uint32_t value; 234 235 value = on ? pllb_init : 0; 236 237 /* 238 * Only write to the register if the value is changing. Besides being 239 * good common sense, this works around RM9200 Errata #26 (CKGR_PLL[AB]R 240 * must not be written with the same value currently in the register). 241 */ 242 if (RD4(sc, CKGR_PLLBR) != value) { 243 WR4(sc, CKGR_PLLBR, value); 244 while (on && (RD4(sc, PMC_SR) & PMC_IER_LOCKB) != PMC_IER_LOCKB) 245 continue; 246 } 247} 248 249static void 250at91_pmc_set_upll_mode(struct at91_pmc_clock *clk, int on) 251{ 252 struct at91_pmc_softc *sc = pmc_softc; 253 uint32_t value; 254 255 if (on) { 256 on = PMC_IER_LOCKU; 257 value = CKGR_UCKR_UPLLEN | CKGR_UCKR_BIASEN; 258 } else 259 value = 0; 260 261 WR4(sc, CKGR_UCKR, RD4(sc, CKGR_UCKR) | value); 262 while ((RD4(sc, PMC_SR) & PMC_IER_LOCKU) != on) 263 continue; 264 265 WR4(sc, PMC_USB, PMC_USB_USBDIV(9) | PMC_USB_USBS); 266 WR4(sc, PMC_SCER, PMC_SCER_UHP_SAM9); 267} 268 269static void 270at91_pmc_set_sys_mode(struct at91_pmc_clock *clk, int on) 271{ 272 struct at91_pmc_softc *sc = pmc_softc; 273 274 WR4(sc, on ? PMC_SCER : PMC_SCDR, clk->pmc_mask); 275 if (on) 276 while ((RD4(sc, PMC_SCSR) & clk->pmc_mask) != clk->pmc_mask) 277 continue; 278 else 279 while ((RD4(sc, PMC_SCSR) & clk->pmc_mask) == clk->pmc_mask) 280 continue; 281} 282 283static void 284at91_pmc_set_periph_mode(struct at91_pmc_clock *clk, int on) 285{ 286 struct at91_pmc_softc *sc = pmc_softc; 287 288 WR4(sc, on ? PMC_PCER : PMC_PCDR, clk->pmc_mask); 289 if (on) 290 while ((RD4(sc, PMC_PCSR) & clk->pmc_mask) != clk->pmc_mask) 291 continue; 292 else 293 while ((RD4(sc, PMC_PCSR) & clk->pmc_mask) == clk->pmc_mask) 294 continue; 295} 296 297struct at91_pmc_clock * 298at91_pmc_clock_add(const char *name, uint32_t irq, 299 struct at91_pmc_clock *parent) 300{ 301 struct at91_pmc_clock *clk; 302 int i, buflen; 303 304 clk = malloc(sizeof(*clk), M_PMC, M_NOWAIT | M_ZERO); 305 if (clk == NULL) 306 goto err; 307 308 buflen = strlen(name) + 1; 309 clk->name = malloc(buflen, M_PMC, M_NOWAIT); 310 if (clk->name == NULL) 311 goto err; 312 313 strlcpy(clk->name, name, buflen); 314 clk->pmc_mask = 1 << irq; 315 clk->set_mode = &at91_pmc_set_periph_mode; 316 if (parent == NULL) 317 clk->parent = &mck; 318 else 319 clk->parent = parent; 320 321 for (i = 0; i < nitems(clock_list); i++) { 322 if (clock_list[i] == NULL) { 323 clock_list[i] = clk; 324 return (clk); 325 } 326 } 327err: 328 if (clk != NULL) { 329 if (clk->name != NULL) 330 free(clk->name, M_PMC); 331 free(clk, M_PMC); 332 } 333 334 panic("could not allocate pmc clock '%s'", name); 335 return (NULL); 336} 337 338static void 339at91_pmc_clock_alias(const char *name, const char *alias) 340{ 341 struct at91_pmc_clock *clk, *alias_clk; 342 343 clk = at91_pmc_clock_ref(name); 344 if (clk) 345 alias_clk = at91_pmc_clock_add(alias, 0, clk->parent); 346 347 if (clk && alias_clk) { 348 alias_clk->hz = clk->hz; 349 alias_clk->pmc_mask = clk->pmc_mask; 350 alias_clk->set_mode = clk->set_mode; 351 } 352} 353 354struct at91_pmc_clock * 355at91_pmc_clock_ref(const char *name) 356{ 357 int i; 358 359 for (i = 0; i < nitems(clock_list); i++) { 360 if (clock_list[i] == NULL) 361 break; 362 if (strcmp(name, clock_list[i]->name) == 0) 363 return (clock_list[i]); 364 } 365 366 return (NULL); 367} 368 369void 370at91_pmc_clock_deref(struct at91_pmc_clock *clk) 371{ 372 if (clk == NULL) 373 return; 374} 375 376void 377at91_pmc_clock_enable(struct at91_pmc_clock *clk) 378{ 379 if (clk == NULL) 380 return; 381 382 /* XXX LOCKING? XXX */ 383 if (clk->parent) 384 at91_pmc_clock_enable(clk->parent); 385 if (clk->refcnt++ == 0 && clk->set_mode) 386 clk->set_mode(clk, 1); 387} 388 389void 390at91_pmc_clock_disable(struct at91_pmc_clock *clk) 391{ 392 if (clk == NULL) 393 return; 394 395 /* XXX LOCKING? XXX */ 396 if (--clk->refcnt == 0 && clk->set_mode) 397 clk->set_mode(clk, 0); 398 if (clk->parent) 399 at91_pmc_clock_disable(clk->parent); 400} 401 402static int 403at91_pmc_pll_rate(struct at91_pmc_clock *clk, uint32_t reg) 404{ 405 uint32_t mul, div, freq; 406 407 freq = clk->parent->hz; 408 div = (reg >> clk->pll_div_shift) & clk->pll_div_mask; 409 mul = (reg >> clk->pll_mul_shift) & clk->pll_mul_mask; 410 411#if 0 412 printf("pll = (%d / %d) * %d = %d\n", 413 freq, div, mul + 1, (freq/div) * (mul+1)); 414#endif 415 416 if (div != 0 && mul != 0) { 417 freq /= div; 418 freq *= mul + 1; 419 } else 420 freq = 0; 421 clk->hz = freq; 422 423 return (freq); 424} 425 426static uint32_t 427at91_pmc_pll_calc(struct at91_pmc_clock *clk, uint32_t out_freq) 428{ 429 uint32_t i, div = 0, mul = 0, diff = 1 << 30; 430 431 unsigned ret = 0x3e00; 432 433 if (out_freq > clk->pll_max_out) 434 goto fail; 435 436 for (i = 1; i < 256; i++) { 437 int32_t diff1; 438 uint32_t input, mul1; 439 440 input = clk->parent->hz / i; 441 if (input < clk->pll_min_in) 442 break; 443 if (input > clk->pll_max_in) 444 continue; 445 446 mul1 = out_freq / input; 447 if (mul1 > (clk->pll_mul_mask + 1)) 448 continue; 449 if (mul1 == 0) 450 break; 451 452 diff1 = out_freq - input * mul1; 453 if (diff1 < 0) 454 diff1 = -diff1; 455 if (diff > diff1) { 456 diff = diff1; 457 div = i; 458 mul = mul1; 459 if (diff == 0) 460 break; 461 } 462 } 463 if (diff > (out_freq >> PMC_PLL_SHIFT_TOL)) 464 goto fail; 465 466 if (clk->set_outb != NULL) 467 ret |= clk->set_outb(out_freq); 468 469 return (ret | 470 ((mul - 1) << clk->pll_mul_shift) | 471 (div << clk->pll_div_shift)); 472fail: 473 return (0); 474} 475 476#if !defined(AT91C_MAIN_CLOCK) 477static const unsigned int at91_main_clock_tbl[] = { 478 3000000, 3276800, 3686400, 3840000, 4000000, 479 4433619, 4915200, 5000000, 5242880, 6000000, 480 6144000, 6400000, 6553600, 7159090, 7372800, 481 7864320, 8000000, 9830400, 10000000, 11059200, 482 12000000, 12288000, 13560000, 14318180, 14745600, 483 16000000, 17344700, 18432000, 20000000 484}; 485#define MAIN_CLOCK_TBL_LEN nitems(at91_main_clock_tbl) 486#endif 487 488static unsigned int 489at91_pmc_sense_main_clock(void) 490{ 491#if !defined(AT91C_MAIN_CLOCK) 492 unsigned int ckgr_val; 493 unsigned int diff, matchdiff, freq; 494 int i; 495 496 ckgr_val = (RD4(NULL, CKGR_MCFR) & CKGR_MCFR_MAINF_MASK) << 11; 497 498 /* 499 * Clocks up to 50MHz can be connected to some models. If 500 * the frequency is >= 21MHz, assume that the slow clock can 501 * measure it correctly, and that any error can be adequately 502 * compensated for by roudning to the nearest 500Hz. Users 503 * with fast, or odd-ball clocks will need to set 504 * AT91C_MAIN_CLOCK in the kernel config file. 505 */ 506 if (ckgr_val >= 21000000) 507 return (rounddown(ckgr_val + 250, 500)); 508 509 /* 510 * Try to find the standard frequency that match best. 511 */ 512 freq = at91_main_clock_tbl[0]; 513 matchdiff = abs(ckgr_val - at91_main_clock_tbl[0]); 514 for (i = 1; i < MAIN_CLOCK_TBL_LEN; i++) { 515 diff = abs(ckgr_val - at91_main_clock_tbl[i]); 516 if (diff < matchdiff) { 517 freq = at91_main_clock_tbl[i]; 518 matchdiff = diff; 519 } 520 } 521 return (freq); 522#else 523 return (AT91C_MAIN_CLOCK); 524#endif 525} 526 527void 528at91_pmc_init_clock(void) 529{ 530 struct at91_pmc_softc *sc = NULL; 531 unsigned int main_clock; 532 uint32_t mckr; 533 uint32_t mdiv; 534 535 soc_info.soc_data->soc_clock_init(); 536 537 main_clock = at91_pmc_sense_main_clock(); 538 539 if (at91_is_sam9() || at91_is_sam9xe()) { 540 uhpck.pmc_mask = PMC_SCER_UHP_SAM9; 541 udpck.pmc_mask = PMC_SCER_UDP_SAM9; 542 } 543 544 /* There is no pllb on AT91SAM9G45 */ 545 if (at91_cpu_is(AT91_T_SAM9G45)) { 546 uhpck.parent = &upll; 547 uhpck.pmc_mask = PMC_SCER_UHP_SAM9; 548 } 549 550 mckr = RD4(sc, PMC_MCKR); 551 main_ck.hz = main_clock; 552 553 /* 554 * Note: this means outa calc code for plla never used since 555 * we never change it. If we did, we'd also have to mind 556 * ICPLLA to get the charge pump current right. 557 */ 558 at91_pmc_pll_rate(&plla, RD4(sc, CKGR_PLLAR)); 559 560 if (at91_cpu_is(AT91_T_SAM9G45) && (mckr & PMC_MCKR_PLLADIV2)) 561 plla.hz /= 2; 562 563 /* 564 * Initialize the usb clock. This sets up pllb, but disables the 565 * actual clock. XXX except for the if 0 :( 566 */ 567 if (!at91_cpu_is(AT91_T_SAM9G45)) { 568 pllb_init = at91_pmc_pll_calc(&pllb, 48000000 * 2) | 0x10000000; 569 at91_pmc_pll_rate(&pllb, pllb_init); 570#if 0 571 /* Turn off USB clocks */ 572 at91_pmc_set_periph_mode(&ohci_clk, 0); 573 at91_pmc_set_periph_mode(&udc_clk, 0); 574#endif 575 } 576 577 if (at91_is_rm92()) { 578 WR4(sc, PMC_SCDR, PMC_SCER_UHP | PMC_SCER_UDP); 579 WR4(sc, PMC_SCER, PMC_SCER_MCKUDP); 580 } else 581 WR4(sc, PMC_SCDR, PMC_SCER_UHP_SAM9 | PMC_SCER_UDP_SAM9); 582 583 /* 584 * MCK and PCU derive from one of the primary clocks. Initialize 585 * this relationship. 586 */ 587 mck.parent = clock_list[mckr & 0x3]; 588 mck.parent->refcnt++; 589 590 cpu.hz = mck.hz = mck.parent->hz / 591 (1 << ((mckr & PMC_MCKR_PRES_MASK) >> 2)); 592 593 mdiv = (mckr & PMC_MCKR_MDIV_MASK) >> 8; 594 if (at91_is_sam9() || at91_is_sam9xe()) { 595 /* 596 * On AT91SAM9G45 when mdiv == 3 we need to divide 597 * MCK by 3 but not, for example, on 9g20. 598 */ 599 if (!at91_cpu_is(AT91_T_SAM9G45) || mdiv <= 2) 600 mdiv *= 2; 601 if (mdiv > 0) 602 mck.hz /= mdiv; 603 } else 604 mck.hz /= (1 + mdiv); 605 606 /* Only found on SAM9G20 */ 607 if (at91_cpu_is(AT91_T_SAM9G20)) 608 cpu.hz /= (mckr & PMC_MCKR_PDIV) ? 2 : 1; 609 610 at91_master_clock = mck.hz; 611 612 /* These clocks refrenced by "special" names */ 613 at91_pmc_clock_alias("ohci0", "ohci_clk"); 614 at91_pmc_clock_alias("udp0", "udp_clk"); 615 616 /* Turn off "Progamable" clocks */ 617 WR4(sc, PMC_SCDR, PMC_SCER_PCK0 | PMC_SCER_PCK1 | PMC_SCER_PCK2 | 618 PMC_SCER_PCK3); 619 620 /* XXX kludge, turn on all peripherals */ 621 WR4(sc, PMC_PCER, 0xffffffff); 622 623 /* Disable all interrupts for PMC */ 624 WR4(sc, PMC_IDR, 0xffffffff); 625} 626 627static void 628at91_pmc_deactivate(device_t dev) 629{ 630 struct at91_pmc_softc *sc; 631 632 sc = device_get_softc(dev); 633 bus_generic_detach(sc->dev); 634 if (sc->mem_res) 635 bus_release_resource(dev, SYS_RES_IOPORT, 636 rman_get_rid(sc->mem_res), sc->mem_res); 637 sc->mem_res = NULL; 638} 639 640static int 641at91_pmc_activate(device_t dev) 642{ 643 struct at91_pmc_softc *sc; 644 int rid; 645 646 sc = device_get_softc(dev); 647 rid = 0; 648 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 649 RF_ACTIVE); 650 if (sc->mem_res == NULL) 651 goto errout; 652 return (0); 653errout: 654 at91_pmc_deactivate(dev); 655 return (ENOMEM); 656} 657 658static int 659at91_pmc_probe(device_t dev) 660{ 661#ifdef FDT 662 if (!ofw_bus_is_compatible(dev, "atmel,at91rm9200-pmc") && 663 !ofw_bus_is_compatible(dev, "atmel,at91sam9260-pmc") && 664 !ofw_bus_is_compatible(dev, "atmel,at91sam9g45-pmc") && 665 !ofw_bus_is_compatible(dev, "atmel,at91sam9x5-pmc")) 666 return (ENXIO); 667#endif 668 device_set_desc(dev, "PMC"); 669 return (0); 670} 671 672static int 673at91_pmc_attach(device_t dev) 674{ 675 int err; 676 677 pmc_softc = device_get_softc(dev); 678 pmc_softc->dev = dev; 679 if ((err = at91_pmc_activate(dev)) != 0) 680 return (err); 681 682 /* 683 * Configure main clock frequency. 684 */ 685 at91_pmc_init_clock(); 686 687 /* 688 * Display info about clocks previously computed 689 */ 690 device_printf(dev, 691 "Primary: %d Hz PLLA: %d MHz CPU: %d MHz MCK: %d MHz\n", 692 main_ck.hz, 693 plla.hz / 1000000, 694 cpu.hz / 1000000, mck.hz / 1000000); 695 696 return (0); 697} 698 699static device_method_t at91_pmc_methods[] = { 700 DEVMETHOD(device_probe, at91_pmc_probe), 701 DEVMETHOD(device_attach, at91_pmc_attach), 702 DEVMETHOD_END 703}; 704 705static driver_t at91_pmc_driver = { 706 "at91_pmc", 707 at91_pmc_methods, 708 sizeof(struct at91_pmc_softc), 709}; 710static devclass_t at91_pmc_devclass; 711 712#ifdef FDT 713EARLY_DRIVER_MODULE(at91_pmc, simplebus, at91_pmc_driver, at91_pmc_devclass, 714 NULL, NULL, BUS_PASS_CPU); 715#else 716EARLY_DRIVER_MODULE(at91_pmc, atmelarm, at91_pmc_driver, at91_pmc_devclass, 717 NULL, NULL, BUS_PASS_CPU); 718#endif 719