mp_machdep.c revision 307344
1/*- 2 * Copyright (c) 2011 Semihalf. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26#include "opt_ddb.h" 27#include "opt_smp.h" 28 29#include <sys/cdefs.h> 30__FBSDID("$FreeBSD: stable/11/sys/arm/arm/mp_machdep.c 307344 2016-10-15 08:27:54Z mmel $"); 31#include <sys/param.h> 32#include <sys/systm.h> 33#include <sys/bus.h> 34#include <sys/kernel.h> 35#include <sys/lock.h> 36#include <sys/mutex.h> 37#include <sys/proc.h> 38#include <sys/pcpu.h> 39#include <sys/sched.h> 40#include <sys/smp.h> 41#include <sys/ktr.h> 42#include <sys/malloc.h> 43 44#include <vm/vm.h> 45#include <vm/vm_extern.h> 46#include <vm/vm_kern.h> 47#include <vm/pmap.h> 48 49#include <machine/armreg.h> 50#include <machine/cpu.h> 51#include <machine/cpufunc.h> 52#include <machine/debug_monitor.h> 53#include <machine/smp.h> 54#include <machine/pcb.h> 55#include <machine/physmem.h> 56#include <machine/intr.h> 57#include <machine/vmparam.h> 58#ifdef VFP 59#include <machine/vfp.h> 60#endif 61#ifdef CPU_MV_PJ4B 62#include <arm/mv/mvwin.h> 63#include <dev/fdt/fdt_common.h> 64#endif 65 66extern struct pcpu __pcpu[]; 67/* used to hold the AP's until we are ready to release them */ 68struct mtx ap_boot_mtx; 69struct pcb stoppcbs[MAXCPU]; 70 71/* # of Applications processors */ 72volatile int mp_naps; 73 74/* Set to 1 once we're ready to let the APs out of the pen. */ 75volatile int aps_ready = 0; 76 77#ifndef INTRNG 78static int ipi_handler(void *arg); 79#endif 80void set_stackptrs(int cpu); 81 82/* Temporary variables for init_secondary() */ 83void *dpcpu[MAXCPU - 1]; 84 85/* Determine if we running MP machine */ 86int 87cpu_mp_probe(void) 88{ 89 90 KASSERT(mp_ncpus != 0, ("cpu_mp_probe: mp_ncpus is unset")); 91 92 CPU_SETOF(0, &all_cpus); 93 94 return (mp_ncpus > 1); 95} 96 97/* Start Application Processor via platform specific function */ 98static int 99check_ap(void) 100{ 101 uint32_t ms; 102 103 for (ms = 0; ms < 2000; ++ms) { 104 if ((mp_naps + 1) == mp_ncpus) 105 return (0); /* success */ 106 else 107 DELAY(1000); 108 } 109 110 return (-2); 111} 112 113extern unsigned char _end[]; 114 115/* Initialize and fire up non-boot processors */ 116void 117cpu_mp_start(void) 118{ 119 int error, i; 120 121 mtx_init(&ap_boot_mtx, "ap boot", NULL, MTX_SPIN); 122 123 /* Reserve memory for application processors */ 124 for(i = 0; i < (mp_ncpus - 1); i++) 125 dpcpu[i] = (void *)kmem_malloc(kernel_arena, DPCPU_SIZE, 126 M_WAITOK | M_ZERO); 127 128 dcache_wbinv_poc_all(); 129 130 /* Initialize boot code and start up processors */ 131 platform_mp_start_ap(); 132 133 /* Check if ap's started properly */ 134 error = check_ap(); 135 if (error) 136 printf("WARNING: Some AP's failed to start\n"); 137 else 138 for (i = 1; i < mp_ncpus; i++) 139 CPU_SET(i, &all_cpus); 140} 141 142/* Introduce rest of cores to the world */ 143void 144cpu_mp_announce(void) 145{ 146 147} 148 149extern vm_paddr_t pmap_pa; 150void 151init_secondary(int cpu) 152{ 153 struct pcpu *pc; 154 uint32_t loop_counter; 155#ifndef INTRNG 156 int start = 0, end = 0; 157#endif 158 uint32_t actlr_mask, actlr_set; 159 160 pmap_set_tex(); 161 cpuinfo_get_actlr_modifier(&actlr_mask, &actlr_set); 162 reinit_mmu(pmap_kern_ttb, actlr_mask, actlr_set); 163 cpu_setup(); 164 165 /* Provide stack pointers for other processor modes. */ 166 set_stackptrs(cpu); 167 168 enable_interrupts(PSR_A); 169 pc = &__pcpu[cpu]; 170 171 /* 172 * pcpu_init() updates queue, so it should not be executed in parallel 173 * on several cores 174 */ 175 while(mp_naps < (cpu - 1)) 176 ; 177 178 pcpu_init(pc, cpu, sizeof(struct pcpu)); 179 dpcpu_init(dpcpu[cpu - 1], cpu); 180#if __ARM_ARCH >= 6 && defined(DDB) 181 dbg_monitor_init_secondary(); 182#endif 183 /* Signal our startup to BSP */ 184 atomic_add_rel_32(&mp_naps, 1); 185 186 /* Spin until the BSP releases the APs */ 187 while (!atomic_load_acq_int(&aps_ready)) { 188#if __ARM_ARCH >= 7 189 __asm __volatile("wfe"); 190#endif 191 } 192 193 /* Initialize curthread */ 194 KASSERT(PCPU_GET(idlethread) != NULL, ("no idle thread")); 195 pc->pc_curthread = pc->pc_idlethread; 196 pc->pc_curpcb = pc->pc_idlethread->td_pcb; 197 set_curthread(pc->pc_idlethread); 198#ifdef VFP 199 vfp_init(); 200#endif 201 202 /* Configure the interrupt controller */ 203 intr_pic_init_secondary(); 204 205 mtx_lock_spin(&ap_boot_mtx); 206 207 atomic_add_rel_32(&smp_cpus, 1); 208 209 if (smp_cpus == mp_ncpus) { 210 /* enable IPI's, tlb shootdown, freezes etc */ 211 atomic_store_rel_int(&smp_started, 1); 212 } 213 214 mtx_unlock_spin(&ap_boot_mtx); 215 216#ifndef INTRNG 217 /* Enable ipi */ 218#ifdef IPI_IRQ_START 219 start = IPI_IRQ_START; 220#ifdef IPI_IRQ_END 221 end = IPI_IRQ_END; 222#else 223 end = IPI_IRQ_START; 224#endif 225#endif 226 227 for (int i = start; i <= end; i++) 228 arm_unmask_irq(i); 229#endif /* INTRNG */ 230 enable_interrupts(PSR_I); 231 232 loop_counter = 0; 233 while (smp_started == 0) { 234 DELAY(100); 235 loop_counter++; 236 if (loop_counter == 1000) 237 CTR0(KTR_SMP, "AP still wait for smp_started"); 238 } 239 /* Start per-CPU event timers. */ 240 cpu_initclocks_ap(); 241 242 CTR0(KTR_SMP, "go into scheduler"); 243 244 /* Enter the scheduler */ 245 sched_throw(NULL); 246 247 panic("scheduler returned us to %s", __func__); 248 /* NOTREACHED */ 249} 250 251#ifdef INTRNG 252static void 253ipi_rendezvous(void *dummy __unused) 254{ 255 256 CTR0(KTR_SMP, "IPI_RENDEZVOUS"); 257 smp_rendezvous_action(); 258} 259 260static void 261ipi_ast(void *dummy __unused) 262{ 263 264 CTR0(KTR_SMP, "IPI_AST"); 265} 266 267static void 268ipi_stop(void *dummy __unused) 269{ 270 u_int cpu; 271 272 /* 273 * IPI_STOP_HARD is mapped to IPI_STOP. 274 */ 275 CTR0(KTR_SMP, "IPI_STOP or IPI_STOP_HARD"); 276 277 cpu = PCPU_GET(cpuid); 278 savectx(&stoppcbs[cpu]); 279 280 /* 281 * CPUs are stopped when entering the debugger and at 282 * system shutdown, both events which can precede a 283 * panic dump. For the dump to be correct, all caches 284 * must be flushed and invalidated, but on ARM there's 285 * no way to broadcast a wbinv_all to other cores. 286 * Instead, we have each core do the local wbinv_all as 287 * part of stopping the core. The core requesting the 288 * stop will do the l2 cache flush after all other cores 289 * have done their l1 flushes and stopped. 290 */ 291 dcache_wbinv_poc_all(); 292 293 /* Indicate we are stopped */ 294 CPU_SET_ATOMIC(cpu, &stopped_cpus); 295 296 /* Wait for restart */ 297 while (!CPU_ISSET(cpu, &started_cpus)) 298 cpu_spinwait(); 299 300 CPU_CLR_ATOMIC(cpu, &started_cpus); 301 CPU_CLR_ATOMIC(cpu, &stopped_cpus); 302#ifdef DDB 303 dbg_resume_dbreg(); 304#endif 305 CTR0(KTR_SMP, "IPI_STOP (restart)"); 306} 307 308static void 309ipi_preempt(void *arg) 310{ 311 struct trapframe *oldframe; 312 struct thread *td; 313 314 critical_enter(); 315 td = curthread; 316 td->td_intr_nesting_level++; 317 oldframe = td->td_intr_frame; 318 td->td_intr_frame = (struct trapframe *)arg; 319 320 CTR1(KTR_SMP, "%s: IPI_PREEMPT", __func__); 321 sched_preempt(td); 322 323 td->td_intr_frame = oldframe; 324 td->td_intr_nesting_level--; 325 critical_exit(); 326} 327 328static void 329ipi_hardclock(void *arg) 330{ 331 struct trapframe *oldframe; 332 struct thread *td; 333 334 critical_enter(); 335 td = curthread; 336 td->td_intr_nesting_level++; 337 oldframe = td->td_intr_frame; 338 td->td_intr_frame = (struct trapframe *)arg; 339 340 CTR1(KTR_SMP, "%s: IPI_HARDCLOCK", __func__); 341 hardclockintr(); 342 343 td->td_intr_frame = oldframe; 344 td->td_intr_nesting_level--; 345 critical_exit(); 346} 347 348#else 349static int 350ipi_handler(void *arg) 351{ 352 u_int cpu, ipi; 353 354 cpu = PCPU_GET(cpuid); 355 356 ipi = pic_ipi_read((int)arg); 357 358 while ((ipi != 0x3ff)) { 359 switch (ipi) { 360 case IPI_RENDEZVOUS: 361 CTR0(KTR_SMP, "IPI_RENDEZVOUS"); 362 smp_rendezvous_action(); 363 break; 364 365 case IPI_AST: 366 CTR0(KTR_SMP, "IPI_AST"); 367 break; 368 369 case IPI_STOP: 370 /* 371 * IPI_STOP_HARD is mapped to IPI_STOP so it is not 372 * necessary to add it in the switch. 373 */ 374 CTR0(KTR_SMP, "IPI_STOP or IPI_STOP_HARD"); 375 376 savectx(&stoppcbs[cpu]); 377 378 /* 379 * CPUs are stopped when entering the debugger and at 380 * system shutdown, both events which can precede a 381 * panic dump. For the dump to be correct, all caches 382 * must be flushed and invalidated, but on ARM there's 383 * no way to broadcast a wbinv_all to other cores. 384 * Instead, we have each core do the local wbinv_all as 385 * part of stopping the core. The core requesting the 386 * stop will do the l2 cache flush after all other cores 387 * have done their l1 flushes and stopped. 388 */ 389 dcache_wbinv_poc_all(); 390 391 /* Indicate we are stopped */ 392 CPU_SET_ATOMIC(cpu, &stopped_cpus); 393 394 /* Wait for restart */ 395 while (!CPU_ISSET(cpu, &started_cpus)) 396 cpu_spinwait(); 397 398 CPU_CLR_ATOMIC(cpu, &started_cpus); 399 CPU_CLR_ATOMIC(cpu, &stopped_cpus); 400#ifdef DDB 401 dbg_resume_dbreg(); 402#endif 403 CTR0(KTR_SMP, "IPI_STOP (restart)"); 404 break; 405 case IPI_PREEMPT: 406 CTR1(KTR_SMP, "%s: IPI_PREEMPT", __func__); 407 sched_preempt(curthread); 408 break; 409 case IPI_HARDCLOCK: 410 CTR1(KTR_SMP, "%s: IPI_HARDCLOCK", __func__); 411 hardclockintr(); 412 break; 413 default: 414 panic("Unknown IPI 0x%0x on cpu %d", ipi, curcpu); 415 } 416 417 pic_ipi_clear(ipi); 418 ipi = pic_ipi_read(-1); 419 } 420 421 return (FILTER_HANDLED); 422} 423#endif 424 425static void 426release_aps(void *dummy __unused) 427{ 428 uint32_t loop_counter; 429#ifndef INTRNG 430 int start = 0, end = 0; 431#endif 432 433 if (mp_ncpus == 1) 434 return; 435 436#ifdef INTRNG 437 intr_pic_ipi_setup(IPI_RENDEZVOUS, "rendezvous", ipi_rendezvous, NULL); 438 intr_pic_ipi_setup(IPI_AST, "ast", ipi_ast, NULL); 439 intr_pic_ipi_setup(IPI_STOP, "stop", ipi_stop, NULL); 440 intr_pic_ipi_setup(IPI_PREEMPT, "preempt", ipi_preempt, NULL); 441 intr_pic_ipi_setup(IPI_HARDCLOCK, "hardclock", ipi_hardclock, NULL); 442#else 443#ifdef IPI_IRQ_START 444 start = IPI_IRQ_START; 445#ifdef IPI_IRQ_END 446 end = IPI_IRQ_END; 447#else 448 end = IPI_IRQ_START; 449#endif 450#endif 451 452 for (int i = start; i <= end; i++) { 453 /* 454 * IPI handler 455 */ 456 /* 457 * Use 0xdeadbeef as the argument value for irq 0, 458 * if we used 0, the intr code will give the trap frame 459 * pointer instead. 460 */ 461 arm_setup_irqhandler("ipi", ipi_handler, NULL, (void *)i, i, 462 INTR_TYPE_MISC | INTR_EXCL, NULL); 463 464 /* Enable ipi */ 465 arm_unmask_irq(i); 466 } 467#endif 468 atomic_store_rel_int(&aps_ready, 1); 469 /* Wake the other threads up */ 470 dsb(); 471 sev(); 472 473 printf("Release APs\n"); 474 475 for (loop_counter = 0; loop_counter < 2000; loop_counter++) { 476 if (smp_started) 477 return; 478 DELAY(1000); 479 } 480 printf("AP's not started\n"); 481} 482 483SYSINIT(start_aps, SI_SUB_SMP, SI_ORDER_FIRST, release_aps, NULL); 484 485struct cpu_group * 486cpu_topo(void) 487{ 488 489 return (smp_topo_1level(CG_SHARE_L2, mp_ncpus, 0)); 490} 491 492void 493cpu_mp_setmaxid(void) 494{ 495 496 platform_mp_setmaxid(); 497} 498 499/* Sending IPI */ 500void 501ipi_all_but_self(u_int ipi) 502{ 503 cpuset_t other_cpus; 504 505 other_cpus = all_cpus; 506 CPU_CLR(PCPU_GET(cpuid), &other_cpus); 507 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi); 508#ifdef INTRNG 509 intr_ipi_send(other_cpus, ipi); 510#else 511 pic_ipi_send(other_cpus, ipi); 512#endif 513} 514 515void 516ipi_cpu(int cpu, u_int ipi) 517{ 518 cpuset_t cpus; 519 520 CPU_ZERO(&cpus); 521 CPU_SET(cpu, &cpus); 522 523 CTR3(KTR_SMP, "%s: cpu: %d, ipi: %x", __func__, cpu, ipi); 524#ifdef INTRNG 525 intr_ipi_send(cpus, ipi); 526#else 527 pic_ipi_send(cpus, ipi); 528#endif 529} 530 531void 532ipi_selected(cpuset_t cpus, u_int ipi) 533{ 534 535 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi); 536#ifdef INTRNG 537 intr_ipi_send(cpus, ipi); 538#else 539 pic_ipi_send(cpus, ipi); 540#endif 541} 542