if_awg.c revision 329648
1/*- 2 * Copyright (c) 2016 Jared McNeill <jmcneill@invisible.ca> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 19 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 20 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 21 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 22 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: stable/11/sys/arm/allwinner/if_awg.c 329648 2018-02-20 18:12:07Z gonzo $ 27 */ 28 29/* 30 * Allwinner Gigabit Ethernet MAC (EMAC) controller 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: stable/11/sys/arm/allwinner/if_awg.c 329648 2018-02-20 18:12:07Z gonzo $"); 35 36#include <sys/param.h> 37#include <sys/systm.h> 38#include <sys/bus.h> 39#include <sys/rman.h> 40#include <sys/kernel.h> 41#include <sys/endian.h> 42#include <sys/mbuf.h> 43#include <sys/socket.h> 44#include <sys/sockio.h> 45#include <sys/module.h> 46#include <sys/taskqueue.h> 47 48#include <net/bpf.h> 49#include <net/if.h> 50#include <net/ethernet.h> 51#include <net/if_dl.h> 52#include <net/if_media.h> 53#include <net/if_types.h> 54#include <net/if_var.h> 55 56#include <machine/bus.h> 57 58#include <dev/ofw/ofw_bus.h> 59#include <dev/ofw/ofw_bus_subr.h> 60 61#include <arm/allwinner/if_awgreg.h> 62#include <dev/mii/mii.h> 63#include <dev/mii/miivar.h> 64 65#include <dev/extres/clk/clk.h> 66#include <dev/extres/hwreset/hwreset.h> 67#include <dev/extres/regulator/regulator.h> 68 69#include "miibus_if.h" 70 71#define RD4(sc, reg) bus_read_4((sc)->res[0], (reg)) 72#define WR4(sc, reg, val) bus_write_4((sc)->res[0], (reg), (val)) 73 74#define AWG_LOCK(sc) mtx_lock(&(sc)->mtx) 75#define AWG_UNLOCK(sc) mtx_unlock(&(sc)->mtx); 76#define AWG_ASSERT_LOCKED(sc) mtx_assert(&(sc)->mtx, MA_OWNED) 77#define AWG_ASSERT_UNLOCKED(sc) mtx_assert(&(sc)->mtx, MA_NOTOWNED) 78 79#define DESC_ALIGN 4 80#define TX_DESC_COUNT 256 81#define TX_DESC_SIZE (sizeof(struct emac_desc) * TX_DESC_COUNT) 82#define RX_DESC_COUNT 256 83#define RX_DESC_SIZE (sizeof(struct emac_desc) * RX_DESC_COUNT) 84 85#define DESC_OFF(n) ((n) * sizeof(struct emac_desc)) 86#define TX_NEXT(n) (((n) + 1) & (TX_DESC_COUNT - 1)) 87#define TX_SKIP(n, o) (((n) + (o)) & (TX_DESC_COUNT - 1)) 88#define RX_NEXT(n) (((n) + 1) & (RX_DESC_COUNT - 1)) 89 90#define TX_MAX_SEGS 20 91 92#define SOFT_RST_RETRY 1000 93#define MII_BUSY_RETRY 1000 94#define MDIO_FREQ 2500000 95 96#define BURST_LEN_DEFAULT 8 97#define RX_TX_PRI_DEFAULT 0 98#define PAUSE_TIME_DEFAULT 0x400 99#define TX_INTERVAL_DEFAULT 64 100 101/* Burst length of RX and TX DMA transfers */ 102static int awg_burst_len = BURST_LEN_DEFAULT; 103TUNABLE_INT("hw.awg.burst_len", &awg_burst_len); 104 105/* RX / TX DMA priority. If 1, RX DMA has priority over TX DMA. */ 106static int awg_rx_tx_pri = RX_TX_PRI_DEFAULT; 107TUNABLE_INT("hw.awg.rx_tx_pri", &awg_rx_tx_pri); 108 109/* Pause time field in the transmitted control frame */ 110static int awg_pause_time = PAUSE_TIME_DEFAULT; 111TUNABLE_INT("hw.awg.pause_time", &awg_pause_time); 112 113/* Request a TX interrupt every <n> descriptors */ 114static int awg_tx_interval = TX_INTERVAL_DEFAULT; 115TUNABLE_INT("hw.awg.tx_interval", &awg_tx_interval); 116 117static struct ofw_compat_data compat_data[] = { 118 { "allwinner,sun8i-a83t-emac", 1 }, 119 { NULL, 0 } 120}; 121 122struct awg_bufmap { 123 bus_dmamap_t map; 124 struct mbuf *mbuf; 125}; 126 127struct awg_txring { 128 bus_dma_tag_t desc_tag; 129 bus_dmamap_t desc_map; 130 struct emac_desc *desc_ring; 131 bus_addr_t desc_ring_paddr; 132 bus_dma_tag_t buf_tag; 133 struct awg_bufmap buf_map[TX_DESC_COUNT]; 134 u_int cur, next, queued; 135}; 136 137struct awg_rxring { 138 bus_dma_tag_t desc_tag; 139 bus_dmamap_t desc_map; 140 struct emac_desc *desc_ring; 141 bus_addr_t desc_ring_paddr; 142 bus_dma_tag_t buf_tag; 143 struct awg_bufmap buf_map[RX_DESC_COUNT]; 144 u_int cur; 145}; 146 147struct awg_softc { 148 struct resource *res[2]; 149 struct mtx mtx; 150 if_t ifp; 151 device_t dev; 152 device_t miibus; 153 struct callout stat_ch; 154 struct task link_task; 155 void *ih; 156 u_int mdc_div_ratio_m; 157 int link; 158 int if_flags; 159 160 struct awg_txring tx; 161 struct awg_rxring rx; 162}; 163 164static struct resource_spec awg_spec[] = { 165 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 166 { SYS_RES_IRQ, 0, RF_ACTIVE }, 167 { -1, 0 } 168}; 169 170static int 171awg_miibus_readreg(device_t dev, int phy, int reg) 172{ 173 struct awg_softc *sc; 174 int retry, val; 175 176 sc = device_get_softc(dev); 177 val = 0; 178 179 WR4(sc, EMAC_MII_CMD, 180 (sc->mdc_div_ratio_m << MDC_DIV_RATIO_M_SHIFT) | 181 (phy << PHY_ADDR_SHIFT) | 182 (reg << PHY_REG_ADDR_SHIFT) | 183 MII_BUSY); 184 for (retry = MII_BUSY_RETRY; retry > 0; retry--) { 185 if ((RD4(sc, EMAC_MII_CMD) & MII_BUSY) == 0) { 186 val = RD4(sc, EMAC_MII_DATA); 187 break; 188 } 189 DELAY(10); 190 } 191 192 if (retry == 0) 193 device_printf(dev, "phy read timeout, phy=%d reg=%d\n", 194 phy, reg); 195 196 return (val); 197} 198 199static int 200awg_miibus_writereg(device_t dev, int phy, int reg, int val) 201{ 202 struct awg_softc *sc; 203 int retry; 204 205 sc = device_get_softc(dev); 206 207 WR4(sc, EMAC_MII_DATA, val); 208 WR4(sc, EMAC_MII_CMD, 209 (sc->mdc_div_ratio_m << MDC_DIV_RATIO_M_SHIFT) | 210 (phy << PHY_ADDR_SHIFT) | 211 (reg << PHY_REG_ADDR_SHIFT) | 212 MII_WR | MII_BUSY); 213 for (retry = MII_BUSY_RETRY; retry > 0; retry--) { 214 if ((RD4(sc, EMAC_MII_CMD) & MII_BUSY) == 0) 215 break; 216 DELAY(10); 217 } 218 219 if (retry == 0) 220 device_printf(dev, "phy write timeout, phy=%d reg=%d\n", 221 phy, reg); 222 223 return (0); 224} 225 226static void 227awg_update_link_locked(struct awg_softc *sc) 228{ 229 struct mii_data *mii; 230 uint32_t val; 231 232 AWG_ASSERT_LOCKED(sc); 233 234 if ((if_getdrvflags(sc->ifp) & IFF_DRV_RUNNING) == 0) 235 return; 236 mii = device_get_softc(sc->miibus); 237 238 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 239 (IFM_ACTIVE | IFM_AVALID)) { 240 switch (IFM_SUBTYPE(mii->mii_media_active)) { 241 case IFM_1000_T: 242 case IFM_1000_SX: 243 case IFM_100_TX: 244 case IFM_10_T: 245 sc->link = 1; 246 break; 247 default: 248 sc->link = 0; 249 break; 250 } 251 } else 252 sc->link = 0; 253 254 if (sc->link == 0) 255 return; 256 257 val = RD4(sc, EMAC_BASIC_CTL_0); 258 val &= ~(BASIC_CTL_SPEED | BASIC_CTL_DUPLEX); 259 260 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 261 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 262 val |= BASIC_CTL_SPEED_1000 << BASIC_CTL_SPEED_SHIFT; 263 else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) 264 val |= BASIC_CTL_SPEED_100 << BASIC_CTL_SPEED_SHIFT; 265 else 266 val |= BASIC_CTL_SPEED_10 << BASIC_CTL_SPEED_SHIFT; 267 268 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 269 val |= BASIC_CTL_DUPLEX; 270 271 WR4(sc, EMAC_BASIC_CTL_0, val); 272 273 val = RD4(sc, EMAC_RX_CTL_0); 274 val &= ~RX_FLOW_CTL_EN; 275 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 276 val |= RX_FLOW_CTL_EN; 277 WR4(sc, EMAC_RX_CTL_0, val); 278 279 val = RD4(sc, EMAC_TX_FLOW_CTL); 280 val &= ~(PAUSE_TIME|TX_FLOW_CTL_EN); 281 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 282 val |= TX_FLOW_CTL_EN; 283 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 284 val |= awg_pause_time << PAUSE_TIME_SHIFT; 285 WR4(sc, EMAC_TX_FLOW_CTL, val); 286} 287 288static void 289awg_link_task(void *arg, int pending) 290{ 291 struct awg_softc *sc; 292 293 sc = arg; 294 295 AWG_LOCK(sc); 296 awg_update_link_locked(sc); 297 AWG_UNLOCK(sc); 298} 299 300static void 301awg_miibus_statchg(device_t dev) 302{ 303 struct awg_softc *sc; 304 305 sc = device_get_softc(dev); 306 307 taskqueue_enqueue(taskqueue_swi, &sc->link_task); 308} 309 310static void 311awg_media_status(if_t ifp, struct ifmediareq *ifmr) 312{ 313 struct awg_softc *sc; 314 struct mii_data *mii; 315 316 sc = if_getsoftc(ifp); 317 mii = device_get_softc(sc->miibus); 318 319 AWG_LOCK(sc); 320 mii_pollstat(mii); 321 ifmr->ifm_active = mii->mii_media_active; 322 ifmr->ifm_status = mii->mii_media_status; 323 AWG_UNLOCK(sc); 324} 325 326static int 327awg_media_change(if_t ifp) 328{ 329 struct awg_softc *sc; 330 struct mii_data *mii; 331 int error; 332 333 sc = if_getsoftc(ifp); 334 mii = device_get_softc(sc->miibus); 335 336 AWG_LOCK(sc); 337 error = mii_mediachg(mii); 338 AWG_UNLOCK(sc); 339 340 return (error); 341} 342 343static void 344awg_setup_txdesc(struct awg_softc *sc, int index, int flags, bus_addr_t paddr, 345 u_int len) 346{ 347 uint32_t status, size; 348 349 if (paddr == 0 || len == 0) { 350 status = 0; 351 size = 0; 352 --sc->tx.queued; 353 } else { 354 status = TX_DESC_CTL; 355 size = flags | len; 356 if ((index & (awg_tx_interval - 1)) == 0) 357 size |= htole32(TX_INT_CTL); 358 ++sc->tx.queued; 359 } 360 361 sc->tx.desc_ring[index].addr = htole32((uint32_t)paddr); 362 sc->tx.desc_ring[index].size = htole32(size); 363 sc->tx.desc_ring[index].status = htole32(status); 364} 365 366static int 367awg_setup_txbuf(struct awg_softc *sc, int index, struct mbuf **mp) 368{ 369 bus_dma_segment_t segs[TX_MAX_SEGS]; 370 int error, nsegs, cur, i, flags; 371 u_int csum_flags; 372 struct mbuf *m; 373 374 m = *mp; 375 error = bus_dmamap_load_mbuf_sg(sc->tx.buf_tag, 376 sc->tx.buf_map[index].map, m, segs, &nsegs, BUS_DMA_NOWAIT); 377 if (error == EFBIG) { 378 m = m_collapse(m, M_NOWAIT, TX_MAX_SEGS); 379 if (m == NULL) { 380 device_printf(sc->dev, "awg_setup_txbuf: m_collapse failed\n"); 381 return (0); 382 } 383 *mp = m; 384 error = bus_dmamap_load_mbuf_sg(sc->tx.buf_tag, 385 sc->tx.buf_map[index].map, m, segs, &nsegs, BUS_DMA_NOWAIT); 386 } 387 if (error != 0) { 388 device_printf(sc->dev, "awg_setup_txbuf: bus_dmamap_load_mbuf_sg failed\n"); 389 return (0); 390 } 391 392 bus_dmamap_sync(sc->tx.buf_tag, sc->tx.buf_map[index].map, 393 BUS_DMASYNC_PREWRITE); 394 395 flags = TX_FIR_DESC; 396 if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0) { 397 if ((m->m_pkthdr.csum_flags & (CSUM_TCP|CSUM_UDP)) != 0) 398 csum_flags = TX_CHECKSUM_CTL_FULL; 399 else 400 csum_flags = TX_CHECKSUM_CTL_IP; 401 flags |= (csum_flags << TX_CHECKSUM_CTL_SHIFT); 402 } 403 404 for (cur = index, i = 0; i < nsegs; i++) { 405 sc->tx.buf_map[cur].mbuf = (i == 0 ? m : NULL); 406 if (i == nsegs - 1) 407 flags |= TX_LAST_DESC; 408 awg_setup_txdesc(sc, cur, flags, segs[i].ds_addr, 409 segs[i].ds_len); 410 flags &= ~TX_FIR_DESC; 411 cur = TX_NEXT(cur); 412 } 413 414 return (nsegs); 415} 416 417static void 418awg_setup_rxdesc(struct awg_softc *sc, int index, bus_addr_t paddr) 419{ 420 uint32_t status, size; 421 422 status = RX_DESC_CTL; 423 size = MCLBYTES - 1; 424 425 sc->rx.desc_ring[index].addr = htole32((uint32_t)paddr); 426 sc->rx.desc_ring[index].size = htole32(size); 427 sc->rx.desc_ring[index].next = 428 htole32(sc->rx.desc_ring_paddr + DESC_OFF(RX_NEXT(index))); 429 sc->rx.desc_ring[index].status = htole32(status); 430} 431 432static int 433awg_setup_rxbuf(struct awg_softc *sc, int index, struct mbuf *m) 434{ 435 bus_dma_segment_t seg; 436 int error, nsegs; 437 438 m_adj(m, ETHER_ALIGN); 439 440 error = bus_dmamap_load_mbuf_sg(sc->rx.buf_tag, 441 sc->rx.buf_map[index].map, m, &seg, &nsegs, 0); 442 if (error != 0) 443 return (error); 444 445 bus_dmamap_sync(sc->rx.buf_tag, sc->rx.buf_map[index].map, 446 BUS_DMASYNC_PREREAD); 447 448 sc->rx.buf_map[index].mbuf = m; 449 awg_setup_rxdesc(sc, index, seg.ds_addr); 450 451 return (0); 452} 453 454static struct mbuf * 455awg_alloc_mbufcl(struct awg_softc *sc) 456{ 457 struct mbuf *m; 458 459 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 460 if (m != NULL) 461 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 462 463 return (m); 464} 465 466static void 467awg_start_locked(struct awg_softc *sc) 468{ 469 struct mbuf *m; 470 uint32_t val; 471 if_t ifp; 472 int cnt, nsegs; 473 474 AWG_ASSERT_LOCKED(sc); 475 476 if (!sc->link) 477 return; 478 479 ifp = sc->ifp; 480 481 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING|IFF_DRV_OACTIVE)) != 482 IFF_DRV_RUNNING) 483 return; 484 485 for (cnt = 0; ; cnt++) { 486 if (sc->tx.queued >= TX_DESC_COUNT - TX_MAX_SEGS) { 487 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 488 break; 489 } 490 491 m = if_dequeue(ifp); 492 if (m == NULL) 493 break; 494 495 nsegs = awg_setup_txbuf(sc, sc->tx.cur, &m); 496 if (nsegs == 0) { 497 if_sendq_prepend(ifp, m); 498 break; 499 } 500 if_bpfmtap(ifp, m); 501 sc->tx.cur = TX_SKIP(sc->tx.cur, nsegs); 502 } 503 504 if (cnt != 0) { 505 bus_dmamap_sync(sc->tx.desc_tag, sc->tx.desc_map, 506 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 507 508 /* Start and run TX DMA */ 509 val = RD4(sc, EMAC_TX_CTL_1); 510 WR4(sc, EMAC_TX_CTL_1, val | TX_DMA_START); 511 } 512} 513 514static void 515awg_start(if_t ifp) 516{ 517 struct awg_softc *sc; 518 519 sc = if_getsoftc(ifp); 520 521 AWG_LOCK(sc); 522 awg_start_locked(sc); 523 AWG_UNLOCK(sc); 524} 525 526static void 527awg_tick(void *softc) 528{ 529 struct awg_softc *sc; 530 struct mii_data *mii; 531 if_t ifp; 532 int link; 533 534 sc = softc; 535 ifp = sc->ifp; 536 mii = device_get_softc(sc->miibus); 537 538 AWG_ASSERT_LOCKED(sc); 539 540 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 541 return; 542 543 link = sc->link; 544 mii_tick(mii); 545 if (sc->link && !link) 546 awg_start_locked(sc); 547 548 callout_reset(&sc->stat_ch, hz, awg_tick, sc); 549} 550 551/* Bit Reversal - http://aggregate.org/MAGIC/#Bit%20Reversal */ 552static uint32_t 553bitrev32(uint32_t x) 554{ 555 x = (((x & 0xaaaaaaaa) >> 1) | ((x & 0x55555555) << 1)); 556 x = (((x & 0xcccccccc) >> 2) | ((x & 0x33333333) << 2)); 557 x = (((x & 0xf0f0f0f0) >> 4) | ((x & 0x0f0f0f0f) << 4)); 558 x = (((x & 0xff00ff00) >> 8) | ((x & 0x00ff00ff) << 8)); 559 560 return (x >> 16) | (x << 16); 561} 562 563static void 564awg_setup_rxfilter(struct awg_softc *sc) 565{ 566 uint32_t val, crc, hashreg, hashbit, hash[2], machi, maclo; 567 int mc_count, mcnt, i; 568 uint8_t *eaddr, *mta; 569 if_t ifp; 570 571 AWG_ASSERT_LOCKED(sc); 572 573 ifp = sc->ifp; 574 val = 0; 575 hash[0] = hash[1] = 0; 576 577 mc_count = if_multiaddr_count(ifp, -1); 578 579 if (if_getflags(ifp) & IFF_PROMISC) 580 val |= DIS_ADDR_FILTER; 581 else if (if_getflags(ifp) & IFF_ALLMULTI) { 582 val |= RX_ALL_MULTICAST; 583 hash[0] = hash[1] = ~0; 584 } else if (mc_count > 0) { 585 val |= HASH_MULTICAST; 586 587 mta = malloc(sizeof(unsigned char) * ETHER_ADDR_LEN * mc_count, 588 M_DEVBUF, M_NOWAIT); 589 if (mta == NULL) { 590 if_printf(ifp, 591 "failed to allocate temporary multicast list\n"); 592 return; 593 } 594 595 if_multiaddr_array(ifp, mta, &mcnt, mc_count); 596 for (i = 0; i < mcnt; i++) { 597 crc = ether_crc32_le(mta + (i * ETHER_ADDR_LEN), 598 ETHER_ADDR_LEN) & 0x7f; 599 crc = bitrev32(~crc) >> 26; 600 hashreg = (crc >> 5); 601 hashbit = (crc & 0x1f); 602 hash[hashreg] |= (1 << hashbit); 603 } 604 605 free(mta, M_DEVBUF); 606 } 607 608 /* Write our unicast address */ 609 eaddr = IF_LLADDR(ifp); 610 machi = (eaddr[5] << 8) | eaddr[4]; 611 maclo = (eaddr[3] << 24) | (eaddr[2] << 16) | (eaddr[1] << 8) | 612 (eaddr[0] << 0); 613 WR4(sc, EMAC_ADDR_HIGH(0), machi); 614 WR4(sc, EMAC_ADDR_LOW(0), maclo); 615 616 /* Multicast hash filters */ 617 WR4(sc, EMAC_RX_HASH_0, hash[1]); 618 WR4(sc, EMAC_RX_HASH_1, hash[0]); 619 620 /* RX frame filter config */ 621 WR4(sc, EMAC_RX_FRM_FLT, val); 622} 623 624static void 625awg_init_locked(struct awg_softc *sc) 626{ 627 struct mii_data *mii; 628 uint32_t val; 629 if_t ifp; 630 631 mii = device_get_softc(sc->miibus); 632 ifp = sc->ifp; 633 634 AWG_ASSERT_LOCKED(sc); 635 636 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 637 return; 638 639 awg_setup_rxfilter(sc); 640 641 /* Configure DMA burst length and priorities */ 642 val = awg_burst_len << BASIC_CTL_BURST_LEN_SHIFT; 643 if (awg_rx_tx_pri) 644 val |= BASIC_CTL_RX_TX_PRI; 645 WR4(sc, EMAC_BASIC_CTL_1, val); 646 647 /* Enable interrupts */ 648 WR4(sc, EMAC_INT_EN, RX_INT_EN | TX_INT_EN | TX_BUF_UA_INT_EN); 649 650 /* Enable transmit DMA */ 651 val = RD4(sc, EMAC_TX_CTL_1); 652 WR4(sc, EMAC_TX_CTL_1, val | TX_DMA_EN | TX_MD); 653 654 /* Enable receive DMA */ 655 val = RD4(sc, EMAC_RX_CTL_1); 656 WR4(sc, EMAC_RX_CTL_1, val | RX_DMA_EN | RX_MD); 657 658 /* Enable transmitter */ 659 val = RD4(sc, EMAC_TX_CTL_0); 660 WR4(sc, EMAC_TX_CTL_0, val | TX_EN); 661 662 /* Enable receiver */ 663 val = RD4(sc, EMAC_RX_CTL_0); 664 WR4(sc, EMAC_RX_CTL_0, val | RX_EN | CHECK_CRC); 665 666 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE); 667 668 mii_mediachg(mii); 669 callout_reset(&sc->stat_ch, hz, awg_tick, sc); 670} 671 672static void 673awg_init(void *softc) 674{ 675 struct awg_softc *sc; 676 677 sc = softc; 678 679 AWG_LOCK(sc); 680 awg_init_locked(sc); 681 AWG_UNLOCK(sc); 682} 683 684static void 685awg_stop(struct awg_softc *sc) 686{ 687 if_t ifp; 688 uint32_t val; 689 690 AWG_ASSERT_LOCKED(sc); 691 692 ifp = sc->ifp; 693 694 callout_stop(&sc->stat_ch); 695 696 /* Stop transmit DMA and flush data in the TX FIFO */ 697 val = RD4(sc, EMAC_TX_CTL_1); 698 val &= ~TX_DMA_EN; 699 val |= FLUSH_TX_FIFO; 700 WR4(sc, EMAC_TX_CTL_1, val); 701 702 /* Disable transmitter */ 703 val = RD4(sc, EMAC_TX_CTL_0); 704 WR4(sc, EMAC_TX_CTL_0, val & ~TX_EN); 705 706 /* Disable receiver */ 707 val = RD4(sc, EMAC_RX_CTL_0); 708 WR4(sc, EMAC_RX_CTL_0, val & ~RX_EN); 709 710 /* Disable interrupts */ 711 WR4(sc, EMAC_INT_EN, 0); 712 713 /* Disable transmit DMA */ 714 val = RD4(sc, EMAC_TX_CTL_1); 715 WR4(sc, EMAC_TX_CTL_1, val & ~TX_DMA_EN); 716 717 /* Disable receive DMA */ 718 val = RD4(sc, EMAC_RX_CTL_1); 719 WR4(sc, EMAC_RX_CTL_1, val & ~RX_DMA_EN); 720 721 sc->link = 0; 722 723 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 724} 725 726static void 727awg_rxintr(struct awg_softc *sc) 728{ 729 if_t ifp; 730 struct mbuf *m, *m0; 731 int error, index, len; 732 uint32_t status; 733 734 ifp = sc->ifp; 735 736 bus_dmamap_sync(sc->rx.desc_tag, sc->rx.desc_map, 737 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 738 739 for (index = sc->rx.cur; ; index = RX_NEXT(index)) { 740 status = le32toh(sc->rx.desc_ring[index].status); 741 if ((status & RX_DESC_CTL) != 0) 742 break; 743 744 bus_dmamap_sync(sc->rx.buf_tag, sc->rx.buf_map[index].map, 745 BUS_DMASYNC_POSTREAD); 746 bus_dmamap_unload(sc->rx.buf_tag, sc->rx.buf_map[index].map); 747 748 len = (status & RX_FRM_LEN) >> RX_FRM_LEN_SHIFT; 749 if (len != 0) { 750 m = sc->rx.buf_map[index].mbuf; 751 m->m_pkthdr.rcvif = ifp; 752 m->m_pkthdr.len = len; 753 m->m_len = len; 754 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 755 756 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0 && 757 (status & RX_FRM_TYPE) != 0) { 758 m->m_pkthdr.csum_flags = CSUM_IP_CHECKED; 759 if ((status & RX_HEADER_ERR) == 0) 760 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 761 if ((status & RX_PAYLOAD_ERR) == 0) { 762 m->m_pkthdr.csum_flags |= 763 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 764 m->m_pkthdr.csum_data = 0xffff; 765 } 766 } 767 768 AWG_UNLOCK(sc); 769 if_input(ifp, m); 770 AWG_LOCK(sc); 771 } 772 773 if ((m0 = awg_alloc_mbufcl(sc)) != NULL) { 774 error = awg_setup_rxbuf(sc, index, m0); 775 if (error != 0) { 776 /* XXX hole in RX ring */ 777 } 778 } else 779 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 780 } 781 782 if (index != sc->rx.cur) { 783 bus_dmamap_sync(sc->rx.desc_tag, sc->rx.desc_map, 784 BUS_DMASYNC_PREWRITE); 785 } 786 787 sc->rx.cur = index; 788} 789 790static void 791awg_txintr(struct awg_softc *sc) 792{ 793 struct awg_bufmap *bmap; 794 struct emac_desc *desc; 795 uint32_t status; 796 if_t ifp; 797 int i; 798 799 AWG_ASSERT_LOCKED(sc); 800 801 bus_dmamap_sync(sc->tx.desc_tag, sc->tx.desc_map, 802 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 803 804 ifp = sc->ifp; 805 for (i = sc->tx.next; sc->tx.queued > 0; i = TX_NEXT(i)) { 806 desc = &sc->tx.desc_ring[i]; 807 status = le32toh(desc->status); 808 if ((status & TX_DESC_CTL) != 0) 809 break; 810 bmap = &sc->tx.buf_map[i]; 811 if (bmap->mbuf != NULL) { 812 bus_dmamap_sync(sc->tx.buf_tag, bmap->map, 813 BUS_DMASYNC_POSTWRITE); 814 bus_dmamap_unload(sc->tx.buf_tag, bmap->map); 815 m_freem(bmap->mbuf); 816 bmap->mbuf = NULL; 817 } 818 awg_setup_txdesc(sc, i, 0, 0, 0); 819 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 820 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 821 } 822 823 sc->tx.next = i; 824 825 bus_dmamap_sync(sc->tx.desc_tag, sc->tx.desc_map, 826 BUS_DMASYNC_PREWRITE); 827} 828 829static void 830awg_intr(void *arg) 831{ 832 struct awg_softc *sc; 833 uint32_t val; 834 835 sc = arg; 836 837 AWG_LOCK(sc); 838 val = RD4(sc, EMAC_INT_STA); 839 WR4(sc, EMAC_INT_STA, val); 840 841 if (val & RX_INT) 842 awg_rxintr(sc); 843 844 if (val & (TX_INT|TX_BUF_UA_INT)) { 845 awg_txintr(sc); 846 if (!if_sendq_empty(sc->ifp)) 847 awg_start_locked(sc); 848 } 849 850 AWG_UNLOCK(sc); 851} 852 853static int 854awg_ioctl(if_t ifp, u_long cmd, caddr_t data) 855{ 856 struct awg_softc *sc; 857 struct mii_data *mii; 858 struct ifreq *ifr; 859 int flags, mask, error; 860 861 sc = if_getsoftc(ifp); 862 mii = device_get_softc(sc->miibus); 863 ifr = (struct ifreq *)data; 864 error = 0; 865 866 switch (cmd) { 867 case SIOCSIFFLAGS: 868 AWG_LOCK(sc); 869 if (if_getflags(ifp) & IFF_UP) { 870 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 871 flags = if_getflags(ifp) ^ sc->if_flags; 872 if ((flags & (IFF_PROMISC|IFF_ALLMULTI)) != 0) 873 awg_setup_rxfilter(sc); 874 } else 875 awg_init_locked(sc); 876 } else { 877 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 878 awg_stop(sc); 879 } 880 sc->if_flags = if_getflags(ifp); 881 AWG_UNLOCK(sc); 882 break; 883 case SIOCADDMULTI: 884 case SIOCDELMULTI: 885 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 886 AWG_LOCK(sc); 887 awg_setup_rxfilter(sc); 888 AWG_UNLOCK(sc); 889 } 890 break; 891 case SIOCSIFMEDIA: 892 case SIOCGIFMEDIA: 893 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 894 break; 895 case SIOCSIFCAP: 896 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 897 if (mask & IFCAP_VLAN_MTU) 898 if_togglecapenable(ifp, IFCAP_VLAN_MTU); 899 if (mask & IFCAP_RXCSUM) 900 if_togglecapenable(ifp, IFCAP_RXCSUM); 901 if (mask & IFCAP_TXCSUM) 902 if_togglecapenable(ifp, IFCAP_TXCSUM); 903 if ((if_getcapenable(ifp) & (IFCAP_RXCSUM|IFCAP_TXCSUM)) != 0) 904 if_sethwassistbits(ifp, CSUM_IP, 0); 905 else 906 if_sethwassistbits(ifp, 0, CSUM_IP); 907 break; 908 default: 909 error = ether_ioctl(ifp, cmd, data); 910 break; 911 } 912 913 return (error); 914} 915 916static int 917awg_setup_extres(device_t dev) 918{ 919 struct awg_softc *sc; 920 hwreset_t rst_ahb; 921 clk_t clk_ahb, clk_tx, clk_tx_parent; 922 regulator_t reg; 923 const char *tx_parent_name; 924 char *phy_type; 925 phandle_t node; 926 uint64_t freq; 927 int error, div; 928 929 sc = device_get_softc(dev); 930 node = ofw_bus_get_node(dev); 931 rst_ahb = NULL; 932 clk_ahb = NULL; 933 clk_tx = NULL; 934 clk_tx_parent = NULL; 935 reg = NULL; 936 phy_type = NULL; 937 938 /* Get AHB clock and reset resources */ 939 error = hwreset_get_by_ofw_name(dev, 0, "ahb", &rst_ahb); 940 if (error != 0) { 941 device_printf(dev, "cannot get ahb reset\n"); 942 goto fail; 943 } 944 error = clk_get_by_ofw_name(dev, 0, "ahb", &clk_ahb); 945 if (error != 0) { 946 device_printf(dev, "cannot get ahb clock\n"); 947 goto fail; 948 } 949 950 /* Configure PHY for MII or RGMII mode */ 951 if (OF_getprop_alloc(node, "phy-mode", 1, (void **)&phy_type)) { 952 if (bootverbose) 953 device_printf(dev, "PHY type: %s\n", phy_type); 954 955 if (strcmp(phy_type, "rgmii") == 0) 956 tx_parent_name = "emac_int_tx"; 957 else 958 tx_parent_name = "mii_phy_tx"; 959 OF_prop_free(phy_type); 960 961 /* Get the TX clock */ 962 error = clk_get_by_ofw_name(dev, 0, "tx", &clk_tx); 963 if (error != 0) { 964 device_printf(dev, "cannot get tx clock\n"); 965 goto fail; 966 } 967 968 /* Find the desired parent clock based on phy-mode property */ 969 error = clk_get_by_name(dev, tx_parent_name, &clk_tx_parent); 970 if (error != 0) { 971 device_printf(dev, "cannot get clock '%s'\n", 972 tx_parent_name); 973 goto fail; 974 } 975 976 /* Set TX clock parent */ 977 error = clk_set_parent_by_clk(clk_tx, clk_tx_parent); 978 if (error != 0) { 979 device_printf(dev, "cannot set tx clock parent\n"); 980 goto fail; 981 } 982 983 /* Enable TX clock */ 984 error = clk_enable(clk_tx); 985 if (error != 0) { 986 device_printf(dev, "cannot enable tx clock\n"); 987 goto fail; 988 } 989 } 990 991 /* Enable AHB clock */ 992 error = clk_enable(clk_ahb); 993 if (error != 0) { 994 device_printf(dev, "cannot enable ahb clock\n"); 995 goto fail; 996 } 997 998 /* De-assert reset */ 999 error = hwreset_deassert(rst_ahb); 1000 if (error != 0) { 1001 device_printf(dev, "cannot de-assert ahb reset\n"); 1002 goto fail; 1003 } 1004 1005 /* Enable PHY regulator if applicable */ 1006 if (regulator_get_by_ofw_property(dev, 0, "phy-supply", ®) == 0) { 1007 error = regulator_enable(reg); 1008 if (error != 0) { 1009 device_printf(dev, "cannot enable PHY regulator\n"); 1010 goto fail; 1011 } 1012 } 1013 1014 /* Determine MDC clock divide ratio based on AHB clock */ 1015 error = clk_get_freq(clk_ahb, &freq); 1016 if (error != 0) { 1017 device_printf(dev, "cannot get AHB clock frequency\n"); 1018 goto fail; 1019 } 1020 div = freq / MDIO_FREQ; 1021 if (div <= 16) 1022 sc->mdc_div_ratio_m = MDC_DIV_RATIO_M_16; 1023 else if (div <= 32) 1024 sc->mdc_div_ratio_m = MDC_DIV_RATIO_M_32; 1025 else if (div <= 64) 1026 sc->mdc_div_ratio_m = MDC_DIV_RATIO_M_64; 1027 else if (div <= 128) 1028 sc->mdc_div_ratio_m = MDC_DIV_RATIO_M_128; 1029 else { 1030 device_printf(dev, "cannot determine MDC clock divide ratio\n"); 1031 error = ENXIO; 1032 goto fail; 1033 } 1034 1035 if (bootverbose) 1036 device_printf(dev, "AHB frequency %llu Hz, MDC div: 0x%x\n", 1037 freq, sc->mdc_div_ratio_m); 1038 1039 return (0); 1040 1041fail: 1042 OF_prop_free(phy_type); 1043 1044 if (reg != NULL) 1045 regulator_release(reg); 1046 if (clk_tx_parent != NULL) 1047 clk_release(clk_tx_parent); 1048 if (clk_tx != NULL) 1049 clk_release(clk_tx); 1050 if (clk_ahb != NULL) 1051 clk_release(clk_ahb); 1052 if (rst_ahb != NULL) 1053 hwreset_release(rst_ahb); 1054 return (error); 1055} 1056 1057static void 1058awg_get_eaddr(device_t dev, uint8_t *eaddr) 1059{ 1060 struct awg_softc *sc; 1061 uint32_t maclo, machi, rnd; 1062 1063 sc = device_get_softc(dev); 1064 1065 machi = RD4(sc, EMAC_ADDR_HIGH(0)) & 0xffff; 1066 maclo = RD4(sc, EMAC_ADDR_LOW(0)); 1067 1068 if (maclo == 0xffffffff && machi == 0xffff) { 1069 /* MAC address in hardware is invalid, create one */ 1070 rnd = arc4random(); 1071 maclo = 0x00f2 | (rnd & 0xffff0000); 1072 machi = rnd & 0xffff; 1073 } 1074 1075 eaddr[0] = maclo & 0xff; 1076 eaddr[1] = (maclo >> 8) & 0xff; 1077 eaddr[2] = (maclo >> 16) & 0xff; 1078 eaddr[3] = (maclo >> 24) & 0xff; 1079 eaddr[4] = machi & 0xff; 1080 eaddr[5] = (machi >> 8) & 0xff; 1081} 1082 1083#ifdef AWG_DEBUG 1084static void 1085awg_dump_regs(device_t dev) 1086{ 1087 static const struct { 1088 const char *name; 1089 u_int reg; 1090 } regs[] = { 1091 { "BASIC_CTL_0", EMAC_BASIC_CTL_0 }, 1092 { "BASIC_CTL_1", EMAC_BASIC_CTL_1 }, 1093 { "INT_STA", EMAC_INT_STA }, 1094 { "INT_EN", EMAC_INT_EN }, 1095 { "TX_CTL_0", EMAC_TX_CTL_0 }, 1096 { "TX_CTL_1", EMAC_TX_CTL_1 }, 1097 { "TX_FLOW_CTL", EMAC_TX_FLOW_CTL }, 1098 { "TX_DMA_LIST", EMAC_TX_DMA_LIST }, 1099 { "RX_CTL_0", EMAC_RX_CTL_0 }, 1100 { "RX_CTL_1", EMAC_RX_CTL_1 }, 1101 { "RX_DMA_LIST", EMAC_RX_DMA_LIST }, 1102 { "RX_FRM_FLT", EMAC_RX_FRM_FLT }, 1103 { "RX_HASH_0", EMAC_RX_HASH_0 }, 1104 { "RX_HASH_1", EMAC_RX_HASH_1 }, 1105 { "MII_CMD", EMAC_MII_CMD }, 1106 { "ADDR_HIGH0", EMAC_ADDR_HIGH(0) }, 1107 { "ADDR_LOW0", EMAC_ADDR_LOW(0) }, 1108 { "TX_DMA_STA", EMAC_TX_DMA_STA }, 1109 { "TX_DMA_CUR_DESC", EMAC_TX_DMA_CUR_DESC }, 1110 { "TX_DMA_CUR_BUF", EMAC_TX_DMA_CUR_BUF }, 1111 { "RX_DMA_STA", EMAC_RX_DMA_STA }, 1112 { "RX_DMA_CUR_DESC", EMAC_RX_DMA_CUR_DESC }, 1113 { "RX_DMA_CUR_BUF", EMAC_RX_DMA_CUR_BUF }, 1114 { "RGMII_STA", EMAC_RGMII_STA }, 1115 }; 1116 struct awg_softc *sc; 1117 unsigned int n; 1118 1119 sc = device_get_softc(dev); 1120 1121 for (n = 0; n < nitems(regs); n++) 1122 device_printf(dev, " %-20s %08x\n", regs[n].name, 1123 RD4(sc, regs[n].reg)); 1124} 1125#endif 1126 1127static int 1128awg_reset(device_t dev) 1129{ 1130 struct awg_softc *sc; 1131 int retry; 1132 1133 sc = device_get_softc(dev); 1134 1135 /* Soft reset all registers and logic */ 1136 WR4(sc, EMAC_BASIC_CTL_1, BASIC_CTL_SOFT_RST); 1137 1138 /* Wait for soft reset bit to self-clear */ 1139 for (retry = SOFT_RST_RETRY; retry > 0; retry--) { 1140 if ((RD4(sc, EMAC_BASIC_CTL_1) & BASIC_CTL_SOFT_RST) == 0) 1141 break; 1142 DELAY(10); 1143 } 1144 if (retry == 0) { 1145 device_printf(dev, "soft reset timed out\n"); 1146#ifdef AWG_DEBUG 1147 awg_dump_regs(dev); 1148#endif 1149 return (ETIMEDOUT); 1150 } 1151 1152 return (0); 1153} 1154 1155static void 1156awg_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1157{ 1158 if (error != 0) 1159 return; 1160 *(bus_addr_t *)arg = segs[0].ds_addr; 1161} 1162 1163static int 1164awg_setup_dma(device_t dev) 1165{ 1166 struct awg_softc *sc; 1167 struct mbuf *m; 1168 int error, i; 1169 1170 sc = device_get_softc(dev); 1171 1172 /* Setup TX ring */ 1173 error = bus_dma_tag_create( 1174 bus_get_dma_tag(dev), /* Parent tag */ 1175 DESC_ALIGN, 0, /* alignment, boundary */ 1176 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1177 BUS_SPACE_MAXADDR, /* highaddr */ 1178 NULL, NULL, /* filter, filterarg */ 1179 TX_DESC_SIZE, 1, /* maxsize, nsegs */ 1180 TX_DESC_SIZE, /* maxsegsize */ 1181 0, /* flags */ 1182 NULL, NULL, /* lockfunc, lockarg */ 1183 &sc->tx.desc_tag); 1184 if (error != 0) { 1185 device_printf(dev, "cannot create TX descriptor ring tag\n"); 1186 return (error); 1187 } 1188 1189 error = bus_dmamem_alloc(sc->tx.desc_tag, (void **)&sc->tx.desc_ring, 1190 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, &sc->tx.desc_map); 1191 if (error != 0) { 1192 device_printf(dev, "cannot allocate TX descriptor ring\n"); 1193 return (error); 1194 } 1195 1196 error = bus_dmamap_load(sc->tx.desc_tag, sc->tx.desc_map, 1197 sc->tx.desc_ring, TX_DESC_SIZE, awg_dmamap_cb, 1198 &sc->tx.desc_ring_paddr, 0); 1199 if (error != 0) { 1200 device_printf(dev, "cannot load TX descriptor ring\n"); 1201 return (error); 1202 } 1203 1204 for (i = 0; i < TX_DESC_COUNT; i++) 1205 sc->tx.desc_ring[i].next = 1206 htole32(sc->tx.desc_ring_paddr + DESC_OFF(TX_NEXT(i))); 1207 1208 error = bus_dma_tag_create( 1209 bus_get_dma_tag(dev), /* Parent tag */ 1210 1, 0, /* alignment, boundary */ 1211 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1212 BUS_SPACE_MAXADDR, /* highaddr */ 1213 NULL, NULL, /* filter, filterarg */ 1214 MCLBYTES, TX_MAX_SEGS, /* maxsize, nsegs */ 1215 MCLBYTES, /* maxsegsize */ 1216 0, /* flags */ 1217 NULL, NULL, /* lockfunc, lockarg */ 1218 &sc->tx.buf_tag); 1219 if (error != 0) { 1220 device_printf(dev, "cannot create TX buffer tag\n"); 1221 return (error); 1222 } 1223 1224 sc->tx.queued = TX_DESC_COUNT; 1225 for (i = 0; i < TX_DESC_COUNT; i++) { 1226 error = bus_dmamap_create(sc->tx.buf_tag, 0, 1227 &sc->tx.buf_map[i].map); 1228 if (error != 0) { 1229 device_printf(dev, "cannot create TX buffer map\n"); 1230 return (error); 1231 } 1232 awg_setup_txdesc(sc, i, 0, 0, 0); 1233 } 1234 1235 /* Setup RX ring */ 1236 error = bus_dma_tag_create( 1237 bus_get_dma_tag(dev), /* Parent tag */ 1238 DESC_ALIGN, 0, /* alignment, boundary */ 1239 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1240 BUS_SPACE_MAXADDR, /* highaddr */ 1241 NULL, NULL, /* filter, filterarg */ 1242 RX_DESC_SIZE, 1, /* maxsize, nsegs */ 1243 RX_DESC_SIZE, /* maxsegsize */ 1244 0, /* flags */ 1245 NULL, NULL, /* lockfunc, lockarg */ 1246 &sc->rx.desc_tag); 1247 if (error != 0) { 1248 device_printf(dev, "cannot create RX descriptor ring tag\n"); 1249 return (error); 1250 } 1251 1252 error = bus_dmamem_alloc(sc->rx.desc_tag, (void **)&sc->rx.desc_ring, 1253 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, &sc->rx.desc_map); 1254 if (error != 0) { 1255 device_printf(dev, "cannot allocate RX descriptor ring\n"); 1256 return (error); 1257 } 1258 1259 error = bus_dmamap_load(sc->rx.desc_tag, sc->rx.desc_map, 1260 sc->rx.desc_ring, RX_DESC_SIZE, awg_dmamap_cb, 1261 &sc->rx.desc_ring_paddr, 0); 1262 if (error != 0) { 1263 device_printf(dev, "cannot load RX descriptor ring\n"); 1264 return (error); 1265 } 1266 1267 error = bus_dma_tag_create( 1268 bus_get_dma_tag(dev), /* Parent tag */ 1269 1, 0, /* alignment, boundary */ 1270 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1271 BUS_SPACE_MAXADDR, /* highaddr */ 1272 NULL, NULL, /* filter, filterarg */ 1273 MCLBYTES, 1, /* maxsize, nsegs */ 1274 MCLBYTES, /* maxsegsize */ 1275 0, /* flags */ 1276 NULL, NULL, /* lockfunc, lockarg */ 1277 &sc->rx.buf_tag); 1278 if (error != 0) { 1279 device_printf(dev, "cannot create RX buffer tag\n"); 1280 return (error); 1281 } 1282 1283 for (i = 0; i < RX_DESC_COUNT; i++) { 1284 error = bus_dmamap_create(sc->rx.buf_tag, 0, 1285 &sc->rx.buf_map[i].map); 1286 if (error != 0) { 1287 device_printf(dev, "cannot create RX buffer map\n"); 1288 return (error); 1289 } 1290 if ((m = awg_alloc_mbufcl(sc)) == NULL) { 1291 device_printf(dev, "cannot allocate RX mbuf\n"); 1292 return (ENOMEM); 1293 } 1294 error = awg_setup_rxbuf(sc, i, m); 1295 if (error != 0) { 1296 device_printf(dev, "cannot create RX buffer\n"); 1297 return (error); 1298 } 1299 } 1300 bus_dmamap_sync(sc->rx.desc_tag, sc->rx.desc_map, 1301 BUS_DMASYNC_PREWRITE); 1302 1303 /* Write transmit and receive descriptor base address registers */ 1304 WR4(sc, EMAC_TX_DMA_LIST, sc->tx.desc_ring_paddr); 1305 WR4(sc, EMAC_RX_DMA_LIST, sc->rx.desc_ring_paddr); 1306 1307 return (0); 1308} 1309 1310static int 1311awg_probe(device_t dev) 1312{ 1313 if (!ofw_bus_status_okay(dev)) 1314 return (ENXIO); 1315 1316 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 1317 return (ENXIO); 1318 1319 device_set_desc(dev, "Allwinner Gigabit Ethernet"); 1320 return (BUS_PROBE_DEFAULT); 1321} 1322 1323static int 1324awg_attach(device_t dev) 1325{ 1326 uint8_t eaddr[ETHER_ADDR_LEN]; 1327 struct awg_softc *sc; 1328 phandle_t node; 1329 int error; 1330 1331 sc = device_get_softc(dev); 1332 sc->dev = dev; 1333 node = ofw_bus_get_node(dev); 1334 1335 if (bus_alloc_resources(dev, awg_spec, sc->res) != 0) { 1336 device_printf(dev, "cannot allocate resources for device\n"); 1337 return (ENXIO); 1338 } 1339 1340 mtx_init(&sc->mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, MTX_DEF); 1341 callout_init_mtx(&sc->stat_ch, &sc->mtx, 0); 1342 TASK_INIT(&sc->link_task, 0, awg_link_task, sc); 1343 1344 /* Setup clocks and regulators */ 1345 error = awg_setup_extres(dev); 1346 if (error != 0) 1347 return (error); 1348 1349 /* Read MAC address before resetting the chip */ 1350 awg_get_eaddr(dev, eaddr); 1351 1352 /* Soft reset EMAC core */ 1353 error = awg_reset(dev); 1354 if (error != 0) 1355 return (error); 1356 1357 /* Setup DMA descriptors */ 1358 error = awg_setup_dma(dev); 1359 if (error != 0) 1360 return (error); 1361 1362 /* Install interrupt handler */ 1363 error = bus_setup_intr(dev, sc->res[1], INTR_TYPE_NET | INTR_MPSAFE, 1364 NULL, awg_intr, sc, &sc->ih); 1365 if (error != 0) { 1366 device_printf(dev, "cannot setup interrupt handler\n"); 1367 return (error); 1368 } 1369 1370 /* Setup ethernet interface */ 1371 sc->ifp = if_alloc(IFT_ETHER); 1372 if_setsoftc(sc->ifp, sc); 1373 if_initname(sc->ifp, device_get_name(dev), device_get_unit(dev)); 1374 if_setflags(sc->ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 1375 if_setstartfn(sc->ifp, awg_start); 1376 if_setioctlfn(sc->ifp, awg_ioctl); 1377 if_setinitfn(sc->ifp, awg_init); 1378 if_setsendqlen(sc->ifp, TX_DESC_COUNT - 1); 1379 if_setsendqready(sc->ifp); 1380 if_sethwassist(sc->ifp, CSUM_IP | CSUM_UDP | CSUM_TCP); 1381 if_setcapabilities(sc->ifp, IFCAP_VLAN_MTU | IFCAP_HWCSUM); 1382 if_setcapenable(sc->ifp, if_getcapabilities(sc->ifp)); 1383 1384 /* Attach MII driver */ 1385 error = mii_attach(dev, &sc->miibus, sc->ifp, awg_media_change, 1386 awg_media_status, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 1387 MIIF_DOPAUSE); 1388 if (error != 0) { 1389 device_printf(dev, "cannot attach PHY\n"); 1390 return (error); 1391 } 1392 1393 /* Attach ethernet interface */ 1394 ether_ifattach(sc->ifp, eaddr); 1395 1396 return (0); 1397} 1398 1399static device_method_t awg_methods[] = { 1400 /* Device interface */ 1401 DEVMETHOD(device_probe, awg_probe), 1402 DEVMETHOD(device_attach, awg_attach), 1403 1404 /* MII interface */ 1405 DEVMETHOD(miibus_readreg, awg_miibus_readreg), 1406 DEVMETHOD(miibus_writereg, awg_miibus_writereg), 1407 DEVMETHOD(miibus_statchg, awg_miibus_statchg), 1408 1409 DEVMETHOD_END 1410}; 1411 1412static driver_t awg_driver = { 1413 "awg", 1414 awg_methods, 1415 sizeof(struct awg_softc), 1416}; 1417 1418static devclass_t awg_devclass; 1419 1420DRIVER_MODULE(awg, simplebus, awg_driver, awg_devclass, 0, 0); 1421DRIVER_MODULE(miibus, awg, miibus_driver, miibus_devclass, 0, 0); 1422 1423MODULE_DEPEND(awg, ether, 1, 1, 1); 1424MODULE_DEPEND(awg, miibus, 1, 1, 1); 1425