a10_gpio.c revision 304212
1/*- 2 * Copyright (c) 2013 Ganbold Tsagaankhuu <ganbold@freebsd.org> 3 * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org> 4 * Copyright (c) 2012 Luiz Otavio O Souza. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 */ 29#include <sys/cdefs.h> 30__FBSDID("$FreeBSD: stable/11/sys/arm/allwinner/a10_gpio.c 304212 2016-08-16 09:06:23Z manu $"); 31 32#include <sys/param.h> 33#include <sys/systm.h> 34#include <sys/bus.h> 35 36#include <sys/kernel.h> 37#include <sys/module.h> 38#include <sys/rman.h> 39#include <sys/lock.h> 40#include <sys/mutex.h> 41#include <sys/gpio.h> 42 43#include <machine/bus.h> 44#include <machine/cpu.h> 45#include <machine/cpufunc.h> 46#include <machine/resource.h> 47#include <machine/intr.h> 48 49#include <dev/fdt/fdt_common.h> 50#include <dev/fdt/fdt_pinctrl.h> 51#include <dev/gpio/gpiobusvar.h> 52#include <dev/ofw/ofw_bus.h> 53#include <dev/ofw/ofw_bus_subr.h> 54 55#include <arm/allwinner/allwinner_machdep.h> 56#include <arm/allwinner/allwinner_pinctrl.h> 57#include <dev/extres/clk/clk.h> 58#include <dev/extres/hwreset/hwreset.h> 59 60#include "gpio_if.h" 61 62#define A10_GPIO_DEFAULT_CAPS (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | \ 63 GPIO_PIN_PULLUP | GPIO_PIN_PULLDOWN) 64 65#define A10_GPIO_NONE 0 66#define A10_GPIO_PULLUP 1 67#define A10_GPIO_PULLDOWN 2 68 69#define A10_GPIO_INPUT 0 70#define A10_GPIO_OUTPUT 1 71 72#define AW_GPIO_DRV_MASK 0x3 73#define AW_GPIO_PUD_MASK 0x3 74 75#define AW_PINCTRL 1 76#define AW_R_PINCTRL 2 77 78/* Defined in a10_padconf.c */ 79#ifdef SOC_ALLWINNER_A10 80extern const struct allwinner_padconf a10_padconf; 81#endif 82 83/* Defined in a20_padconf.c */ 84#ifdef SOC_ALLWINNER_A20 85extern const struct allwinner_padconf a20_padconf; 86#endif 87 88/* Defined in a31_padconf.c */ 89#ifdef SOC_ALLWINNER_A31 90extern const struct allwinner_padconf a31_padconf; 91#endif 92 93/* Defined in a31s_padconf.c */ 94#ifdef SOC_ALLWINNER_A31S 95extern const struct allwinner_padconf a31s_padconf; 96#endif 97 98#if defined(SOC_ALLWINNER_A31) || defined(SOC_ALLWINNER_A31S) 99extern const struct allwinner_padconf a31_r_padconf; 100#endif 101 102/* Defined in h3_padconf.c */ 103#ifdef SOC_ALLWINNER_H3 104extern const struct allwinner_padconf h3_padconf; 105extern const struct allwinner_padconf h3_r_padconf; 106#endif 107 108/* Defined in a83t_padconf.c */ 109#ifdef SOC_ALLWINNER_A83T 110extern const struct allwinner_padconf a83t_padconf; 111extern const struct allwinner_padconf a83t_r_padconf; 112#endif 113 114static struct ofw_compat_data compat_data[] = { 115#ifdef SOC_ALLWINNER_A10 116 {"allwinner,sun4i-a10-pinctrl", (uintptr_t)&a10_padconf}, 117#endif 118#ifdef SOC_ALLWINNER_A20 119 {"allwinner,sun7i-a20-pinctrl", (uintptr_t)&a20_padconf}, 120#endif 121#ifdef SOC_ALLWINNER_A31 122 {"allwinner,sun6i-a31-pinctrl", (uintptr_t)&a31_padconf}, 123#endif 124#ifdef SOC_ALLWINNER_A31S 125 {"allwinner,sun6i-a31s-pinctrl", (uintptr_t)&a31s_padconf}, 126#endif 127#if defined(SOC_ALLWINNER_A31) || defined(SOC_ALLWINNER_A31S) 128 {"allwinner,sun6i-a31-r-pinctrl", (uintptr_t)&a31_r_padconf}, 129#endif 130#ifdef SOC_ALLWINNER_A83T 131 {"allwinner,sun8i-a83t-pinctrl", (uintptr_t)&a83t_padconf}, 132 {"allwinner,sun8i-a83t-r-pinctrl", (uintptr_t)&a83t_r_padconf}, 133#endif 134#ifdef SOC_ALLWINNER_H3 135 {"allwinner,sun8i-h3-pinctrl", (uintptr_t)&h3_padconf}, 136 {"allwinner,sun8i-h3-r-pinctrl", (uintptr_t)&h3_r_padconf}, 137#endif 138 {NULL, 0} 139}; 140 141struct a10_gpio_softc { 142 device_t sc_dev; 143 device_t sc_busdev; 144 struct mtx sc_mtx; 145 struct resource * sc_mem_res; 146 struct resource * sc_irq_res; 147 bus_space_tag_t sc_bst; 148 bus_space_handle_t sc_bsh; 149 void * sc_intrhand; 150 const struct allwinner_padconf * padconf; 151}; 152 153#define A10_GPIO_LOCK(_sc) mtx_lock_spin(&(_sc)->sc_mtx) 154#define A10_GPIO_UNLOCK(_sc) mtx_unlock_spin(&(_sc)->sc_mtx) 155#define A10_GPIO_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) 156 157#define A10_GPIO_GP_CFG(_bank, _idx) 0x00 + ((_bank) * 0x24) + ((_idx) << 2) 158#define A10_GPIO_GP_DAT(_bank) 0x10 + ((_bank) * 0x24) 159#define A10_GPIO_GP_DRV(_bank, _idx) 0x14 + ((_bank) * 0x24) + ((_idx) << 2) 160#define A10_GPIO_GP_PUL(_bank, _idx) 0x1c + ((_bank) * 0x24) + ((_idx) << 2) 161 162#define A10_GPIO_GP_INT_CFG0 0x200 163#define A10_GPIO_GP_INT_CFG1 0x204 164#define A10_GPIO_GP_INT_CFG2 0x208 165#define A10_GPIO_GP_INT_CFG3 0x20c 166 167#define A10_GPIO_GP_INT_CTL 0x210 168#define A10_GPIO_GP_INT_STA 0x214 169#define A10_GPIO_GP_INT_DEB 0x218 170 171#define A10_GPIO_WRITE(_sc, _off, _val) \ 172 bus_space_write_4(_sc->sc_bst, _sc->sc_bsh, _off, _val) 173#define A10_GPIO_READ(_sc, _off) \ 174 bus_space_read_4(_sc->sc_bst, _sc->sc_bsh, _off) 175 176static uint32_t 177a10_gpio_get_function(struct a10_gpio_softc *sc, uint32_t pin) 178{ 179 uint32_t bank, func, offset; 180 181 /* Must be called with lock held. */ 182 A10_GPIO_LOCK_ASSERT(sc); 183 184 if (pin > sc->padconf->npins) 185 return (0); 186 bank = sc->padconf->pins[pin].port; 187 pin = sc->padconf->pins[pin].pin; 188 offset = ((pin & 0x07) << 2); 189 190 func = A10_GPIO_READ(sc, A10_GPIO_GP_CFG(bank, pin >> 3)); 191 switch ((func >> offset) & 0x7) { 192 case A10_GPIO_INPUT: 193 return (GPIO_PIN_INPUT); 194 case A10_GPIO_OUTPUT: 195 return (GPIO_PIN_OUTPUT); 196 } 197 198 return (0); 199} 200 201static void 202a10_gpio_set_function(struct a10_gpio_softc *sc, uint32_t pin, uint32_t f) 203{ 204 uint32_t bank, data, offset; 205 206 /* Must be called with lock held. */ 207 A10_GPIO_LOCK_ASSERT(sc); 208 209 bank = sc->padconf->pins[pin].port; 210 pin = sc->padconf->pins[pin].pin; 211 offset = ((pin & 0x07) << 2); 212 213 data = A10_GPIO_READ(sc, A10_GPIO_GP_CFG(bank, pin >> 3)); 214 data &= ~(7 << offset); 215 data |= (f << offset); 216 A10_GPIO_WRITE(sc, A10_GPIO_GP_CFG(bank, pin >> 3), data); 217} 218 219static uint32_t 220a10_gpio_get_pud(struct a10_gpio_softc *sc, uint32_t pin) 221{ 222 uint32_t bank, offset, val; 223 224 /* Must be called with lock held. */ 225 A10_GPIO_LOCK_ASSERT(sc); 226 227 bank = sc->padconf->pins[pin].port; 228 pin = sc->padconf->pins[pin].pin; 229 offset = ((pin & 0x0f) << 1); 230 231 val = A10_GPIO_READ(sc, A10_GPIO_GP_PUL(bank, pin >> 4)); 232 switch ((val >> offset) & 0x3) { 233 case A10_GPIO_PULLDOWN: 234 return (GPIO_PIN_PULLDOWN); 235 case A10_GPIO_PULLUP: 236 return (GPIO_PIN_PULLUP); 237 } 238 239 return (0); 240} 241 242static void 243a10_gpio_set_pud(struct a10_gpio_softc *sc, uint32_t pin, uint32_t state) 244{ 245 uint32_t bank, offset, val; 246 247 /* Must be called with lock held. */ 248 A10_GPIO_LOCK_ASSERT(sc); 249 250 bank = sc->padconf->pins[pin].port; 251 pin = sc->padconf->pins[pin].pin; 252 offset = ((pin & 0x0f) << 1); 253 254 val = A10_GPIO_READ(sc, A10_GPIO_GP_PUL(bank, pin >> 4)); 255 val &= ~(AW_GPIO_PUD_MASK << offset); 256 val |= (state << offset); 257 A10_GPIO_WRITE(sc, A10_GPIO_GP_PUL(bank, pin >> 4), val); 258} 259 260static void 261a10_gpio_set_drv(struct a10_gpio_softc *sc, uint32_t pin, uint32_t drive) 262{ 263 uint32_t bank, offset, val; 264 265 /* Must be called with lock held. */ 266 A10_GPIO_LOCK_ASSERT(sc); 267 268 bank = sc->padconf->pins[pin].port; 269 pin = sc->padconf->pins[pin].pin; 270 offset = ((pin & 0x0f) << 1); 271 272 val = A10_GPIO_READ(sc, A10_GPIO_GP_DRV(bank, pin >> 4)); 273 val &= ~(AW_GPIO_DRV_MASK << offset); 274 val |= (drive << offset); 275 A10_GPIO_WRITE(sc, A10_GPIO_GP_DRV(bank, pin >> 4), val); 276} 277 278static void 279a10_gpio_pin_configure(struct a10_gpio_softc *sc, uint32_t pin, uint32_t flags) 280{ 281 282 /* Must be called with lock held. */ 283 A10_GPIO_LOCK_ASSERT(sc); 284 285 /* Manage input/output. */ 286 if (flags & (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT)) { 287 if (flags & GPIO_PIN_OUTPUT) 288 a10_gpio_set_function(sc, pin, A10_GPIO_OUTPUT); 289 else 290 a10_gpio_set_function(sc, pin, A10_GPIO_INPUT); 291 } 292 293 /* Manage Pull-up/pull-down. */ 294 if (flags & (GPIO_PIN_PULLUP | GPIO_PIN_PULLDOWN)) { 295 if (flags & GPIO_PIN_PULLUP) 296 a10_gpio_set_pud(sc, pin, A10_GPIO_PULLUP); 297 else 298 a10_gpio_set_pud(sc, pin, A10_GPIO_PULLDOWN); 299 } else 300 a10_gpio_set_pud(sc, pin, A10_GPIO_NONE); 301} 302 303static device_t 304a10_gpio_get_bus(device_t dev) 305{ 306 struct a10_gpio_softc *sc; 307 308 sc = device_get_softc(dev); 309 310 return (sc->sc_busdev); 311} 312 313static int 314a10_gpio_pin_max(device_t dev, int *maxpin) 315{ 316 struct a10_gpio_softc *sc; 317 318 sc = device_get_softc(dev); 319 320 *maxpin = sc->padconf->npins - 1; 321 return (0); 322} 323 324static int 325a10_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps) 326{ 327 struct a10_gpio_softc *sc; 328 329 sc = device_get_softc(dev); 330 if (pin >= sc->padconf->npins) 331 return (EINVAL); 332 333 *caps = A10_GPIO_DEFAULT_CAPS; 334 335 return (0); 336} 337 338static int 339a10_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags) 340{ 341 struct a10_gpio_softc *sc; 342 343 sc = device_get_softc(dev); 344 if (pin >= sc->padconf->npins) 345 return (EINVAL); 346 347 A10_GPIO_LOCK(sc); 348 *flags = a10_gpio_get_function(sc, pin); 349 *flags |= a10_gpio_get_pud(sc, pin); 350 A10_GPIO_UNLOCK(sc); 351 352 return (0); 353} 354 355static int 356a10_gpio_pin_getname(device_t dev, uint32_t pin, char *name) 357{ 358 struct a10_gpio_softc *sc; 359 360 sc = device_get_softc(dev); 361 if (pin >= sc->padconf->npins) 362 return (EINVAL); 363 364 snprintf(name, GPIOMAXNAME - 1, "%s", 365 sc->padconf->pins[pin].name); 366 name[GPIOMAXNAME - 1] = '\0'; 367 368 return (0); 369} 370 371static int 372a10_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags) 373{ 374 struct a10_gpio_softc *sc; 375 376 sc = device_get_softc(dev); 377 if (pin > sc->padconf->npins) 378 return (EINVAL); 379 380 A10_GPIO_LOCK(sc); 381 a10_gpio_pin_configure(sc, pin, flags); 382 A10_GPIO_UNLOCK(sc); 383 384 return (0); 385} 386 387static int 388a10_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value) 389{ 390 struct a10_gpio_softc *sc; 391 uint32_t bank, data; 392 393 sc = device_get_softc(dev); 394 if (pin > sc->padconf->npins) 395 return (EINVAL); 396 397 bank = sc->padconf->pins[pin].port; 398 pin = sc->padconf->pins[pin].pin; 399 400 A10_GPIO_LOCK(sc); 401 data = A10_GPIO_READ(sc, A10_GPIO_GP_DAT(bank)); 402 if (value) 403 data |= (1 << pin); 404 else 405 data &= ~(1 << pin); 406 A10_GPIO_WRITE(sc, A10_GPIO_GP_DAT(bank), data); 407 A10_GPIO_UNLOCK(sc); 408 409 return (0); 410} 411 412static int 413a10_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val) 414{ 415 struct a10_gpio_softc *sc; 416 uint32_t bank, reg_data; 417 418 sc = device_get_softc(dev); 419 if (pin > sc->padconf->npins) 420 return (EINVAL); 421 422 bank = sc->padconf->pins[pin].port; 423 pin = sc->padconf->pins[pin].pin; 424 425 A10_GPIO_LOCK(sc); 426 reg_data = A10_GPIO_READ(sc, A10_GPIO_GP_DAT(bank)); 427 A10_GPIO_UNLOCK(sc); 428 *val = (reg_data & (1 << pin)) ? 1 : 0; 429 430 return (0); 431} 432 433static int 434a10_gpio_pin_toggle(device_t dev, uint32_t pin) 435{ 436 struct a10_gpio_softc *sc; 437 uint32_t bank, data; 438 439 sc = device_get_softc(dev); 440 if (pin > sc->padconf->npins) 441 return (EINVAL); 442 443 bank = sc->padconf->pins[pin].port; 444 pin = sc->padconf->pins[pin].pin; 445 446 A10_GPIO_LOCK(sc); 447 data = A10_GPIO_READ(sc, A10_GPIO_GP_DAT(bank)); 448 if (data & (1 << pin)) 449 data &= ~(1 << pin); 450 else 451 data |= (1 << pin); 452 A10_GPIO_WRITE(sc, A10_GPIO_GP_DAT(bank), data); 453 A10_GPIO_UNLOCK(sc); 454 455 return (0); 456} 457 458static int 459aw_find_pinnum_by_name(struct a10_gpio_softc *sc, const char *pinname) 460{ 461 int i; 462 463 for (i = 0; i < sc->padconf->npins; i++) 464 if (!strcmp(pinname, sc->padconf->pins[i].name)) 465 return i; 466 467 return (-1); 468} 469 470static int 471aw_find_pin_func(struct a10_gpio_softc *sc, int pin, const char *func) 472{ 473 int i; 474 475 for (i = 0; i < AW_MAX_FUNC_BY_PIN; i++) 476 if (sc->padconf->pins[pin].functions[i] && 477 !strcmp(func, sc->padconf->pins[pin].functions[i])) 478 return (i); 479 480 return (-1); 481} 482 483static int 484aw_fdt_configure_pins(device_t dev, phandle_t cfgxref) 485{ 486 struct a10_gpio_softc *sc; 487 phandle_t node; 488 const char **pinlist = NULL; 489 char *pin_function = NULL; 490 uint32_t pin_drive, pin_pull; 491 int pins_nb, pin_num, pin_func, i, ret; 492 493 sc = device_get_softc(dev); 494 node = OF_node_from_xref(cfgxref); 495 ret = 0; 496 497 /* Getting all prop for configuring pins */ 498 pins_nb = ofw_bus_string_list_to_array(node, "allwinner,pins", &pinlist); 499 if (pins_nb <= 0) 500 return (ENOENT); 501 if (OF_getprop_alloc(node, "allwinner,function", 502 sizeof(*pin_function), 503 (void **)&pin_function) == -1) { 504 ret = ENOENT; 505 goto out; 506 } 507 if (OF_getencprop(node, "allwinner,drive", 508 &pin_drive, sizeof(pin_drive)) == -1) { 509 ret = ENOENT; 510 goto out; 511 } 512 if (OF_getencprop(node, "allwinner,pull", 513 &pin_pull, sizeof(pin_pull)) == -1) { 514 ret = ENOENT; 515 goto out; 516 } 517 518 /* Configure each pin to the correct function, drive and pull */ 519 for (i = 0; i < pins_nb; i++) { 520 pin_num = aw_find_pinnum_by_name(sc, pinlist[i]); 521 if (pin_num == -1) { 522 ret = ENOENT; 523 goto out; 524 } 525 pin_func = aw_find_pin_func(sc, pin_num, pin_function); 526 if (pin_func == -1) { 527 ret = ENOENT; 528 goto out; 529 } 530 531 A10_GPIO_LOCK(sc); 532 a10_gpio_set_function(sc, pin_num, pin_func); 533 a10_gpio_set_drv(sc, pin_num, pin_drive); 534 a10_gpio_set_pud(sc, pin_num, pin_pull); 535 A10_GPIO_UNLOCK(sc); 536 } 537 538 out: 539 OF_prop_free(pinlist); 540 OF_prop_free(pin_function); 541 return (ret); 542} 543 544static int 545a10_gpio_probe(device_t dev) 546{ 547 548 if (!ofw_bus_status_okay(dev)) 549 return (ENXIO); 550 551 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 552 return (ENXIO); 553 554 device_set_desc(dev, "Allwinner GPIO/Pinmux controller"); 555 return (BUS_PROBE_DEFAULT); 556} 557 558static int 559a10_gpio_attach(device_t dev) 560{ 561 int rid, error; 562 phandle_t gpio; 563 struct a10_gpio_softc *sc; 564 clk_t clk; 565 hwreset_t rst; 566 567 sc = device_get_softc(dev); 568 sc->sc_dev = dev; 569 570 mtx_init(&sc->sc_mtx, "a10 gpio", "gpio", MTX_SPIN); 571 572 rid = 0; 573 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 574 RF_ACTIVE); 575 if (!sc->sc_mem_res) { 576 device_printf(dev, "cannot allocate memory window\n"); 577 goto fail; 578 } 579 580 sc->sc_bst = rman_get_bustag(sc->sc_mem_res); 581 sc->sc_bsh = rman_get_bushandle(sc->sc_mem_res); 582 583 rid = 0; 584 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 585 RF_ACTIVE); 586 if (!sc->sc_irq_res) { 587 device_printf(dev, "cannot allocate interrupt\n"); 588 goto fail; 589 } 590 591 /* Find our node. */ 592 gpio = ofw_bus_get_node(sc->sc_dev); 593 if (!OF_hasprop(gpio, "gpio-controller")) 594 /* Node is not a GPIO controller. */ 595 goto fail; 596 597 /* Use the right pin data for the current SoC */ 598 sc->padconf = (struct allwinner_padconf *)ofw_bus_search_compatible(dev, 599 compat_data)->ocd_data; 600 601 if (hwreset_get_by_ofw_idx(dev, 0, &rst) == 0) { 602 error = hwreset_deassert(rst); 603 if (error != 0) { 604 device_printf(dev, "cannot de-assert reset\n"); 605 return (error); 606 } 607 } 608 609 if (clk_get_by_ofw_index(dev, 0, &clk) == 0) { 610 error = clk_enable(clk); 611 if (error != 0) { 612 device_printf(dev, "could not enable clock\n"); 613 return (error); 614 } 615 } 616 617 sc->sc_busdev = gpiobus_attach_bus(dev); 618 if (sc->sc_busdev == NULL) 619 goto fail; 620 621 /* 622 * Register as a pinctrl device 623 */ 624 fdt_pinctrl_register(dev, "allwinner,pins"); 625 fdt_pinctrl_configure_tree(dev); 626 627 return (0); 628 629fail: 630 if (sc->sc_irq_res) 631 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); 632 if (sc->sc_mem_res) 633 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 634 mtx_destroy(&sc->sc_mtx); 635 636 return (ENXIO); 637} 638 639static int 640a10_gpio_detach(device_t dev) 641{ 642 643 return (EBUSY); 644} 645 646static phandle_t 647a10_gpio_get_node(device_t dev, device_t bus) 648{ 649 650 /* We only have one child, the GPIO bus, which needs our own node. */ 651 return (ofw_bus_get_node(dev)); 652} 653 654static int 655a10_gpio_map_gpios(device_t bus, phandle_t dev, phandle_t gparent, int gcells, 656 pcell_t *gpios, uint32_t *pin, uint32_t *flags) 657{ 658 struct a10_gpio_softc *sc; 659 int i; 660 661 sc = device_get_softc(bus); 662 663 /* The GPIO pins are mapped as: <gpio-phandle bank pin flags>. */ 664 for (i = 0; i < sc->padconf->npins; i++) 665 if (sc->padconf->pins[i].port == gpios[0] && 666 sc->padconf->pins[i].pin == gpios[1]) { 667 *pin = i; 668 break; 669 } 670 *flags = gpios[gcells - 1]; 671 672 return (0); 673} 674 675static device_method_t a10_gpio_methods[] = { 676 /* Device interface */ 677 DEVMETHOD(device_probe, a10_gpio_probe), 678 DEVMETHOD(device_attach, a10_gpio_attach), 679 DEVMETHOD(device_detach, a10_gpio_detach), 680 681 /* GPIO protocol */ 682 DEVMETHOD(gpio_get_bus, a10_gpio_get_bus), 683 DEVMETHOD(gpio_pin_max, a10_gpio_pin_max), 684 DEVMETHOD(gpio_pin_getname, a10_gpio_pin_getname), 685 DEVMETHOD(gpio_pin_getflags, a10_gpio_pin_getflags), 686 DEVMETHOD(gpio_pin_getcaps, a10_gpio_pin_getcaps), 687 DEVMETHOD(gpio_pin_setflags, a10_gpio_pin_setflags), 688 DEVMETHOD(gpio_pin_get, a10_gpio_pin_get), 689 DEVMETHOD(gpio_pin_set, a10_gpio_pin_set), 690 DEVMETHOD(gpio_pin_toggle, a10_gpio_pin_toggle), 691 DEVMETHOD(gpio_map_gpios, a10_gpio_map_gpios), 692 693 /* ofw_bus interface */ 694 DEVMETHOD(ofw_bus_get_node, a10_gpio_get_node), 695 696 /* fdt_pinctrl interface */ 697 DEVMETHOD(fdt_pinctrl_configure,aw_fdt_configure_pins), 698 699 DEVMETHOD_END 700}; 701 702static devclass_t a10_gpio_devclass; 703 704static driver_t a10_gpio_driver = { 705 "gpio", 706 a10_gpio_methods, 707 sizeof(struct a10_gpio_softc), 708}; 709 710EARLY_DRIVER_MODULE(a10_gpio, simplebus, a10_gpio_driver, a10_gpio_devclass, 0, 0, 711 BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LATE); 712