fpu.c revision 332028
1/*- 2 * Copyright (c) 1990 William Jolitz. 3 * Copyright (c) 1991 The Regents of the University of California. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 4. Neither the name of the University nor the names of its contributors 15 * may be used to endorse or promote products derived from this software 16 * without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * from: @(#)npx.c 7.2 (Berkeley) 5/12/91 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: stable/11/sys/amd64/amd64/fpu.c 332028 2018-04-04 13:58:18Z kevans $"); 35 36#include <sys/param.h> 37#include <sys/systm.h> 38#include <sys/bus.h> 39#include <sys/kernel.h> 40#include <sys/lock.h> 41#include <sys/malloc.h> 42#include <sys/module.h> 43#include <sys/mutex.h> 44#include <sys/mutex.h> 45#include <sys/proc.h> 46#include <sys/sysctl.h> 47#include <machine/bus.h> 48#include <sys/rman.h> 49#include <sys/signalvar.h> 50#include <vm/uma.h> 51 52#include <machine/cputypes.h> 53#include <machine/frame.h> 54#include <machine/intr_machdep.h> 55#include <machine/md_var.h> 56#include <machine/pcb.h> 57#include <machine/psl.h> 58#include <machine/resource.h> 59#include <machine/specialreg.h> 60#include <machine/segments.h> 61#include <machine/ucontext.h> 62 63/* 64 * Floating point support. 65 */ 66 67#if defined(__GNUCLIKE_ASM) && !defined(lint) 68 69#define fldcw(cw) __asm __volatile("fldcw %0" : : "m" (cw)) 70#define fnclex() __asm __volatile("fnclex") 71#define fninit() __asm __volatile("fninit") 72#define fnstcw(addr) __asm __volatile("fnstcw %0" : "=m" (*(addr))) 73#define fnstsw(addr) __asm __volatile("fnstsw %0" : "=am" (*(addr))) 74#define fxrstor(addr) __asm __volatile("fxrstor %0" : : "m" (*(addr))) 75#define fxsave(addr) __asm __volatile("fxsave %0" : "=m" (*(addr))) 76#define ldmxcsr(csr) __asm __volatile("ldmxcsr %0" : : "m" (csr)) 77#define stmxcsr(addr) __asm __volatile("stmxcsr %0" : : "m" (*(addr))) 78 79static __inline void 80xrstor(char *addr, uint64_t mask) 81{ 82 uint32_t low, hi; 83 84 low = mask; 85 hi = mask >> 32; 86 __asm __volatile("xrstor %0" : : "m" (*addr), "a" (low), "d" (hi)); 87} 88 89static __inline void 90xsave(char *addr, uint64_t mask) 91{ 92 uint32_t low, hi; 93 94 low = mask; 95 hi = mask >> 32; 96 __asm __volatile("xsave %0" : "=m" (*addr) : "a" (low), "d" (hi) : 97 "memory"); 98} 99 100#else /* !(__GNUCLIKE_ASM && !lint) */ 101 102void fldcw(u_short cw); 103void fnclex(void); 104void fninit(void); 105void fnstcw(caddr_t addr); 106void fnstsw(caddr_t addr); 107void fxsave(caddr_t addr); 108void fxrstor(caddr_t addr); 109void ldmxcsr(u_int csr); 110void stmxcsr(u_int *csr); 111void xrstor(char *addr, uint64_t mask); 112void xsave(char *addr, uint64_t mask); 113 114#endif /* __GNUCLIKE_ASM && !lint */ 115 116#define start_emulating() load_cr0(rcr0() | CR0_TS) 117#define stop_emulating() clts() 118 119CTASSERT(sizeof(struct savefpu) == 512); 120CTASSERT(sizeof(struct xstate_hdr) == 64); 121CTASSERT(sizeof(struct savefpu_ymm) == 832); 122 123/* 124 * This requirement is to make it easier for asm code to calculate 125 * offset of the fpu save area from the pcb address. FPU save area 126 * must be 64-byte aligned. 127 */ 128CTASSERT(sizeof(struct pcb) % XSAVE_AREA_ALIGN == 0); 129 130/* 131 * Ensure the copy of XCR0 saved in a core is contained in the padding 132 * area. 133 */ 134CTASSERT(X86_XSTATE_XCR0_OFFSET >= offsetof(struct savefpu, sv_pad) && 135 X86_XSTATE_XCR0_OFFSET + sizeof(uint64_t) <= sizeof(struct savefpu)); 136 137static void fpu_clean_state(void); 138 139SYSCTL_INT(_hw, HW_FLOATINGPT, floatingpoint, CTLFLAG_RD, 140 SYSCTL_NULL_INT_PTR, 1, "Floating point instructions executed in hardware"); 141 142int use_xsave; /* non-static for cpu_switch.S */ 143uint64_t xsave_mask; /* the same */ 144static uma_zone_t fpu_save_area_zone; 145static struct savefpu *fpu_initialstate; 146 147struct xsave_area_elm_descr { 148 u_int offset; 149 u_int size; 150} *xsave_area_desc; 151 152void 153fpusave(void *addr) 154{ 155 156 if (use_xsave) 157 xsave((char *)addr, xsave_mask); 158 else 159 fxsave((char *)addr); 160} 161 162void 163fpurestore(void *addr) 164{ 165 166 if (use_xsave) 167 xrstor((char *)addr, xsave_mask); 168 else 169 fxrstor((char *)addr); 170} 171 172void 173fpususpend(void *addr) 174{ 175 u_long cr0; 176 177 cr0 = rcr0(); 178 stop_emulating(); 179 fpusave(addr); 180 load_cr0(cr0); 181} 182 183void 184fpuresume(void *addr) 185{ 186 u_long cr0; 187 188 cr0 = rcr0(); 189 stop_emulating(); 190 fninit(); 191 if (use_xsave) 192 load_xcr(XCR0, xsave_mask); 193 fpurestore(addr); 194 load_cr0(cr0); 195} 196 197/* 198 * Enable XSAVE if supported and allowed by user. 199 * Calculate the xsave_mask. 200 */ 201static void 202fpuinit_bsp1(void) 203{ 204 u_int cp[4]; 205 uint64_t xsave_mask_user; 206 207 if ((cpu_feature2 & CPUID2_XSAVE) != 0) { 208 use_xsave = 1; 209 TUNABLE_INT_FETCH("hw.use_xsave", &use_xsave); 210 } 211 if (!use_xsave) 212 return; 213 214 cpuid_count(0xd, 0x0, cp); 215 xsave_mask = XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE; 216 if ((cp[0] & xsave_mask) != xsave_mask) 217 panic("CPU0 does not support X87 or SSE: %x", cp[0]); 218 xsave_mask = ((uint64_t)cp[3] << 32) | cp[0]; 219 xsave_mask_user = xsave_mask; 220 TUNABLE_ULONG_FETCH("hw.xsave_mask", &xsave_mask_user); 221 xsave_mask_user |= XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE; 222 xsave_mask &= xsave_mask_user; 223 if ((xsave_mask & XFEATURE_AVX512) != XFEATURE_AVX512) 224 xsave_mask &= ~XFEATURE_AVX512; 225 if ((xsave_mask & XFEATURE_MPX) != XFEATURE_MPX) 226 xsave_mask &= ~XFEATURE_MPX; 227 228 cpuid_count(0xd, 0x1, cp); 229 if ((cp[0] & CPUID_EXTSTATE_XSAVEOPT) != 0) { 230 /* 231 * Patch the XSAVE instruction in the cpu_switch code 232 * to XSAVEOPT. We assume that XSAVE encoding used 233 * REX byte, and set the bit 4 of the r/m byte. 234 */ 235 ctx_switch_xsave[3] |= 0x10; 236 } 237} 238 239/* 240 * Calculate the fpu save area size. 241 */ 242static void 243fpuinit_bsp2(void) 244{ 245 u_int cp[4]; 246 247 if (use_xsave) { 248 cpuid_count(0xd, 0x0, cp); 249 cpu_max_ext_state_size = cp[1]; 250 251 /* 252 * Reload the cpu_feature2, since we enabled OSXSAVE. 253 */ 254 do_cpuid(1, cp); 255 cpu_feature2 = cp[2]; 256 } else 257 cpu_max_ext_state_size = sizeof(struct savefpu); 258} 259 260/* 261 * Initialize the floating point unit. 262 */ 263void 264fpuinit(void) 265{ 266 register_t saveintr; 267 u_int mxcsr; 268 u_short control; 269 270 if (IS_BSP()) 271 fpuinit_bsp1(); 272 273 if (use_xsave) { 274 load_cr4(rcr4() | CR4_XSAVE); 275 load_xcr(XCR0, xsave_mask); 276 } 277 278 /* 279 * XCR0 shall be set up before CPU can report the save area size. 280 */ 281 if (IS_BSP()) 282 fpuinit_bsp2(); 283 284 /* 285 * It is too early for critical_enter() to work on AP. 286 */ 287 saveintr = intr_disable(); 288 stop_emulating(); 289 fninit(); 290 control = __INITIAL_FPUCW__; 291 fldcw(control); 292 mxcsr = __INITIAL_MXCSR__; 293 ldmxcsr(mxcsr); 294 start_emulating(); 295 intr_restore(saveintr); 296} 297 298/* 299 * On the boot CPU we generate a clean state that is used to 300 * initialize the floating point unit when it is first used by a 301 * process. 302 */ 303static void 304fpuinitstate(void *arg __unused) 305{ 306 register_t saveintr; 307 int cp[4], i, max_ext_n; 308 309 fpu_initialstate = malloc(cpu_max_ext_state_size, M_DEVBUF, 310 M_WAITOK | M_ZERO); 311 saveintr = intr_disable(); 312 stop_emulating(); 313 314 fpusave(fpu_initialstate); 315 if (fpu_initialstate->sv_env.en_mxcsr_mask) 316 cpu_mxcsr_mask = fpu_initialstate->sv_env.en_mxcsr_mask; 317 else 318 cpu_mxcsr_mask = 0xFFBF; 319 320 /* 321 * The fninit instruction does not modify XMM registers or x87 322 * registers (MM/ST). The fpusave call dumped the garbage 323 * contained in the registers after reset to the initial state 324 * saved. Clear XMM and x87 registers file image to make the 325 * startup program state and signal handler XMM/x87 register 326 * content predictable. 327 */ 328 bzero(fpu_initialstate->sv_fp, sizeof(fpu_initialstate->sv_fp)); 329 bzero(fpu_initialstate->sv_xmm, sizeof(fpu_initialstate->sv_xmm)); 330 331 /* 332 * Create a table describing the layout of the CPU Extended 333 * Save Area. 334 */ 335 if (use_xsave) { 336 max_ext_n = flsl(xsave_mask); 337 xsave_area_desc = malloc(max_ext_n * sizeof(struct 338 xsave_area_elm_descr), M_DEVBUF, M_WAITOK | M_ZERO); 339 /* x87 state */ 340 xsave_area_desc[0].offset = 0; 341 xsave_area_desc[0].size = 160; 342 /* XMM */ 343 xsave_area_desc[1].offset = 160; 344 xsave_area_desc[1].size = 288 - 160; 345 346 for (i = 2; i < max_ext_n; i++) { 347 cpuid_count(0xd, i, cp); 348 xsave_area_desc[i].offset = cp[1]; 349 xsave_area_desc[i].size = cp[0]; 350 } 351 } 352 353 fpu_save_area_zone = uma_zcreate("FPU_save_area", 354 cpu_max_ext_state_size, NULL, NULL, NULL, NULL, 355 XSAVE_AREA_ALIGN - 1, 0); 356 357 start_emulating(); 358 intr_restore(saveintr); 359} 360/* EFIRT needs this to be initialized before we can enter our EFI environment */ 361SYSINIT(fpuinitstate, SI_SUB_DRIVERS, SI_ORDER_FIRST, fpuinitstate, NULL); 362 363/* 364 * Free coprocessor (if we have it). 365 */ 366void 367fpuexit(struct thread *td) 368{ 369 370 critical_enter(); 371 if (curthread == PCPU_GET(fpcurthread)) { 372 stop_emulating(); 373 fpusave(curpcb->pcb_save); 374 start_emulating(); 375 PCPU_SET(fpcurthread, NULL); 376 } 377 critical_exit(); 378} 379 380int 381fpuformat(void) 382{ 383 384 return (_MC_FPFMT_XMM); 385} 386 387/* 388 * The following mechanism is used to ensure that the FPE_... value 389 * that is passed as a trapcode to the signal handler of the user 390 * process does not have more than one bit set. 391 * 392 * Multiple bits may be set if the user process modifies the control 393 * word while a status word bit is already set. While this is a sign 394 * of bad coding, we have no choise than to narrow them down to one 395 * bit, since we must not send a trapcode that is not exactly one of 396 * the FPE_ macros. 397 * 398 * The mechanism has a static table with 127 entries. Each combination 399 * of the 7 FPU status word exception bits directly translates to a 400 * position in this table, where a single FPE_... value is stored. 401 * This FPE_... value stored there is considered the "most important" 402 * of the exception bits and will be sent as the signal code. The 403 * precedence of the bits is based upon Intel Document "Numerical 404 * Applications", Chapter "Special Computational Situations". 405 * 406 * The macro to choose one of these values does these steps: 1) Throw 407 * away status word bits that cannot be masked. 2) Throw away the bits 408 * currently masked in the control word, assuming the user isn't 409 * interested in them anymore. 3) Reinsert status word bit 7 (stack 410 * fault) if it is set, which cannot be masked but must be presered. 411 * 4) Use the remaining bits to point into the trapcode table. 412 * 413 * The 6 maskable bits in order of their preference, as stated in the 414 * above referenced Intel manual: 415 * 1 Invalid operation (FP_X_INV) 416 * 1a Stack underflow 417 * 1b Stack overflow 418 * 1c Operand of unsupported format 419 * 1d SNaN operand. 420 * 2 QNaN operand (not an exception, irrelavant here) 421 * 3 Any other invalid-operation not mentioned above or zero divide 422 * (FP_X_INV, FP_X_DZ) 423 * 4 Denormal operand (FP_X_DNML) 424 * 5 Numeric over/underflow (FP_X_OFL, FP_X_UFL) 425 * 6 Inexact result (FP_X_IMP) 426 */ 427static char fpetable[128] = { 428 0, 429 FPE_FLTINV, /* 1 - INV */ 430 FPE_FLTUND, /* 2 - DNML */ 431 FPE_FLTINV, /* 3 - INV | DNML */ 432 FPE_FLTDIV, /* 4 - DZ */ 433 FPE_FLTINV, /* 5 - INV | DZ */ 434 FPE_FLTDIV, /* 6 - DNML | DZ */ 435 FPE_FLTINV, /* 7 - INV | DNML | DZ */ 436 FPE_FLTOVF, /* 8 - OFL */ 437 FPE_FLTINV, /* 9 - INV | OFL */ 438 FPE_FLTUND, /* A - DNML | OFL */ 439 FPE_FLTINV, /* B - INV | DNML | OFL */ 440 FPE_FLTDIV, /* C - DZ | OFL */ 441 FPE_FLTINV, /* D - INV | DZ | OFL */ 442 FPE_FLTDIV, /* E - DNML | DZ | OFL */ 443 FPE_FLTINV, /* F - INV | DNML | DZ | OFL */ 444 FPE_FLTUND, /* 10 - UFL */ 445 FPE_FLTINV, /* 11 - INV | UFL */ 446 FPE_FLTUND, /* 12 - DNML | UFL */ 447 FPE_FLTINV, /* 13 - INV | DNML | UFL */ 448 FPE_FLTDIV, /* 14 - DZ | UFL */ 449 FPE_FLTINV, /* 15 - INV | DZ | UFL */ 450 FPE_FLTDIV, /* 16 - DNML | DZ | UFL */ 451 FPE_FLTINV, /* 17 - INV | DNML | DZ | UFL */ 452 FPE_FLTOVF, /* 18 - OFL | UFL */ 453 FPE_FLTINV, /* 19 - INV | OFL | UFL */ 454 FPE_FLTUND, /* 1A - DNML | OFL | UFL */ 455 FPE_FLTINV, /* 1B - INV | DNML | OFL | UFL */ 456 FPE_FLTDIV, /* 1C - DZ | OFL | UFL */ 457 FPE_FLTINV, /* 1D - INV | DZ | OFL | UFL */ 458 FPE_FLTDIV, /* 1E - DNML | DZ | OFL | UFL */ 459 FPE_FLTINV, /* 1F - INV | DNML | DZ | OFL | UFL */ 460 FPE_FLTRES, /* 20 - IMP */ 461 FPE_FLTINV, /* 21 - INV | IMP */ 462 FPE_FLTUND, /* 22 - DNML | IMP */ 463 FPE_FLTINV, /* 23 - INV | DNML | IMP */ 464 FPE_FLTDIV, /* 24 - DZ | IMP */ 465 FPE_FLTINV, /* 25 - INV | DZ | IMP */ 466 FPE_FLTDIV, /* 26 - DNML | DZ | IMP */ 467 FPE_FLTINV, /* 27 - INV | DNML | DZ | IMP */ 468 FPE_FLTOVF, /* 28 - OFL | IMP */ 469 FPE_FLTINV, /* 29 - INV | OFL | IMP */ 470 FPE_FLTUND, /* 2A - DNML | OFL | IMP */ 471 FPE_FLTINV, /* 2B - INV | DNML | OFL | IMP */ 472 FPE_FLTDIV, /* 2C - DZ | OFL | IMP */ 473 FPE_FLTINV, /* 2D - INV | DZ | OFL | IMP */ 474 FPE_FLTDIV, /* 2E - DNML | DZ | OFL | IMP */ 475 FPE_FLTINV, /* 2F - INV | DNML | DZ | OFL | IMP */ 476 FPE_FLTUND, /* 30 - UFL | IMP */ 477 FPE_FLTINV, /* 31 - INV | UFL | IMP */ 478 FPE_FLTUND, /* 32 - DNML | UFL | IMP */ 479 FPE_FLTINV, /* 33 - INV | DNML | UFL | IMP */ 480 FPE_FLTDIV, /* 34 - DZ | UFL | IMP */ 481 FPE_FLTINV, /* 35 - INV | DZ | UFL | IMP */ 482 FPE_FLTDIV, /* 36 - DNML | DZ | UFL | IMP */ 483 FPE_FLTINV, /* 37 - INV | DNML | DZ | UFL | IMP */ 484 FPE_FLTOVF, /* 38 - OFL | UFL | IMP */ 485 FPE_FLTINV, /* 39 - INV | OFL | UFL | IMP */ 486 FPE_FLTUND, /* 3A - DNML | OFL | UFL | IMP */ 487 FPE_FLTINV, /* 3B - INV | DNML | OFL | UFL | IMP */ 488 FPE_FLTDIV, /* 3C - DZ | OFL | UFL | IMP */ 489 FPE_FLTINV, /* 3D - INV | DZ | OFL | UFL | IMP */ 490 FPE_FLTDIV, /* 3E - DNML | DZ | OFL | UFL | IMP */ 491 FPE_FLTINV, /* 3F - INV | DNML | DZ | OFL | UFL | IMP */ 492 FPE_FLTSUB, /* 40 - STK */ 493 FPE_FLTSUB, /* 41 - INV | STK */ 494 FPE_FLTUND, /* 42 - DNML | STK */ 495 FPE_FLTSUB, /* 43 - INV | DNML | STK */ 496 FPE_FLTDIV, /* 44 - DZ | STK */ 497 FPE_FLTSUB, /* 45 - INV | DZ | STK */ 498 FPE_FLTDIV, /* 46 - DNML | DZ | STK */ 499 FPE_FLTSUB, /* 47 - INV | DNML | DZ | STK */ 500 FPE_FLTOVF, /* 48 - OFL | STK */ 501 FPE_FLTSUB, /* 49 - INV | OFL | STK */ 502 FPE_FLTUND, /* 4A - DNML | OFL | STK */ 503 FPE_FLTSUB, /* 4B - INV | DNML | OFL | STK */ 504 FPE_FLTDIV, /* 4C - DZ | OFL | STK */ 505 FPE_FLTSUB, /* 4D - INV | DZ | OFL | STK */ 506 FPE_FLTDIV, /* 4E - DNML | DZ | OFL | STK */ 507 FPE_FLTSUB, /* 4F - INV | DNML | DZ | OFL | STK */ 508 FPE_FLTUND, /* 50 - UFL | STK */ 509 FPE_FLTSUB, /* 51 - INV | UFL | STK */ 510 FPE_FLTUND, /* 52 - DNML | UFL | STK */ 511 FPE_FLTSUB, /* 53 - INV | DNML | UFL | STK */ 512 FPE_FLTDIV, /* 54 - DZ | UFL | STK */ 513 FPE_FLTSUB, /* 55 - INV | DZ | UFL | STK */ 514 FPE_FLTDIV, /* 56 - DNML | DZ | UFL | STK */ 515 FPE_FLTSUB, /* 57 - INV | DNML | DZ | UFL | STK */ 516 FPE_FLTOVF, /* 58 - OFL | UFL | STK */ 517 FPE_FLTSUB, /* 59 - INV | OFL | UFL | STK */ 518 FPE_FLTUND, /* 5A - DNML | OFL | UFL | STK */ 519 FPE_FLTSUB, /* 5B - INV | DNML | OFL | UFL | STK */ 520 FPE_FLTDIV, /* 5C - DZ | OFL | UFL | STK */ 521 FPE_FLTSUB, /* 5D - INV | DZ | OFL | UFL | STK */ 522 FPE_FLTDIV, /* 5E - DNML | DZ | OFL | UFL | STK */ 523 FPE_FLTSUB, /* 5F - INV | DNML | DZ | OFL | UFL | STK */ 524 FPE_FLTRES, /* 60 - IMP | STK */ 525 FPE_FLTSUB, /* 61 - INV | IMP | STK */ 526 FPE_FLTUND, /* 62 - DNML | IMP | STK */ 527 FPE_FLTSUB, /* 63 - INV | DNML | IMP | STK */ 528 FPE_FLTDIV, /* 64 - DZ | IMP | STK */ 529 FPE_FLTSUB, /* 65 - INV | DZ | IMP | STK */ 530 FPE_FLTDIV, /* 66 - DNML | DZ | IMP | STK */ 531 FPE_FLTSUB, /* 67 - INV | DNML | DZ | IMP | STK */ 532 FPE_FLTOVF, /* 68 - OFL | IMP | STK */ 533 FPE_FLTSUB, /* 69 - INV | OFL | IMP | STK */ 534 FPE_FLTUND, /* 6A - DNML | OFL | IMP | STK */ 535 FPE_FLTSUB, /* 6B - INV | DNML | OFL | IMP | STK */ 536 FPE_FLTDIV, /* 6C - DZ | OFL | IMP | STK */ 537 FPE_FLTSUB, /* 6D - INV | DZ | OFL | IMP | STK */ 538 FPE_FLTDIV, /* 6E - DNML | DZ | OFL | IMP | STK */ 539 FPE_FLTSUB, /* 6F - INV | DNML | DZ | OFL | IMP | STK */ 540 FPE_FLTUND, /* 70 - UFL | IMP | STK */ 541 FPE_FLTSUB, /* 71 - INV | UFL | IMP | STK */ 542 FPE_FLTUND, /* 72 - DNML | UFL | IMP | STK */ 543 FPE_FLTSUB, /* 73 - INV | DNML | UFL | IMP | STK */ 544 FPE_FLTDIV, /* 74 - DZ | UFL | IMP | STK */ 545 FPE_FLTSUB, /* 75 - INV | DZ | UFL | IMP | STK */ 546 FPE_FLTDIV, /* 76 - DNML | DZ | UFL | IMP | STK */ 547 FPE_FLTSUB, /* 77 - INV | DNML | DZ | UFL | IMP | STK */ 548 FPE_FLTOVF, /* 78 - OFL | UFL | IMP | STK */ 549 FPE_FLTSUB, /* 79 - INV | OFL | UFL | IMP | STK */ 550 FPE_FLTUND, /* 7A - DNML | OFL | UFL | IMP | STK */ 551 FPE_FLTSUB, /* 7B - INV | DNML | OFL | UFL | IMP | STK */ 552 FPE_FLTDIV, /* 7C - DZ | OFL | UFL | IMP | STK */ 553 FPE_FLTSUB, /* 7D - INV | DZ | OFL | UFL | IMP | STK */ 554 FPE_FLTDIV, /* 7E - DNML | DZ | OFL | UFL | IMP | STK */ 555 FPE_FLTSUB, /* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */ 556}; 557 558/* 559 * Read the FP status and control words, then generate si_code value 560 * for SIGFPE. The error code chosen will be one of the 561 * FPE_... macros. It will be sent as the second argument to old 562 * BSD-style signal handlers and as "siginfo_t->si_code" (second 563 * argument) to SA_SIGINFO signal handlers. 564 * 565 * Some time ago, we cleared the x87 exceptions with FNCLEX there. 566 * Clearing exceptions was necessary mainly to avoid IRQ13 bugs. The 567 * usermode code which understands the FPU hardware enough to enable 568 * the exceptions, can also handle clearing the exception state in the 569 * handler. The only consequence of not clearing the exception is the 570 * rethrow of the SIGFPE on return from the signal handler and 571 * reexecution of the corresponding instruction. 572 * 573 * For XMM traps, the exceptions were never cleared. 574 */ 575int 576fputrap_x87(void) 577{ 578 struct savefpu *pcb_save; 579 u_short control, status; 580 581 critical_enter(); 582 583 /* 584 * Interrupt handling (for another interrupt) may have pushed the 585 * state to memory. Fetch the relevant parts of the state from 586 * wherever they are. 587 */ 588 if (PCPU_GET(fpcurthread) != curthread) { 589 pcb_save = curpcb->pcb_save; 590 control = pcb_save->sv_env.en_cw; 591 status = pcb_save->sv_env.en_sw; 592 } else { 593 fnstcw(&control); 594 fnstsw(&status); 595 } 596 597 critical_exit(); 598 return (fpetable[status & ((~control & 0x3f) | 0x40)]); 599} 600 601int 602fputrap_sse(void) 603{ 604 u_int mxcsr; 605 606 critical_enter(); 607 if (PCPU_GET(fpcurthread) != curthread) 608 mxcsr = curpcb->pcb_save->sv_env.en_mxcsr; 609 else 610 stmxcsr(&mxcsr); 611 critical_exit(); 612 return (fpetable[(mxcsr & (~mxcsr >> 7)) & 0x3f]); 613} 614 615/* 616 * Device Not Available (DNA, #NM) exception handler. 617 * 618 * It would be better to switch FP context here (if curthread != 619 * fpcurthread) and not necessarily for every context switch, but it 620 * is too hard to access foreign pcb's. 621 */ 622void 623fpudna(void) 624{ 625 626 /* 627 * This handler is entered with interrupts enabled, so context 628 * switches may occur before critical_enter() is executed. If 629 * a context switch occurs, then when we regain control, our 630 * state will have been completely restored. The CPU may 631 * change underneath us, but the only part of our context that 632 * lives in the CPU is CR0.TS and that will be "restored" by 633 * setting it on the new CPU. 634 */ 635 critical_enter(); 636 637 KASSERT((curpcb->pcb_flags & PCB_FPUNOSAVE) == 0, 638 ("fpudna while in fpu_kern_enter(FPU_KERN_NOCTX)")); 639 if (PCPU_GET(fpcurthread) == curthread) { 640 printf("fpudna: fpcurthread == curthread\n"); 641 stop_emulating(); 642 critical_exit(); 643 return; 644 } 645 if (PCPU_GET(fpcurthread) != NULL) { 646 panic("fpudna: fpcurthread = %p (%d), curthread = %p (%d)\n", 647 PCPU_GET(fpcurthread), PCPU_GET(fpcurthread)->td_tid, 648 curthread, curthread->td_tid); 649 } 650 stop_emulating(); 651 /* 652 * Record new context early in case frstor causes a trap. 653 */ 654 PCPU_SET(fpcurthread, curthread); 655 656 fpu_clean_state(); 657 658 if ((curpcb->pcb_flags & PCB_FPUINITDONE) == 0) { 659 /* 660 * This is the first time this thread has used the FPU or 661 * the PCB doesn't contain a clean FPU state. Explicitly 662 * load an initial state. 663 * 664 * We prefer to restore the state from the actual save 665 * area in PCB instead of directly loading from 666 * fpu_initialstate, to ignite the XSAVEOPT 667 * tracking engine. 668 */ 669 bcopy(fpu_initialstate, curpcb->pcb_save, 670 cpu_max_ext_state_size); 671 fpurestore(curpcb->pcb_save); 672 if (curpcb->pcb_initial_fpucw != __INITIAL_FPUCW__) 673 fldcw(curpcb->pcb_initial_fpucw); 674 if (PCB_USER_FPU(curpcb)) 675 set_pcb_flags(curpcb, 676 PCB_FPUINITDONE | PCB_USERFPUINITDONE); 677 else 678 set_pcb_flags(curpcb, PCB_FPUINITDONE); 679 } else 680 fpurestore(curpcb->pcb_save); 681 critical_exit(); 682} 683 684void 685fpudrop(void) 686{ 687 struct thread *td; 688 689 td = PCPU_GET(fpcurthread); 690 KASSERT(td == curthread, ("fpudrop: fpcurthread != curthread")); 691 CRITICAL_ASSERT(td); 692 PCPU_SET(fpcurthread, NULL); 693 clear_pcb_flags(td->td_pcb, PCB_FPUINITDONE); 694 start_emulating(); 695} 696 697/* 698 * Get the user state of the FPU into pcb->pcb_user_save without 699 * dropping ownership (if possible). It returns the FPU ownership 700 * status. 701 */ 702int 703fpugetregs(struct thread *td) 704{ 705 struct pcb *pcb; 706 uint64_t *xstate_bv, bit; 707 char *sa; 708 int max_ext_n, i, owned; 709 710 pcb = td->td_pcb; 711 if ((pcb->pcb_flags & PCB_USERFPUINITDONE) == 0) { 712 bcopy(fpu_initialstate, get_pcb_user_save_pcb(pcb), 713 cpu_max_ext_state_size); 714 get_pcb_user_save_pcb(pcb)->sv_env.en_cw = 715 pcb->pcb_initial_fpucw; 716 fpuuserinited(td); 717 return (_MC_FPOWNED_PCB); 718 } 719 critical_enter(); 720 if (td == PCPU_GET(fpcurthread) && PCB_USER_FPU(pcb)) { 721 fpusave(get_pcb_user_save_pcb(pcb)); 722 owned = _MC_FPOWNED_FPU; 723 } else { 724 owned = _MC_FPOWNED_PCB; 725 } 726 critical_exit(); 727 if (use_xsave) { 728 /* 729 * Handle partially saved state. 730 */ 731 sa = (char *)get_pcb_user_save_pcb(pcb); 732 xstate_bv = (uint64_t *)(sa + sizeof(struct savefpu) + 733 offsetof(struct xstate_hdr, xstate_bv)); 734 max_ext_n = flsl(xsave_mask); 735 for (i = 0; i < max_ext_n; i++) { 736 bit = 1ULL << i; 737 if ((xsave_mask & bit) == 0 || (*xstate_bv & bit) != 0) 738 continue; 739 bcopy((char *)fpu_initialstate + 740 xsave_area_desc[i].offset, 741 sa + xsave_area_desc[i].offset, 742 xsave_area_desc[i].size); 743 *xstate_bv |= bit; 744 } 745 } 746 return (owned); 747} 748 749void 750fpuuserinited(struct thread *td) 751{ 752 struct pcb *pcb; 753 754 pcb = td->td_pcb; 755 if (PCB_USER_FPU(pcb)) 756 set_pcb_flags(pcb, 757 PCB_FPUINITDONE | PCB_USERFPUINITDONE); 758 else 759 set_pcb_flags(pcb, PCB_FPUINITDONE); 760} 761 762int 763fpusetxstate(struct thread *td, char *xfpustate, size_t xfpustate_size) 764{ 765 struct xstate_hdr *hdr, *ehdr; 766 size_t len, max_len; 767 uint64_t bv; 768 769 /* XXXKIB should we clear all extended state in xstate_bv instead ? */ 770 if (xfpustate == NULL) 771 return (0); 772 if (!use_xsave) 773 return (EOPNOTSUPP); 774 775 len = xfpustate_size; 776 if (len < sizeof(struct xstate_hdr)) 777 return (EINVAL); 778 max_len = cpu_max_ext_state_size - sizeof(struct savefpu); 779 if (len > max_len) 780 return (EINVAL); 781 782 ehdr = (struct xstate_hdr *)xfpustate; 783 bv = ehdr->xstate_bv; 784 785 /* 786 * Avoid #gp. 787 */ 788 if (bv & ~xsave_mask) 789 return (EINVAL); 790 791 hdr = (struct xstate_hdr *)(get_pcb_user_save_td(td) + 1); 792 793 hdr->xstate_bv = bv; 794 bcopy(xfpustate + sizeof(struct xstate_hdr), 795 (char *)(hdr + 1), len - sizeof(struct xstate_hdr)); 796 797 return (0); 798} 799 800/* 801 * Set the state of the FPU. 802 */ 803int 804fpusetregs(struct thread *td, struct savefpu *addr, char *xfpustate, 805 size_t xfpustate_size) 806{ 807 struct pcb *pcb; 808 int error; 809 810 addr->sv_env.en_mxcsr &= cpu_mxcsr_mask; 811 pcb = td->td_pcb; 812 critical_enter(); 813 if (td == PCPU_GET(fpcurthread) && PCB_USER_FPU(pcb)) { 814 error = fpusetxstate(td, xfpustate, xfpustate_size); 815 if (error != 0) { 816 critical_exit(); 817 return (error); 818 } 819 bcopy(addr, get_pcb_user_save_td(td), sizeof(*addr)); 820 fpurestore(get_pcb_user_save_td(td)); 821 critical_exit(); 822 set_pcb_flags(pcb, PCB_FPUINITDONE | PCB_USERFPUINITDONE); 823 } else { 824 critical_exit(); 825 error = fpusetxstate(td, xfpustate, xfpustate_size); 826 if (error != 0) 827 return (error); 828 bcopy(addr, get_pcb_user_save_td(td), sizeof(*addr)); 829 fpuuserinited(td); 830 } 831 return (0); 832} 833 834/* 835 * On AuthenticAMD processors, the fxrstor instruction does not restore 836 * the x87's stored last instruction pointer, last data pointer, and last 837 * opcode values, except in the rare case in which the exception summary 838 * (ES) bit in the x87 status word is set to 1. 839 * 840 * In order to avoid leaking this information across processes, we clean 841 * these values by performing a dummy load before executing fxrstor(). 842 */ 843static void 844fpu_clean_state(void) 845{ 846 static float dummy_variable = 0.0; 847 u_short status; 848 849 /* 850 * Clear the ES bit in the x87 status word if it is currently 851 * set, in order to avoid causing a fault in the upcoming load. 852 */ 853 fnstsw(&status); 854 if (status & 0x80) 855 fnclex(); 856 857 /* 858 * Load the dummy variable into the x87 stack. This mangles 859 * the x87 stack, but we don't care since we're about to call 860 * fxrstor() anyway. 861 */ 862 __asm __volatile("ffree %%st(7); flds %0" : : "m" (dummy_variable)); 863} 864 865/* 866 * This really sucks. We want the acpi version only, but it requires 867 * the isa_if.h file in order to get the definitions. 868 */ 869#include "opt_isa.h" 870#ifdef DEV_ISA 871#include <isa/isavar.h> 872/* 873 * This sucks up the legacy ISA support assignments from PNPBIOS/ACPI. 874 */ 875static struct isa_pnp_id fpupnp_ids[] = { 876 { 0x040cd041, "Legacy ISA coprocessor support" }, /* PNP0C04 */ 877 { 0 } 878}; 879 880static int 881fpupnp_probe(device_t dev) 882{ 883 int result; 884 885 result = ISA_PNP_PROBE(device_get_parent(dev), dev, fpupnp_ids); 886 if (result <= 0) 887 device_quiet(dev); 888 return (result); 889} 890 891static int 892fpupnp_attach(device_t dev) 893{ 894 895 return (0); 896} 897 898static device_method_t fpupnp_methods[] = { 899 /* Device interface */ 900 DEVMETHOD(device_probe, fpupnp_probe), 901 DEVMETHOD(device_attach, fpupnp_attach), 902 DEVMETHOD(device_detach, bus_generic_detach), 903 DEVMETHOD(device_shutdown, bus_generic_shutdown), 904 DEVMETHOD(device_suspend, bus_generic_suspend), 905 DEVMETHOD(device_resume, bus_generic_resume), 906 907 { 0, 0 } 908}; 909 910static driver_t fpupnp_driver = { 911 "fpupnp", 912 fpupnp_methods, 913 1, /* no softc */ 914}; 915 916static devclass_t fpupnp_devclass; 917 918DRIVER_MODULE(fpupnp, acpi, fpupnp_driver, fpupnp_devclass, 0, 0); 919#endif /* DEV_ISA */ 920 921static MALLOC_DEFINE(M_FPUKERN_CTX, "fpukern_ctx", 922 "Kernel contexts for FPU state"); 923 924#define FPU_KERN_CTX_FPUINITDONE 0x01 925#define FPU_KERN_CTX_DUMMY 0x02 /* avoided save for the kern thread */ 926#define FPU_KERN_CTX_INUSE 0x04 927 928struct fpu_kern_ctx { 929 struct savefpu *prev; 930 uint32_t flags; 931 char hwstate1[]; 932}; 933 934struct fpu_kern_ctx * 935fpu_kern_alloc_ctx(u_int flags) 936{ 937 struct fpu_kern_ctx *res; 938 size_t sz; 939 940 sz = sizeof(struct fpu_kern_ctx) + XSAVE_AREA_ALIGN + 941 cpu_max_ext_state_size; 942 res = malloc(sz, M_FPUKERN_CTX, ((flags & FPU_KERN_NOWAIT) ? 943 M_NOWAIT : M_WAITOK) | M_ZERO); 944 return (res); 945} 946 947void 948fpu_kern_free_ctx(struct fpu_kern_ctx *ctx) 949{ 950 951 KASSERT((ctx->flags & FPU_KERN_CTX_INUSE) == 0, ("free'ing inuse ctx")); 952 /* XXXKIB clear the memory ? */ 953 free(ctx, M_FPUKERN_CTX); 954} 955 956static struct savefpu * 957fpu_kern_ctx_savefpu(struct fpu_kern_ctx *ctx) 958{ 959 vm_offset_t p; 960 961 p = (vm_offset_t)&ctx->hwstate1; 962 p = roundup2(p, XSAVE_AREA_ALIGN); 963 return ((struct savefpu *)p); 964} 965 966int 967fpu_kern_enter(struct thread *td, struct fpu_kern_ctx *ctx, u_int flags) 968{ 969 struct pcb *pcb; 970 971 pcb = td->td_pcb; 972 KASSERT((flags & FPU_KERN_NOCTX) != 0 || ctx != NULL, 973 ("ctx is required when !FPU_KERN_NOCTX")); 974 KASSERT(ctx == NULL || (ctx->flags & FPU_KERN_CTX_INUSE) == 0, 975 ("using inuse ctx")); 976 KASSERT((pcb->pcb_flags & PCB_FPUNOSAVE) == 0, 977 ("recursive fpu_kern_enter while in PCB_FPUNOSAVE state")); 978 979 if ((flags & FPU_KERN_NOCTX) != 0) { 980 critical_enter(); 981 stop_emulating(); 982 if (curthread == PCPU_GET(fpcurthread)) { 983 fpusave(curpcb->pcb_save); 984 PCPU_SET(fpcurthread, NULL); 985 } else { 986 KASSERT(PCPU_GET(fpcurthread) == NULL, 987 ("invalid fpcurthread")); 988 } 989 990 /* 991 * This breaks XSAVEOPT tracker, but 992 * PCB_FPUNOSAVE state is supposed to never need to 993 * save FPU context at all. 994 */ 995 fpurestore(fpu_initialstate); 996 set_pcb_flags(pcb, PCB_KERNFPU | PCB_FPUNOSAVE | 997 PCB_FPUINITDONE); 998 return (0); 999 } 1000 if ((flags & FPU_KERN_KTHR) != 0 && is_fpu_kern_thread(0)) { 1001 ctx->flags = FPU_KERN_CTX_DUMMY | FPU_KERN_CTX_INUSE; 1002 return (0); 1003 } 1004 KASSERT(!PCB_USER_FPU(pcb) || pcb->pcb_save == 1005 get_pcb_user_save_pcb(pcb), ("mangled pcb_save")); 1006 ctx->flags = FPU_KERN_CTX_INUSE; 1007 if ((pcb->pcb_flags & PCB_FPUINITDONE) != 0) 1008 ctx->flags |= FPU_KERN_CTX_FPUINITDONE; 1009 fpuexit(td); 1010 ctx->prev = pcb->pcb_save; 1011 pcb->pcb_save = fpu_kern_ctx_savefpu(ctx); 1012 set_pcb_flags(pcb, PCB_KERNFPU); 1013 clear_pcb_flags(pcb, PCB_FPUINITDONE); 1014 return (0); 1015} 1016 1017int 1018fpu_kern_leave(struct thread *td, struct fpu_kern_ctx *ctx) 1019{ 1020 struct pcb *pcb; 1021 1022 pcb = td->td_pcb; 1023 1024 if ((pcb->pcb_flags & PCB_FPUNOSAVE) != 0) { 1025 KASSERT(ctx == NULL, ("non-null ctx after FPU_KERN_NOCTX")); 1026 KASSERT(PCPU_GET(fpcurthread) == NULL, 1027 ("non-NULL fpcurthread for PCB_FPUNOSAVE")); 1028 CRITICAL_ASSERT(td); 1029 1030 clear_pcb_flags(pcb, PCB_FPUNOSAVE | PCB_FPUINITDONE); 1031 start_emulating(); 1032 critical_exit(); 1033 } else { 1034 KASSERT((ctx->flags & FPU_KERN_CTX_INUSE) != 0, 1035 ("leaving not inuse ctx")); 1036 ctx->flags &= ~FPU_KERN_CTX_INUSE; 1037 1038 if (is_fpu_kern_thread(0) && 1039 (ctx->flags & FPU_KERN_CTX_DUMMY) != 0) 1040 return (0); 1041 KASSERT((ctx->flags & FPU_KERN_CTX_DUMMY) == 0, 1042 ("dummy ctx")); 1043 critical_enter(); 1044 if (curthread == PCPU_GET(fpcurthread)) 1045 fpudrop(); 1046 critical_exit(); 1047 pcb->pcb_save = ctx->prev; 1048 } 1049 1050 if (pcb->pcb_save == get_pcb_user_save_pcb(pcb)) { 1051 if ((pcb->pcb_flags & PCB_USERFPUINITDONE) != 0) { 1052 set_pcb_flags(pcb, PCB_FPUINITDONE); 1053 clear_pcb_flags(pcb, PCB_KERNFPU); 1054 } else 1055 clear_pcb_flags(pcb, PCB_FPUINITDONE | PCB_KERNFPU); 1056 } else { 1057 if ((ctx->flags & FPU_KERN_CTX_FPUINITDONE) != 0) 1058 set_pcb_flags(pcb, PCB_FPUINITDONE); 1059 else 1060 clear_pcb_flags(pcb, PCB_FPUINITDONE); 1061 KASSERT(!PCB_USER_FPU(pcb), ("unpaired fpu_kern_leave")); 1062 } 1063 return (0); 1064} 1065 1066int 1067fpu_kern_thread(u_int flags) 1068{ 1069 1070 KASSERT((curthread->td_pflags & TDP_KTHREAD) != 0, 1071 ("Only kthread may use fpu_kern_thread")); 1072 KASSERT(curpcb->pcb_save == get_pcb_user_save_pcb(curpcb), 1073 ("mangled pcb_save")); 1074 KASSERT(PCB_USER_FPU(curpcb), ("recursive call")); 1075 1076 set_pcb_flags(curpcb, PCB_KERNFPU); 1077 return (0); 1078} 1079 1080int 1081is_fpu_kern_thread(u_int flags) 1082{ 1083 1084 if ((curthread->td_pflags & TDP_KTHREAD) == 0) 1085 return (0); 1086 return ((curpcb->pcb_flags & PCB_KERNFPU) != 0); 1087} 1088 1089/* 1090 * FPU save area alloc/free/init utility routines 1091 */ 1092struct savefpu * 1093fpu_save_area_alloc(void) 1094{ 1095 1096 return (uma_zalloc(fpu_save_area_zone, 0)); 1097} 1098 1099void 1100fpu_save_area_free(struct savefpu *fsa) 1101{ 1102 1103 uma_zfree(fpu_save_area_zone, fsa); 1104} 1105 1106void 1107fpu_save_area_reset(struct savefpu *fsa) 1108{ 1109 1110 bcopy(fpu_initialstate, fsa, cpu_max_ext_state_size); 1111} 1112