CodeGenTarget.h revision 360784 
1//===- CodeGenTarget.h - Target Class Wrapper -------------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines wrappers for the Target class and related global
10// functionality.  This makes it easier to access the data and provides a single
11// place that needs to check it for validity.  All of these classes abort
12// on error conditions.
13//
14//===----------------------------------------------------------------------===//
15
16#ifndef LLVM_UTILS_TABLEGEN_CODEGENTARGET_H
17#define LLVM_UTILS_TABLEGEN_CODEGENTARGET_H
18
19#include "CodeGenHwModes.h"
20#include "CodeGenInstruction.h"
21#include "CodeGenRegisters.h"
22#include "InfoByHwMode.h"
23#include "SDNodeProperties.h"
24#include "llvm/Support/raw_ostream.h"
25#include "llvm/TableGen/Record.h"
26#include <algorithm>
27
28namespace llvm {
29
30struct CodeGenRegister;
31class CodeGenSchedModels;
32class CodeGenTarget;
33
34/// getValueType - Return the MVT::SimpleValueType that the specified TableGen
35/// record corresponds to.
36MVT::SimpleValueType getValueType(Record *Rec);
37
38StringRef getName(MVT::SimpleValueType T);
39StringRef getEnumName(MVT::SimpleValueType T);
40
41/// getQualifiedName - Return the name of the specified record, with a
42/// namespace qualifier if the record contains one.
43std::string getQualifiedName(const Record *R);
44
45/// CodeGenTarget - This class corresponds to the Target class in the .td files.
46///
47class CodeGenTarget {
48  RecordKeeper &Records;
49  Record *TargetRec;
50
51  mutable DenseMap<const Record*,
52                   std::unique_ptr<CodeGenInstruction>> Instructions;
53  mutable std::unique_ptr<CodeGenRegBank> RegBank;
54  mutable std::vector<Record*> RegAltNameIndices;
55  mutable SmallVector<ValueTypeByHwMode, 8> LegalValueTypes;
56  CodeGenHwModes CGH;
57  void ReadRegAltNameIndices() const;
58  void ReadInstructions() const;
59  void ReadLegalValueTypes() const;
60
61  mutable std::unique_ptr<CodeGenSchedModels> SchedModels;
62
63  mutable std::vector<const CodeGenInstruction*> InstrsByEnum;
64  mutable unsigned NumPseudoInstructions = 0;
65public:
66  CodeGenTarget(RecordKeeper &Records);
67  ~CodeGenTarget();
68
69  Record *getTargetRecord() const { return TargetRec; }
70  const StringRef getName() const;
71
72  /// getInstNamespace - Return the target-specific instruction namespace.
73  ///
74  StringRef getInstNamespace() const;
75
76  /// getInstructionSet - Return the InstructionSet object.
77  ///
78  Record *getInstructionSet() const;
79
80  /// getAllowRegisterRenaming - Return the AllowRegisterRenaming flag value for
81  /// this target.
82  ///
83  bool getAllowRegisterRenaming() const;
84
85  /// getAsmParser - Return the AssemblyParser definition for this target.
86  ///
87  Record *getAsmParser() const;
88
89  /// getAsmParserVariant - Return the AssemblyParserVariant definition for
90  /// this target.
91  ///
92  Record *getAsmParserVariant(unsigned i) const;
93
94  /// getAsmParserVariantCount - Return the AssemblyParserVariant definition
95  /// available for this target.
96  ///
97  unsigned getAsmParserVariantCount() const;
98
99  /// getAsmWriter - Return the AssemblyWriter definition for this target.
100  ///
101  Record *getAsmWriter() const;
102
103  /// getRegBank - Return the register bank description.
104  CodeGenRegBank &getRegBank() const;
105
106  /// Return the largest register class on \p RegBank which supports \p Ty and
107  /// covers \p SubIdx if it exists.
108  Optional<CodeGenRegisterClass *>
109  getSuperRegForSubReg(const ValueTypeByHwMode &Ty, CodeGenRegBank &RegBank,
110                       const CodeGenSubRegIndex *SubIdx) const;
111
112  /// getRegisterByName - If there is a register with the specific AsmName,
113  /// return it.
114  const CodeGenRegister *getRegisterByName(StringRef Name) const;
115
116  const std::vector<Record*> &getRegAltNameIndices() const {
117    if (RegAltNameIndices.empty()) ReadRegAltNameIndices();
118    return RegAltNameIndices;
119  }
120
121  const CodeGenRegisterClass &getRegisterClass(Record *R) const {
122    return *getRegBank().getRegClass(R);
123  }
124
125  /// getRegisterVTs - Find the union of all possible SimpleValueTypes for the
126  /// specified physical register.
127  std::vector<ValueTypeByHwMode> getRegisterVTs(Record *R) const;
128
129  ArrayRef<ValueTypeByHwMode> getLegalValueTypes() const {
130    if (LegalValueTypes.empty())
131      ReadLegalValueTypes();
132    return LegalValueTypes;
133  }
134
135  CodeGenSchedModels &getSchedModels() const;
136
137  const CodeGenHwModes &getHwModes() const { return CGH; }
138
139private:
140  DenseMap<const Record*, std::unique_ptr<CodeGenInstruction>> &
141  getInstructions() const {
142    if (Instructions.empty()) ReadInstructions();
143    return Instructions;
144  }
145public:
146
147  CodeGenInstruction &getInstruction(const Record *InstRec) const {
148    if (Instructions.empty()) ReadInstructions();
149    auto I = Instructions.find(InstRec);
150    assert(I != Instructions.end() && "Not an instruction");
151    return *I->second;
152  }
153
154  /// Returns the number of predefined instructions.
155  static unsigned getNumFixedInstructions();
156
157  /// Returns the number of pseudo instructions.
158  unsigned getNumPseudoInstructions() const {
159    if (InstrsByEnum.empty())
160      ComputeInstrsByEnum();
161    return NumPseudoInstructions;
162  }
163
164  /// Return all of the instructions defined by the target, ordered by their
165  /// enum value.
166  /// The following order of instructions is also guaranteed:
167  /// - fixed / generic instructions as declared in TargetOpcodes.def, in order;
168  /// - pseudo instructions in lexicographical order sorted by name;
169  /// - other instructions in lexicographical order sorted by name.
170  ArrayRef<const CodeGenInstruction *> getInstructionsByEnumValue() const {
171    if (InstrsByEnum.empty())
172      ComputeInstrsByEnum();
173    return InstrsByEnum;
174  }
175
176  typedef ArrayRef<const CodeGenInstruction *>::const_iterator inst_iterator;
177  inst_iterator inst_begin() const{return getInstructionsByEnumValue().begin();}
178  inst_iterator inst_end() const { return getInstructionsByEnumValue().end(); }
179
180
181  /// isLittleEndianEncoding - are instruction bit patterns defined as  [0..n]?
182  ///
183  bool isLittleEndianEncoding() const;
184
185  /// reverseBitsForLittleEndianEncoding - For little-endian instruction bit
186  /// encodings, reverse the bit order of all instructions.
187  void reverseBitsForLittleEndianEncoding();
188
189  /// guessInstructionProperties - should we just guess unset instruction
190  /// properties?
191  bool guessInstructionProperties() const;
192
193private:
194  void ComputeInstrsByEnum() const;
195};
196
197/// ComplexPattern - ComplexPattern info, corresponding to the ComplexPattern
198/// tablegen class in TargetSelectionDAG.td
199class ComplexPattern {
200  MVT::SimpleValueType Ty;
201  unsigned NumOperands;
202  std::string SelectFunc;
203  std::vector<Record*> RootNodes;
204  unsigned Properties; // Node properties
205  unsigned Complexity;
206public:
207  ComplexPattern(Record *R);
208
209  MVT::SimpleValueType getValueType() const { return Ty; }
210  unsigned getNumOperands() const { return NumOperands; }
211  const std::string &getSelectFunc() const { return SelectFunc; }
212  const std::vector<Record*> &getRootNodes() const {
213    return RootNodes;
214  }
215  bool hasProperty(enum SDNP Prop) const { return Properties & (1 << Prop); }
216  unsigned getComplexity() const { return Complexity; }
217};
218
219} // End llvm namespace
220
221#endif
222