CodeGenTarget.cpp revision 360784 
1//===- CodeGenTarget.cpp - CodeGen Target Class Wrapper -------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This class wraps target description classes used by the various code
10// generation TableGen backends.  This makes it easier to access the data and
11// provides a single place that needs to check it for validity.  All of these
12// classes abort on error conditions.
13//
14//===----------------------------------------------------------------------===//
15
16#include "CodeGenTarget.h"
17#include "CodeGenDAGPatterns.h"
18#include "CodeGenIntrinsics.h"
19#include "CodeGenSchedule.h"
20#include "llvm/ADT/STLExtras.h"
21#include "llvm/ADT/StringExtras.h"
22#include "llvm/Support/CommandLine.h"
23#include "llvm/Support/Timer.h"
24#include "llvm/TableGen/Error.h"
25#include "llvm/TableGen/Record.h"
26#include "llvm/TableGen/TableGenBackend.h"
27#include <algorithm>
28using namespace llvm;
29
30cl::OptionCategory AsmParserCat("Options for -gen-asm-parser");
31cl::OptionCategory AsmWriterCat("Options for -gen-asm-writer");
32
33static cl::opt<unsigned>
34    AsmParserNum("asmparsernum", cl::init(0),
35                 cl::desc("Make -gen-asm-parser emit assembly parser #N"),
36                 cl::cat(AsmParserCat));
37
38static cl::opt<unsigned>
39    AsmWriterNum("asmwriternum", cl::init(0),
40                 cl::desc("Make -gen-asm-writer emit assembly writer #N"),
41                 cl::cat(AsmWriterCat));
42
43/// getValueType - Return the MVT::SimpleValueType that the specified TableGen
44/// record corresponds to.
45MVT::SimpleValueType llvm::getValueType(Record *Rec) {
46  return (MVT::SimpleValueType)Rec->getValueAsInt("Value");
47}
48
49StringRef llvm::getName(MVT::SimpleValueType T) {
50  switch (T) {
51  case MVT::Other:   return "UNKNOWN";
52  case MVT::iPTR:    return "TLI.getPointerTy()";
53  case MVT::iPTRAny: return "TLI.getPointerTy()";
54  default: return getEnumName(T);
55  }
56}
57
58StringRef llvm::getEnumName(MVT::SimpleValueType T) {
59  switch (T) {
60  case MVT::Other:    return "MVT::Other";
61  case MVT::i1:       return "MVT::i1";
62  case MVT::i8:       return "MVT::i8";
63  case MVT::i16:      return "MVT::i16";
64  case MVT::i32:      return "MVT::i32";
65  case MVT::i64:      return "MVT::i64";
66  case MVT::i128:     return "MVT::i128";
67  case MVT::Any:      return "MVT::Any";
68  case MVT::iAny:     return "MVT::iAny";
69  case MVT::fAny:     return "MVT::fAny";
70  case MVT::vAny:     return "MVT::vAny";
71  case MVT::f16:      return "MVT::f16";
72  case MVT::f32:      return "MVT::f32";
73  case MVT::f64:      return "MVT::f64";
74  case MVT::f80:      return "MVT::f80";
75  case MVT::f128:     return "MVT::f128";
76  case MVT::ppcf128:  return "MVT::ppcf128";
77  case MVT::x86mmx:   return "MVT::x86mmx";
78  case MVT::Glue:     return "MVT::Glue";
79  case MVT::isVoid:   return "MVT::isVoid";
80  case MVT::v1i1:     return "MVT::v1i1";
81  case MVT::v2i1:     return "MVT::v2i1";
82  case MVT::v4i1:     return "MVT::v4i1";
83  case MVT::v8i1:     return "MVT::v8i1";
84  case MVT::v16i1:    return "MVT::v16i1";
85  case MVT::v32i1:    return "MVT::v32i1";
86  case MVT::v64i1:    return "MVT::v64i1";
87  case MVT::v128i1:   return "MVT::v128i1";
88  case MVT::v512i1:   return "MVT::v512i1";
89  case MVT::v1024i1:  return "MVT::v1024i1";
90  case MVT::v1i8:     return "MVT::v1i8";
91  case MVT::v2i8:     return "MVT::v2i8";
92  case MVT::v4i8:     return "MVT::v4i8";
93  case MVT::v8i8:     return "MVT::v8i8";
94  case MVT::v16i8:    return "MVT::v16i8";
95  case MVT::v32i8:    return "MVT::v32i8";
96  case MVT::v64i8:    return "MVT::v64i8";
97  case MVT::v128i8:   return "MVT::v128i8";
98  case MVT::v256i8:   return "MVT::v256i8";
99  case MVT::v1i16:    return "MVT::v1i16";
100  case MVT::v2i16:    return "MVT::v2i16";
101  case MVT::v3i16:    return "MVT::v3i16";
102  case MVT::v4i16:    return "MVT::v4i16";
103  case MVT::v8i16:    return "MVT::v8i16";
104  case MVT::v16i16:   return "MVT::v16i16";
105  case MVT::v32i16:   return "MVT::v32i16";
106  case MVT::v64i16:   return "MVT::v64i16";
107  case MVT::v128i16:  return "MVT::v128i16";
108  case MVT::v1i32:    return "MVT::v1i32";
109  case MVT::v2i32:    return "MVT::v2i32";
110  case MVT::v3i32:    return "MVT::v3i32";
111  case MVT::v4i32:    return "MVT::v4i32";
112  case MVT::v5i32:    return "MVT::v5i32";
113  case MVT::v8i32:    return "MVT::v8i32";
114  case MVT::v16i32:   return "MVT::v16i32";
115  case MVT::v32i32:   return "MVT::v32i32";
116  case MVT::v64i32:   return "MVT::v64i32";
117  case MVT::v128i32:  return "MVT::v128i32";
118  case MVT::v256i32:  return "MVT::v256i32";
119  case MVT::v512i32:  return "MVT::v512i32";
120  case MVT::v1024i32: return "MVT::v1024i32";
121  case MVT::v2048i32: return "MVT::v2048i32";
122  case MVT::v1i64:    return "MVT::v1i64";
123  case MVT::v2i64:    return "MVT::v2i64";
124  case MVT::v4i64:    return "MVT::v4i64";
125  case MVT::v8i64:    return "MVT::v8i64";
126  case MVT::v16i64:   return "MVT::v16i64";
127  case MVT::v32i64:   return "MVT::v32i64";
128  case MVT::v1i128:   return "MVT::v1i128";
129  case MVT::v2f16:    return "MVT::v2f16";
130  case MVT::v3f16:    return "MVT::v3f16";
131  case MVT::v4f16:    return "MVT::v4f16";
132  case MVT::v8f16:    return "MVT::v8f16";
133  case MVT::v16f16:   return "MVT::v16f16";
134  case MVT::v32f16:   return "MVT::v32f16";
135  case MVT::v1f32:    return "MVT::v1f32";
136  case MVT::v2f32:    return "MVT::v2f32";
137  case MVT::v3f32:    return "MVT::v3f32";
138  case MVT::v4f32:    return "MVT::v4f32";
139  case MVT::v5f32:    return "MVT::v5f32";
140  case MVT::v8f32:    return "MVT::v8f32";
141  case MVT::v16f32:   return "MVT::v16f32";
142  case MVT::v32f32:   return "MVT::v32f32";
143  case MVT::v64f32:   return "MVT::v64f32";
144  case MVT::v128f32:  return "MVT::v128f32";
145  case MVT::v256f32:  return "MVT::v256f32";
146  case MVT::v512f32:  return "MVT::v512f32";
147  case MVT::v1024f32: return "MVT::v1024f32";
148  case MVT::v2048f32: return "MVT::v2048f32";
149  case MVT::v1f64:    return "MVT::v1f64";
150  case MVT::v2f64:    return "MVT::v2f64";
151  case MVT::v4f64:    return "MVT::v4f64";
152  case MVT::v8f64:    return "MVT::v8f64";
153  case MVT::nxv1i1:   return "MVT::nxv1i1";
154  case MVT::nxv2i1:   return "MVT::nxv2i1";
155  case MVT::nxv4i1:   return "MVT::nxv4i1";
156  case MVT::nxv8i1:   return "MVT::nxv8i1";
157  case MVT::nxv16i1:  return "MVT::nxv16i1";
158  case MVT::nxv32i1:  return "MVT::nxv32i1";
159  case MVT::nxv1i8:   return "MVT::nxv1i8";
160  case MVT::nxv2i8:   return "MVT::nxv2i8";
161  case MVT::nxv4i8:   return "MVT::nxv4i8";
162  case MVT::nxv8i8:   return "MVT::nxv8i8";
163  case MVT::nxv16i8:  return "MVT::nxv16i8";
164  case MVT::nxv32i8:  return "MVT::nxv32i8";
165  case MVT::nxv1i16:  return "MVT::nxv1i16";
166  case MVT::nxv2i16:  return "MVT::nxv2i16";
167  case MVT::nxv4i16:  return "MVT::nxv4i16";
168  case MVT::nxv8i16:  return "MVT::nxv8i16";
169  case MVT::nxv16i16: return "MVT::nxv16i16";
170  case MVT::nxv32i16: return "MVT::nxv32i16";
171  case MVT::nxv1i32:  return "MVT::nxv1i32";
172  case MVT::nxv2i32:  return "MVT::nxv2i32";
173  case MVT::nxv4i32:  return "MVT::nxv4i32";
174  case MVT::nxv8i32:  return "MVT::nxv8i32";
175  case MVT::nxv16i32: return "MVT::nxv16i32";
176  case MVT::nxv1i64:  return "MVT::nxv1i64";
177  case MVT::nxv2i64:  return "MVT::nxv2i64";
178  case MVT::nxv4i64:  return "MVT::nxv4i64";
179  case MVT::nxv8i64:  return "MVT::nxv8i64";
180  case MVT::nxv16i64: return "MVT::nxv16i64";
181  case MVT::nxv2f16:  return "MVT::nxv2f16";
182  case MVT::nxv4f16:  return "MVT::nxv4f16";
183  case MVT::nxv8f16:  return "MVT::nxv8f16";
184  case MVT::nxv1f32:  return "MVT::nxv1f32";
185  case MVT::nxv2f32:  return "MVT::nxv2f32";
186  case MVT::nxv4f32:  return "MVT::nxv4f32";
187  case MVT::nxv8f32:  return "MVT::nxv8f32";
188  case MVT::nxv16f32: return "MVT::nxv16f32";
189  case MVT::nxv1f64:  return "MVT::nxv1f64";
190  case MVT::nxv2f64:  return "MVT::nxv2f64";
191  case MVT::nxv4f64:  return "MVT::nxv4f64";
192  case MVT::nxv8f64:  return "MVT::nxv8f64";
193  case MVT::token:    return "MVT::token";
194  case MVT::Metadata: return "MVT::Metadata";
195  case MVT::iPTR:     return "MVT::iPTR";
196  case MVT::iPTRAny:  return "MVT::iPTRAny";
197  case MVT::Untyped:  return "MVT::Untyped";
198  case MVT::exnref:   return "MVT::exnref";
199  default: llvm_unreachable("ILLEGAL VALUE TYPE!");
200  }
201}
202
203/// getQualifiedName - Return the name of the specified record, with a
204/// namespace qualifier if the record contains one.
205///
206std::string llvm::getQualifiedName(const Record *R) {
207  std::string Namespace;
208  if (R->getValue("Namespace"))
209     Namespace = R->getValueAsString("Namespace");
210  if (Namespace.empty()) return R->getName();
211  return Namespace + "::" + R->getName().str();
212}
213
214
215/// getTarget - Return the current instance of the Target class.
216///
217CodeGenTarget::CodeGenTarget(RecordKeeper &records)
218  : Records(records), CGH(records) {
219  std::vector<Record*> Targets = Records.getAllDerivedDefinitions("Target");
220  if (Targets.size() == 0)
221    PrintFatalError("ERROR: No 'Target' subclasses defined!");
222  if (Targets.size() != 1)
223    PrintFatalError("ERROR: Multiple subclasses of Target defined!");
224  TargetRec = Targets[0];
225}
226
227CodeGenTarget::~CodeGenTarget() {
228}
229
230const StringRef CodeGenTarget::getName() const {
231  return TargetRec->getName();
232}
233
234StringRef CodeGenTarget::getInstNamespace() const {
235  for (const CodeGenInstruction *Inst : getInstructionsByEnumValue()) {
236    // Make sure not to pick up "TargetOpcode" by accidentally getting
237    // the namespace off the PHI instruction or something.
238    if (Inst->Namespace != "TargetOpcode")
239      return Inst->Namespace;
240  }
241
242  return "";
243}
244
245Record *CodeGenTarget::getInstructionSet() const {
246  return TargetRec->getValueAsDef("InstructionSet");
247}
248
249bool CodeGenTarget::getAllowRegisterRenaming() const {
250  return TargetRec->getValueAsInt("AllowRegisterRenaming");
251}
252
253/// getAsmParser - Return the AssemblyParser definition for this target.
254///
255Record *CodeGenTarget::getAsmParser() const {
256  std::vector<Record*> LI = TargetRec->getValueAsListOfDefs("AssemblyParsers");
257  if (AsmParserNum >= LI.size())
258    PrintFatalError("Target does not have an AsmParser #" +
259                    Twine(AsmParserNum) + "!");
260  return LI[AsmParserNum];
261}
262
263/// getAsmParserVariant - Return the AssemblyParserVariant definition for
264/// this target.
265///
266Record *CodeGenTarget::getAsmParserVariant(unsigned i) const {
267  std::vector<Record*> LI =
268    TargetRec->getValueAsListOfDefs("AssemblyParserVariants");
269  if (i >= LI.size())
270    PrintFatalError("Target does not have an AsmParserVariant #" + Twine(i) +
271                    "!");
272  return LI[i];
273}
274
275/// getAsmParserVariantCount - Return the AssemblyParserVariant definition
276/// available for this target.
277///
278unsigned CodeGenTarget::getAsmParserVariantCount() const {
279  std::vector<Record*> LI =
280    TargetRec->getValueAsListOfDefs("AssemblyParserVariants");
281  return LI.size();
282}
283
284/// getAsmWriter - Return the AssemblyWriter definition for this target.
285///
286Record *CodeGenTarget::getAsmWriter() const {
287  std::vector<Record*> LI = TargetRec->getValueAsListOfDefs("AssemblyWriters");
288  if (AsmWriterNum >= LI.size())
289    PrintFatalError("Target does not have an AsmWriter #" +
290                    Twine(AsmWriterNum) + "!");
291  return LI[AsmWriterNum];
292}
293
294CodeGenRegBank &CodeGenTarget::getRegBank() const {
295  if (!RegBank)
296    RegBank = std::make_unique<CodeGenRegBank>(Records, getHwModes());
297  return *RegBank;
298}
299
300Optional<CodeGenRegisterClass *>
301CodeGenTarget::getSuperRegForSubReg(const ValueTypeByHwMode &ValueTy,
302                                    CodeGenRegBank &RegBank,
303                                    const CodeGenSubRegIndex *SubIdx) const {
304  std::vector<CodeGenRegisterClass *> Candidates;
305  auto &RegClasses = RegBank.getRegClasses();
306
307  // Try to find a register class which supports ValueTy, and also contains
308  // SubIdx.
309  for (CodeGenRegisterClass &RC : RegClasses) {
310    // Is there a subclass of this class which contains this subregister index?
311    CodeGenRegisterClass *SubClassWithSubReg = RC.getSubClassWithSubReg(SubIdx);
312    if (!SubClassWithSubReg)
313      continue;
314
315    // We have a class. Check if it supports this value type.
316    if (llvm::none_of(SubClassWithSubReg->VTs,
317                      [&ValueTy](const ValueTypeByHwMode &ClassVT) {
318                        return ClassVT == ValueTy;
319                      }))
320      continue;
321
322    // We have a register class which supports both the value type and
323    // subregister index. Remember it.
324    Candidates.push_back(SubClassWithSubReg);
325  }
326
327  // If we didn't find anything, we're done.
328  if (Candidates.empty())
329    return None;
330
331  // Find and return the largest of our candidate classes.
332  llvm::stable_sort(Candidates, [&](const CodeGenRegisterClass *A,
333                                    const CodeGenRegisterClass *B) {
334    if (A->getMembers().size() > B->getMembers().size())
335      return true;
336
337    if (A->getMembers().size() < B->getMembers().size())
338      return false;
339
340    // Order by name as a tie-breaker.
341    return StringRef(A->getName()) < B->getName();
342  });
343
344  return Candidates[0];
345}
346
347void CodeGenTarget::ReadRegAltNameIndices() const {
348  RegAltNameIndices = Records.getAllDerivedDefinitions("RegAltNameIndex");
349  llvm::sort(RegAltNameIndices, LessRecord());
350}
351
352/// getRegisterByName - If there is a register with the specific AsmName,
353/// return it.
354const CodeGenRegister *CodeGenTarget::getRegisterByName(StringRef Name) const {
355  const StringMap<CodeGenRegister*> &Regs = getRegBank().getRegistersByName();
356  StringMap<CodeGenRegister*>::const_iterator I = Regs.find(Name);
357  if (I == Regs.end())
358    return nullptr;
359  return I->second;
360}
361
362std::vector<ValueTypeByHwMode> CodeGenTarget::getRegisterVTs(Record *R)
363      const {
364  const CodeGenRegister *Reg = getRegBank().getReg(R);
365  std::vector<ValueTypeByHwMode> Result;
366  for (const auto &RC : getRegBank().getRegClasses()) {
367    if (RC.contains(Reg)) {
368      ArrayRef<ValueTypeByHwMode> InVTs = RC.getValueTypes();
369      Result.insert(Result.end(), InVTs.begin(), InVTs.end());
370    }
371  }
372
373  // Remove duplicates.
374  llvm::sort(Result);
375  Result.erase(std::unique(Result.begin(), Result.end()), Result.end());
376  return Result;
377}
378
379
380void CodeGenTarget::ReadLegalValueTypes() const {
381  for (const auto &RC : getRegBank().getRegClasses())
382    LegalValueTypes.insert(LegalValueTypes.end(), RC.VTs.begin(), RC.VTs.end());
383
384  // Remove duplicates.
385  llvm::sort(LegalValueTypes);
386  LegalValueTypes.erase(std::unique(LegalValueTypes.begin(),
387                                    LegalValueTypes.end()),
388                        LegalValueTypes.end());
389}
390
391CodeGenSchedModels &CodeGenTarget::getSchedModels() const {
392  if (!SchedModels)
393    SchedModels = std::make_unique<CodeGenSchedModels>(Records, *this);
394  return *SchedModels;
395}
396
397void CodeGenTarget::ReadInstructions() const {
398  NamedRegionTimer T("Read Instructions", "Time spent reading instructions",
399                     "CodeGenTarget", "CodeGenTarget", TimeRegions);
400  std::vector<Record*> Insts = Records.getAllDerivedDefinitions("Instruction");
401  if (Insts.size() <= 2)
402    PrintFatalError("No 'Instruction' subclasses defined!");
403
404  // Parse the instructions defined in the .td file.
405  for (unsigned i = 0, e = Insts.size(); i != e; ++i)
406    Instructions[Insts[i]] = std::make_unique<CodeGenInstruction>(Insts[i]);
407}
408
409static const CodeGenInstruction *
410GetInstByName(const char *Name,
411              const DenseMap<const Record*,
412                             std::unique_ptr<CodeGenInstruction>> &Insts,
413              RecordKeeper &Records) {
414  const Record *Rec = Records.getDef(Name);
415
416  const auto I = Insts.find(Rec);
417  if (!Rec || I == Insts.end())
418    PrintFatalError(Twine("Could not find '") + Name + "' instruction!");
419  return I->second.get();
420}
421
422static const char *const FixedInstrs[] = {
423#define HANDLE_TARGET_OPCODE(OPC) #OPC,
424#include "llvm/Support/TargetOpcodes.def"
425    nullptr};
426
427unsigned CodeGenTarget::getNumFixedInstructions() {
428  return array_lengthof(FixedInstrs) - 1;
429}
430
431/// Return all of the instructions defined by the target, ordered by
432/// their enum value.
433void CodeGenTarget::ComputeInstrsByEnum() const {
434  const auto &Insts = getInstructions();
435  for (const char *const *p = FixedInstrs; *p; ++p) {
436    const CodeGenInstruction *Instr = GetInstByName(*p, Insts, Records);
437    assert(Instr && "Missing target independent instruction");
438    assert(Instr->Namespace == "TargetOpcode" && "Bad namespace");
439    InstrsByEnum.push_back(Instr);
440  }
441  unsigned EndOfPredefines = InstrsByEnum.size();
442  assert(EndOfPredefines == getNumFixedInstructions() &&
443         "Missing generic opcode");
444
445  for (const auto &I : Insts) {
446    const CodeGenInstruction *CGI = I.second.get();
447    if (CGI->Namespace != "TargetOpcode") {
448      InstrsByEnum.push_back(CGI);
449      if (CGI->TheDef->getValueAsBit("isPseudo"))
450        ++NumPseudoInstructions;
451    }
452  }
453
454  assert(InstrsByEnum.size() == Insts.size() && "Missing predefined instr");
455
456  // All of the instructions are now in random order based on the map iteration.
457  llvm::sort(
458      InstrsByEnum.begin() + EndOfPredefines, InstrsByEnum.end(),
459      [](const CodeGenInstruction *Rec1, const CodeGenInstruction *Rec2) {
460        const auto &D1 = *Rec1->TheDef;
461        const auto &D2 = *Rec2->TheDef;
462        return std::make_tuple(!D1.getValueAsBit("isPseudo"), D1.getName()) <
463               std::make_tuple(!D2.getValueAsBit("isPseudo"), D2.getName());
464      });
465}
466
467
468/// isLittleEndianEncoding - Return whether this target encodes its instruction
469/// in little-endian format, i.e. bits laid out in the order [0..n]
470///
471bool CodeGenTarget::isLittleEndianEncoding() const {
472  return getInstructionSet()->getValueAsBit("isLittleEndianEncoding");
473}
474
475/// reverseBitsForLittleEndianEncoding - For little-endian instruction bit
476/// encodings, reverse the bit order of all instructions.
477void CodeGenTarget::reverseBitsForLittleEndianEncoding() {
478  if (!isLittleEndianEncoding())
479    return;
480
481  std::vector<Record *> Insts =
482      Records.getAllDerivedDefinitions("InstructionEncoding");
483  for (Record *R : Insts) {
484    if (R->getValueAsString("Namespace") == "TargetOpcode" ||
485        R->getValueAsBit("isPseudo"))
486      continue;
487
488    BitsInit *BI = R->getValueAsBitsInit("Inst");
489
490    unsigned numBits = BI->getNumBits();
491
492    SmallVector<Init *, 16> NewBits(numBits);
493
494    for (unsigned bit = 0, end = numBits / 2; bit != end; ++bit) {
495      unsigned bitSwapIdx = numBits - bit - 1;
496      Init *OrigBit = BI->getBit(bit);
497      Init *BitSwap = BI->getBit(bitSwapIdx);
498      NewBits[bit]        = BitSwap;
499      NewBits[bitSwapIdx] = OrigBit;
500    }
501    if (numBits % 2) {
502      unsigned middle = (numBits + 1) / 2;
503      NewBits[middle] = BI->getBit(middle);
504    }
505
506    BitsInit *NewBI = BitsInit::get(NewBits);
507
508    // Update the bits in reversed order so that emitInstrOpBits will get the
509    // correct endianness.
510    R->getValue("Inst")->setValue(NewBI);
511  }
512}
513
514/// guessInstructionProperties - Return true if it's OK to guess instruction
515/// properties instead of raising an error.
516///
517/// This is configurable as a temporary migration aid. It will eventually be
518/// permanently false.
519bool CodeGenTarget::guessInstructionProperties() const {
520  return getInstructionSet()->getValueAsBit("guessInstructionProperties");
521}
522
523//===----------------------------------------------------------------------===//
524// ComplexPattern implementation
525//
526ComplexPattern::ComplexPattern(Record *R) {
527  Ty          = ::getValueType(R->getValueAsDef("Ty"));
528  NumOperands = R->getValueAsInt("NumOperands");
529  SelectFunc  = R->getValueAsString("SelectFunc");
530  RootNodes   = R->getValueAsListOfDefs("RootNodes");
531
532  // FIXME: This is a hack to statically increase the priority of patterns which
533  // maps a sub-dag to a complex pattern. e.g. favors LEA over ADD. To get best
534  // possible pattern match we'll need to dynamically calculate the complexity
535  // of all patterns a dag can potentially map to.
536  int64_t RawComplexity = R->getValueAsInt("Complexity");
537  if (RawComplexity == -1)
538    Complexity = NumOperands * 3;
539  else
540    Complexity = RawComplexity;
541
542  // FIXME: Why is this different from parseSDPatternOperatorProperties?
543  // Parse the properties.
544  Properties = 0;
545  std::vector<Record*> PropList = R->getValueAsListOfDefs("Properties");
546  for (unsigned i = 0, e = PropList.size(); i != e; ++i)
547    if (PropList[i]->getName() == "SDNPHasChain") {
548      Properties |= 1 << SDNPHasChain;
549    } else if (PropList[i]->getName() == "SDNPOptInGlue") {
550      Properties |= 1 << SDNPOptInGlue;
551    } else if (PropList[i]->getName() == "SDNPMayStore") {
552      Properties |= 1 << SDNPMayStore;
553    } else if (PropList[i]->getName() == "SDNPMayLoad") {
554      Properties |= 1 << SDNPMayLoad;
555    } else if (PropList[i]->getName() == "SDNPSideEffect") {
556      Properties |= 1 << SDNPSideEffect;
557    } else if (PropList[i]->getName() == "SDNPMemOperand") {
558      Properties |= 1 << SDNPMemOperand;
559    } else if (PropList[i]->getName() == "SDNPVariadic") {
560      Properties |= 1 << SDNPVariadic;
561    } else if (PropList[i]->getName() == "SDNPWantRoot") {
562      Properties |= 1 << SDNPWantRoot;
563    } else if (PropList[i]->getName() == "SDNPWantParent") {
564      Properties |= 1 << SDNPWantParent;
565    } else {
566      PrintFatalError(R->getLoc(), "Unsupported SD Node property '" +
567                                       PropList[i]->getName() +
568                                       "' on ComplexPattern '" + R->getName() +
569                                       "'!");
570    }
571}
572
573//===----------------------------------------------------------------------===//
574// CodeGenIntrinsic Implementation
575//===----------------------------------------------------------------------===//
576
577CodeGenIntrinsicTable::CodeGenIntrinsicTable(const RecordKeeper &RC) {
578  std::vector<Record*> Defs = RC.getAllDerivedDefinitions("Intrinsic");
579
580  Intrinsics.reserve(Defs.size());
581
582  for (unsigned I = 0, e = Defs.size(); I != e; ++I)
583    Intrinsics.push_back(CodeGenIntrinsic(Defs[I]));
584
585  llvm::sort(Intrinsics,
586             [](const CodeGenIntrinsic &LHS, const CodeGenIntrinsic &RHS) {
587               return std::tie(LHS.TargetPrefix, LHS.Name) <
588                      std::tie(RHS.TargetPrefix, RHS.Name);
589             });
590  Targets.push_back({"", 0, 0});
591  for (size_t I = 0, E = Intrinsics.size(); I < E; ++I)
592    if (Intrinsics[I].TargetPrefix != Targets.back().Name) {
593      Targets.back().Count = I - Targets.back().Offset;
594      Targets.push_back({Intrinsics[I].TargetPrefix, I, 0});
595    }
596  Targets.back().Count = Intrinsics.size() - Targets.back().Offset;
597}
598
599CodeGenIntrinsic::CodeGenIntrinsic(Record *R) {
600  TheDef = R;
601  std::string DefName = R->getName();
602  ArrayRef<SMLoc> DefLoc = R->getLoc();
603  ModRef = ReadWriteMem;
604  Properties = 0;
605  isOverloaded = false;
606  isCommutative = false;
607  canThrow = false;
608  isNoReturn = false;
609  isWillReturn = false;
610  isCold = false;
611  isNoDuplicate = false;
612  isConvergent = false;
613  isSpeculatable = false;
614  hasSideEffects = false;
615
616  if (DefName.size() <= 4 ||
617      std::string(DefName.begin(), DefName.begin() + 4) != "int_")
618    PrintFatalError(DefLoc,
619                    "Intrinsic '" + DefName + "' does not start with 'int_'!");
620
621  EnumName = std::string(DefName.begin()+4, DefName.end());
622
623  if (R->getValue("GCCBuiltinName"))  // Ignore a missing GCCBuiltinName field.
624    GCCBuiltinName = R->getValueAsString("GCCBuiltinName");
625  if (R->getValue("MSBuiltinName"))   // Ignore a missing MSBuiltinName field.
626    MSBuiltinName = R->getValueAsString("MSBuiltinName");
627
628  TargetPrefix = R->getValueAsString("TargetPrefix");
629  Name = R->getValueAsString("LLVMName");
630
631  if (Name == "") {
632    // If an explicit name isn't specified, derive one from the DefName.
633    Name = "llvm.";
634
635    for (unsigned i = 0, e = EnumName.size(); i != e; ++i)
636      Name += (EnumName[i] == '_') ? '.' : EnumName[i];
637  } else {
638    // Verify it starts with "llvm.".
639    if (Name.size() <= 5 ||
640        std::string(Name.begin(), Name.begin() + 5) != "llvm.")
641      PrintFatalError(DefLoc, "Intrinsic '" + DefName +
642                                  "'s name does not start with 'llvm.'!");
643  }
644
645  // If TargetPrefix is specified, make sure that Name starts with
646  // "llvm.<targetprefix>.".
647  if (!TargetPrefix.empty()) {
648    if (Name.size() < 6+TargetPrefix.size() ||
649        std::string(Name.begin() + 5, Name.begin() + 6 + TargetPrefix.size())
650        != (TargetPrefix + "."))
651      PrintFatalError(DefLoc, "Intrinsic '" + DefName +
652                                  "' does not start with 'llvm." +
653                                  TargetPrefix + ".'!");
654  }
655
656  ListInit *RetTypes = R->getValueAsListInit("RetTypes");
657  ListInit *ParamTypes = R->getValueAsListInit("ParamTypes");
658
659  // First collate a list of overloaded types.
660  std::vector<MVT::SimpleValueType> OverloadedVTs;
661  for (ListInit *TypeList : {RetTypes, ParamTypes}) {
662    for (unsigned i = 0, e = TypeList->size(); i != e; ++i) {
663      Record *TyEl = TypeList->getElementAsRecord(i);
664      assert(TyEl->isSubClassOf("LLVMType") && "Expected a type!");
665
666      if (TyEl->isSubClassOf("LLVMMatchType"))
667        continue;
668
669      MVT::SimpleValueType VT = getValueType(TyEl->getValueAsDef("VT"));
670      if (MVT(VT).isOverloaded()) {
671        OverloadedVTs.push_back(VT);
672        isOverloaded = true;
673      }
674    }
675  }
676
677  // Parse the list of return types.
678  ListInit *TypeList = RetTypes;
679  for (unsigned i = 0, e = TypeList->size(); i != e; ++i) {
680    Record *TyEl = TypeList->getElementAsRecord(i);
681    assert(TyEl->isSubClassOf("LLVMType") && "Expected a type!");
682    MVT::SimpleValueType VT;
683    if (TyEl->isSubClassOf("LLVMMatchType")) {
684      unsigned MatchTy = TyEl->getValueAsInt("Number");
685      assert(MatchTy < OverloadedVTs.size() &&
686             "Invalid matching number!");
687      VT = OverloadedVTs[MatchTy];
688      // It only makes sense to use the extended and truncated vector element
689      // variants with iAny types; otherwise, if the intrinsic is not
690      // overloaded, all the types can be specified directly.
691      assert(((!TyEl->isSubClassOf("LLVMExtendedType") &&
692               !TyEl->isSubClassOf("LLVMTruncatedType")) ||
693              VT == MVT::iAny || VT == MVT::vAny) &&
694             "Expected iAny or vAny type");
695    } else {
696      VT = getValueType(TyEl->getValueAsDef("VT"));
697    }
698
699    // Reject invalid types.
700    if (VT == MVT::isVoid)
701      PrintFatalError(DefLoc, "Intrinsic '" + DefName +
702                                  " has void in result type list!");
703
704    IS.RetVTs.push_back(VT);
705    IS.RetTypeDefs.push_back(TyEl);
706  }
707
708  // Parse the list of parameter types.
709  TypeList = ParamTypes;
710  for (unsigned i = 0, e = TypeList->size(); i != e; ++i) {
711    Record *TyEl = TypeList->getElementAsRecord(i);
712    assert(TyEl->isSubClassOf("LLVMType") && "Expected a type!");
713    MVT::SimpleValueType VT;
714    if (TyEl->isSubClassOf("LLVMMatchType")) {
715      unsigned MatchTy = TyEl->getValueAsInt("Number");
716      if (MatchTy >= OverloadedVTs.size()) {
717        PrintError(R->getLoc(),
718                   "Parameter #" + Twine(i) + " has out of bounds matching "
719                   "number " + Twine(MatchTy));
720        PrintFatalError(DefLoc,
721                        Twine("ParamTypes is ") + TypeList->getAsString());
722      }
723      VT = OverloadedVTs[MatchTy];
724      // It only makes sense to use the extended and truncated vector element
725      // variants with iAny types; otherwise, if the intrinsic is not
726      // overloaded, all the types can be specified directly.
727      assert(((!TyEl->isSubClassOf("LLVMExtendedType") &&
728               !TyEl->isSubClassOf("LLVMTruncatedType") &&
729               !TyEl->isSubClassOf("LLVMScalarOrSameVectorWidth")) ||
730              VT == MVT::iAny || VT == MVT::vAny) &&
731             "Expected iAny or vAny type");
732    } else
733      VT = getValueType(TyEl->getValueAsDef("VT"));
734
735    // Reject invalid types.
736    if (VT == MVT::isVoid && i != e-1 /*void at end means varargs*/)
737      PrintFatalError(DefLoc, "Intrinsic '" + DefName +
738                                  " has void in result type list!");
739
740    IS.ParamVTs.push_back(VT);
741    IS.ParamTypeDefs.push_back(TyEl);
742  }
743
744  // Parse the intrinsic properties.
745  ListInit *PropList = R->getValueAsListInit("IntrProperties");
746  for (unsigned i = 0, e = PropList->size(); i != e; ++i) {
747    Record *Property = PropList->getElementAsRecord(i);
748    assert(Property->isSubClassOf("IntrinsicProperty") &&
749           "Expected a property!");
750
751    if (Property->getName() == "IntrNoMem")
752      ModRef = NoMem;
753    else if (Property->getName() == "IntrReadMem")
754      ModRef = ModRefBehavior(ModRef & ~MR_Mod);
755    else if (Property->getName() == "IntrWriteMem")
756      ModRef = ModRefBehavior(ModRef & ~MR_Ref);
757    else if (Property->getName() == "IntrArgMemOnly")
758      ModRef = ModRefBehavior((ModRef & ~MR_Anywhere) | MR_ArgMem);
759    else if (Property->getName() == "IntrInaccessibleMemOnly")
760      ModRef = ModRefBehavior((ModRef & ~MR_Anywhere) | MR_InaccessibleMem);
761    else if (Property->getName() == "IntrInaccessibleMemOrArgMemOnly")
762      ModRef = ModRefBehavior((ModRef & ~MR_Anywhere) | MR_ArgMem |
763                              MR_InaccessibleMem);
764    else if (Property->getName() == "Commutative")
765      isCommutative = true;
766    else if (Property->getName() == "Throws")
767      canThrow = true;
768    else if (Property->getName() == "IntrNoDuplicate")
769      isNoDuplicate = true;
770    else if (Property->getName() == "IntrConvergent")
771      isConvergent = true;
772    else if (Property->getName() == "IntrNoReturn")
773      isNoReturn = true;
774    else if (Property->getName() == "IntrWillReturn")
775      isWillReturn = true;
776    else if (Property->getName() == "IntrCold")
777      isCold = true;
778    else if (Property->getName() == "IntrSpeculatable")
779      isSpeculatable = true;
780    else if (Property->getName() == "IntrHasSideEffects")
781      hasSideEffects = true;
782    else if (Property->isSubClassOf("NoCapture")) {
783      unsigned ArgNo = Property->getValueAsInt("ArgNo");
784      ArgumentAttributes.push_back(std::make_pair(ArgNo, NoCapture));
785    } else if (Property->isSubClassOf("NoAlias")) {
786      unsigned ArgNo = Property->getValueAsInt("ArgNo");
787      ArgumentAttributes.push_back(std::make_pair(ArgNo, NoAlias));
788    } else if (Property->isSubClassOf("Returned")) {
789      unsigned ArgNo = Property->getValueAsInt("ArgNo");
790      ArgumentAttributes.push_back(std::make_pair(ArgNo, Returned));
791    } else if (Property->isSubClassOf("ReadOnly")) {
792      unsigned ArgNo = Property->getValueAsInt("ArgNo");
793      ArgumentAttributes.push_back(std::make_pair(ArgNo, ReadOnly));
794    } else if (Property->isSubClassOf("WriteOnly")) {
795      unsigned ArgNo = Property->getValueAsInt("ArgNo");
796      ArgumentAttributes.push_back(std::make_pair(ArgNo, WriteOnly));
797    } else if (Property->isSubClassOf("ReadNone")) {
798      unsigned ArgNo = Property->getValueAsInt("ArgNo");
799      ArgumentAttributes.push_back(std::make_pair(ArgNo, ReadNone));
800    } else if (Property->isSubClassOf("ImmArg")) {
801      unsigned ArgNo = Property->getValueAsInt("ArgNo");
802      ArgumentAttributes.push_back(std::make_pair(ArgNo, ImmArg));
803    } else
804      llvm_unreachable("Unknown property!");
805  }
806
807  // Also record the SDPatternOperator Properties.
808  Properties = parseSDPatternOperatorProperties(R);
809
810  // Sort the argument attributes for later benefit.
811  llvm::sort(ArgumentAttributes);
812}
813
814bool CodeGenIntrinsic::isParamAPointer(unsigned ParamIdx) const {
815  if (ParamIdx >= IS.ParamVTs.size())
816    return false;
817  MVT ParamType = MVT(IS.ParamVTs[ParamIdx]);
818  return ParamType == MVT::iPTR || ParamType == MVT::iPTRAny;
819}
820
821bool CodeGenIntrinsic::isParamImmArg(unsigned ParamIdx) const {
822  std::pair<unsigned, ArgAttribute> Val = {ParamIdx, ImmArg};
823  return std::binary_search(ArgumentAttributes.begin(),
824                            ArgumentAttributes.end(), Val);
825}
826