CodeGenRegisters.h revision 360784
1//===- CodeGenRegisters.h - Register and RegisterClass Info -----*- C++ -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines structures to encapsulate information gleaned from the 10// target register and register class definitions. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef LLVM_UTILS_TABLEGEN_CODEGENREGISTERS_H 15#define LLVM_UTILS_TABLEGEN_CODEGENREGISTERS_H 16 17#include "InfoByHwMode.h" 18#include "llvm/ADT/ArrayRef.h" 19#include "llvm/ADT/BitVector.h" 20#include "llvm/ADT/DenseMap.h" 21#include "llvm/ADT/STLExtras.h" 22#include "llvm/ADT/SetVector.h" 23#include "llvm/ADT/SmallPtrSet.h" 24#include "llvm/ADT/SmallVector.h" 25#include "llvm/ADT/SparseBitVector.h" 26#include "llvm/ADT/StringMap.h" 27#include "llvm/ADT/StringRef.h" 28#include "llvm/MC/LaneBitmask.h" 29#include "llvm/Support/ErrorHandling.h" 30#include "llvm/Support/MachineValueType.h" 31#include "llvm/TableGen/Record.h" 32#include "llvm/TableGen/SetTheory.h" 33#include <cassert> 34#include <cstdint> 35#include <deque> 36#include <list> 37#include <map> 38#include <string> 39#include <utility> 40#include <vector> 41 42namespace llvm { 43 44 class CodeGenRegBank; 45 template <typename T, typename Vector, typename Set> class SetVector; 46 47 /// Used to encode a step in a register lane mask transformation. 48 /// Mask the bits specified in Mask, then rotate them Rol bits to the left 49 /// assuming a wraparound at 32bits. 50 struct MaskRolPair { 51 LaneBitmask Mask; 52 uint8_t RotateLeft; 53 54 bool operator==(const MaskRolPair Other) const { 55 return Mask == Other.Mask && RotateLeft == Other.RotateLeft; 56 } 57 bool operator!=(const MaskRolPair Other) const { 58 return Mask != Other.Mask || RotateLeft != Other.RotateLeft; 59 } 60 }; 61 62 /// CodeGenSubRegIndex - Represents a sub-register index. 63 class CodeGenSubRegIndex { 64 Record *const TheDef; 65 std::string Name; 66 std::string Namespace; 67 68 public: 69 uint16_t Size; 70 uint16_t Offset; 71 const unsigned EnumValue; 72 mutable LaneBitmask LaneMask; 73 mutable SmallVector<MaskRolPair,1> CompositionLaneMaskTransform; 74 75 /// A list of subregister indexes concatenated resulting in this 76 /// subregister index. This is the reverse of CodeGenRegBank::ConcatIdx. 77 SmallVector<CodeGenSubRegIndex*,4> ConcatenationOf; 78 79 // Are all super-registers containing this SubRegIndex covered by their 80 // sub-registers? 81 bool AllSuperRegsCovered; 82 // A subregister index is "artificial" if every subregister obtained 83 // from applying this index is artificial. Artificial subregister 84 // indexes are not used to create new register classes. 85 bool Artificial; 86 87 CodeGenSubRegIndex(Record *R, unsigned Enum); 88 CodeGenSubRegIndex(StringRef N, StringRef Nspace, unsigned Enum); 89 90 const std::string &getName() const { return Name; } 91 const std::string &getNamespace() const { return Namespace; } 92 std::string getQualifiedName() const; 93 94 // Map of composite subreg indices. 95 typedef std::map<CodeGenSubRegIndex *, CodeGenSubRegIndex *, 96 deref<std::less<>>> 97 CompMap; 98 99 // Returns the subreg index that results from composing this with Idx. 100 // Returns NULL if this and Idx don't compose. 101 CodeGenSubRegIndex *compose(CodeGenSubRegIndex *Idx) const { 102 CompMap::const_iterator I = Composed.find(Idx); 103 return I == Composed.end() ? nullptr : I->second; 104 } 105 106 // Add a composite subreg index: this+A = B. 107 // Return a conflicting composite, or NULL 108 CodeGenSubRegIndex *addComposite(CodeGenSubRegIndex *A, 109 CodeGenSubRegIndex *B) { 110 assert(A && B); 111 std::pair<CompMap::iterator, bool> Ins = 112 Composed.insert(std::make_pair(A, B)); 113 // Synthetic subreg indices that aren't contiguous (for instance ARM 114 // register tuples) don't have a bit range, so it's OK to let 115 // B->Offset == -1. For the other cases, accumulate the offset and set 116 // the size here. Only do so if there is no offset yet though. 117 if ((Offset != (uint16_t)-1 && A->Offset != (uint16_t)-1) && 118 (B->Offset == (uint16_t)-1)) { 119 B->Offset = Offset + A->Offset; 120 B->Size = A->Size; 121 } 122 return (Ins.second || Ins.first->second == B) ? nullptr 123 : Ins.first->second; 124 } 125 126 // Update the composite maps of components specified in 'ComposedOf'. 127 void updateComponents(CodeGenRegBank&); 128 129 // Return the map of composites. 130 const CompMap &getComposites() const { return Composed; } 131 132 // Compute LaneMask from Composed. Return LaneMask. 133 LaneBitmask computeLaneMask() const; 134 135 void setConcatenationOf(ArrayRef<CodeGenSubRegIndex*> Parts); 136 137 /// Replaces subregister indexes in the `ConcatenationOf` list with 138 /// list of subregisters they are composed of (if any). Do this recursively. 139 void computeConcatTransitiveClosure(); 140 141 bool operator<(const CodeGenSubRegIndex &RHS) const { 142 return this->EnumValue < RHS.EnumValue; 143 } 144 145 private: 146 CompMap Composed; 147 }; 148 149 /// CodeGenRegister - Represents a register definition. 150 struct CodeGenRegister { 151 Record *TheDef; 152 unsigned EnumValue; 153 unsigned CostPerUse; 154 bool CoveredBySubRegs; 155 bool HasDisjunctSubRegs; 156 bool Artificial; 157 158 // Map SubRegIndex -> Register. 159 typedef std::map<CodeGenSubRegIndex *, CodeGenRegister *, 160 deref<std::less<>>> 161 SubRegMap; 162 163 CodeGenRegister(Record *R, unsigned Enum); 164 165 const StringRef getName() const; 166 167 // Extract more information from TheDef. This is used to build an object 168 // graph after all CodeGenRegister objects have been created. 169 void buildObjectGraph(CodeGenRegBank&); 170 171 // Lazily compute a map of all sub-registers. 172 // This includes unique entries for all sub-sub-registers. 173 const SubRegMap &computeSubRegs(CodeGenRegBank&); 174 175 // Compute extra sub-registers by combining the existing sub-registers. 176 void computeSecondarySubRegs(CodeGenRegBank&); 177 178 // Add this as a super-register to all sub-registers after the sub-register 179 // graph has been built. 180 void computeSuperRegs(CodeGenRegBank&); 181 182 const SubRegMap &getSubRegs() const { 183 assert(SubRegsComplete && "Must precompute sub-registers"); 184 return SubRegs; 185 } 186 187 // Add sub-registers to OSet following a pre-order defined by the .td file. 188 void addSubRegsPreOrder(SetVector<const CodeGenRegister*> &OSet, 189 CodeGenRegBank&) const; 190 191 // Return the sub-register index naming Reg as a sub-register of this 192 // register. Returns NULL if Reg is not a sub-register. 193 CodeGenSubRegIndex *getSubRegIndex(const CodeGenRegister *Reg) const { 194 return SubReg2Idx.lookup(Reg); 195 } 196 197 typedef std::vector<const CodeGenRegister*> SuperRegList; 198 199 // Get the list of super-registers in topological order, small to large. 200 // This is valid after computeSubRegs visits all registers during RegBank 201 // construction. 202 const SuperRegList &getSuperRegs() const { 203 assert(SubRegsComplete && "Must precompute sub-registers"); 204 return SuperRegs; 205 } 206 207 // Get the list of ad hoc aliases. The graph is symmetric, so the list 208 // contains all registers in 'Aliases', and all registers that mention this 209 // register in 'Aliases'. 210 ArrayRef<CodeGenRegister*> getExplicitAliases() const { 211 return ExplicitAliases; 212 } 213 214 // Get the topological signature of this register. This is a small integer 215 // less than RegBank.getNumTopoSigs(). Registers with the same TopoSig have 216 // identical sub-register structure. That is, they support the same set of 217 // sub-register indices mapping to the same kind of sub-registers 218 // (TopoSig-wise). 219 unsigned getTopoSig() const { 220 assert(SuperRegsComplete && "TopoSigs haven't been computed yet."); 221 return TopoSig; 222 } 223 224 // List of register units in ascending order. 225 typedef SparseBitVector<> RegUnitList; 226 typedef SmallVector<LaneBitmask, 16> RegUnitLaneMaskList; 227 228 // How many entries in RegUnitList are native? 229 RegUnitList NativeRegUnits; 230 231 // Get the list of register units. 232 // This is only valid after computeSubRegs() completes. 233 const RegUnitList &getRegUnits() const { return RegUnits; } 234 235 ArrayRef<LaneBitmask> getRegUnitLaneMasks() const { 236 return makeArrayRef(RegUnitLaneMasks).slice(0, NativeRegUnits.count()); 237 } 238 239 // Get the native register units. This is a prefix of getRegUnits(). 240 RegUnitList getNativeRegUnits() const { 241 return NativeRegUnits; 242 } 243 244 void setRegUnitLaneMasks(const RegUnitLaneMaskList &LaneMasks) { 245 RegUnitLaneMasks = LaneMasks; 246 } 247 248 // Inherit register units from subregisters. 249 // Return true if the RegUnits changed. 250 bool inheritRegUnits(CodeGenRegBank &RegBank); 251 252 // Adopt a register unit for pressure tracking. 253 // A unit is adopted iff its unit number is >= NativeRegUnits.count(). 254 void adoptRegUnit(unsigned RUID) { RegUnits.set(RUID); } 255 256 // Get the sum of this register's register unit weights. 257 unsigned getWeight(const CodeGenRegBank &RegBank) const; 258 259 // Canonically ordered set. 260 typedef std::vector<const CodeGenRegister*> Vec; 261 262 private: 263 bool SubRegsComplete; 264 bool SuperRegsComplete; 265 unsigned TopoSig; 266 267 // The sub-registers explicit in the .td file form a tree. 268 SmallVector<CodeGenSubRegIndex*, 8> ExplicitSubRegIndices; 269 SmallVector<CodeGenRegister*, 8> ExplicitSubRegs; 270 271 // Explicit ad hoc aliases, symmetrized to form an undirected graph. 272 SmallVector<CodeGenRegister*, 8> ExplicitAliases; 273 274 // Super-registers where this is the first explicit sub-register. 275 SuperRegList LeadingSuperRegs; 276 277 SubRegMap SubRegs; 278 SuperRegList SuperRegs; 279 DenseMap<const CodeGenRegister*, CodeGenSubRegIndex*> SubReg2Idx; 280 RegUnitList RegUnits; 281 RegUnitLaneMaskList RegUnitLaneMasks; 282 }; 283 284 inline bool operator<(const CodeGenRegister &A, const CodeGenRegister &B) { 285 return A.EnumValue < B.EnumValue; 286 } 287 288 inline bool operator==(const CodeGenRegister &A, const CodeGenRegister &B) { 289 return A.EnumValue == B.EnumValue; 290 } 291 292 class CodeGenRegisterClass { 293 CodeGenRegister::Vec Members; 294 // Allocation orders. Order[0] always contains all registers in Members. 295 std::vector<SmallVector<Record*, 16>> Orders; 296 // Bit mask of sub-classes including this, indexed by their EnumValue. 297 BitVector SubClasses; 298 // List of super-classes, topologocally ordered to have the larger classes 299 // first. This is the same as sorting by EnumValue. 300 SmallVector<CodeGenRegisterClass*, 4> SuperClasses; 301 Record *TheDef; 302 std::string Name; 303 304 // For a synthesized class, inherit missing properties from the nearest 305 // super-class. 306 void inheritProperties(CodeGenRegBank&); 307 308 // Map SubRegIndex -> sub-class. This is the largest sub-class where all 309 // registers have a SubRegIndex sub-register. 310 DenseMap<const CodeGenSubRegIndex *, CodeGenRegisterClass *> 311 SubClassWithSubReg; 312 313 // Map SubRegIndex -> set of super-reg classes. This is all register 314 // classes SuperRC such that: 315 // 316 // R:SubRegIndex in this RC for all R in SuperRC. 317 // 318 DenseMap<const CodeGenSubRegIndex *, SmallPtrSet<CodeGenRegisterClass *, 8>> 319 SuperRegClasses; 320 321 // Bit vector of TopoSigs for the registers in this class. This will be 322 // very sparse on regular architectures. 323 BitVector TopoSigs; 324 325 public: 326 unsigned EnumValue; 327 StringRef Namespace; 328 SmallVector<ValueTypeByHwMode, 4> VTs; 329 RegSizeInfoByHwMode RSI; 330 int CopyCost; 331 bool Allocatable; 332 StringRef AltOrderSelect; 333 uint8_t AllocationPriority; 334 /// Contains the combination of the lane masks of all subregisters. 335 LaneBitmask LaneMask; 336 /// True if there are at least 2 subregisters which do not interfere. 337 bool HasDisjunctSubRegs; 338 bool CoveredBySubRegs; 339 /// A register class is artificial if all its members are artificial. 340 bool Artificial; 341 342 // Return the Record that defined this class, or NULL if the class was 343 // created by TableGen. 344 Record *getDef() const { return TheDef; } 345 346 const std::string &getName() const { return Name; } 347 std::string getQualifiedName() const; 348 ArrayRef<ValueTypeByHwMode> getValueTypes() const { return VTs; } 349 unsigned getNumValueTypes() const { return VTs.size(); } 350 351 bool hasType(const ValueTypeByHwMode &VT) const { 352 return std::find(VTs.begin(), VTs.end(), VT) != VTs.end(); 353 } 354 355 const ValueTypeByHwMode &getValueTypeNum(unsigned VTNum) const { 356 if (VTNum < VTs.size()) 357 return VTs[VTNum]; 358 llvm_unreachable("VTNum greater than number of ValueTypes in RegClass!"); 359 } 360 361 // Return true if this this class contains the register. 362 bool contains(const CodeGenRegister*) const; 363 364 // Returns true if RC is a subclass. 365 // RC is a sub-class of this class if it is a valid replacement for any 366 // instruction operand where a register of this classis required. It must 367 // satisfy these conditions: 368 // 369 // 1. All RC registers are also in this. 370 // 2. The RC spill size must not be smaller than our spill size. 371 // 3. RC spill alignment must be compatible with ours. 372 // 373 bool hasSubClass(const CodeGenRegisterClass *RC) const { 374 return SubClasses.test(RC->EnumValue); 375 } 376 377 // getSubClassWithSubReg - Returns the largest sub-class where all 378 // registers have a SubIdx sub-register. 379 CodeGenRegisterClass * 380 getSubClassWithSubReg(const CodeGenSubRegIndex *SubIdx) const { 381 return SubClassWithSubReg.lookup(SubIdx); 382 } 383 384 /// Find largest subclass where all registers have SubIdx subregisters in 385 /// SubRegClass and the largest subregister class that contains those 386 /// subregisters without (as far as possible) also containing additional registers. 387 /// 388 /// This can be used to find a suitable pair of classes for subregister copies. 389 /// \return std::pair<SubClass, SubRegClass> where SubClass is a SubClass is 390 /// a class where every register has SubIdx and SubRegClass is a class where 391 /// every register is covered by the SubIdx subregister of SubClass. 392 Optional<std::pair<CodeGenRegisterClass *, CodeGenRegisterClass *>> 393 getMatchingSubClassWithSubRegs(CodeGenRegBank &RegBank, 394 const CodeGenSubRegIndex *SubIdx) const; 395 396 void setSubClassWithSubReg(const CodeGenSubRegIndex *SubIdx, 397 CodeGenRegisterClass *SubRC) { 398 SubClassWithSubReg[SubIdx] = SubRC; 399 } 400 401 // getSuperRegClasses - Returns a bit vector of all register classes 402 // containing only SubIdx super-registers of this class. 403 void getSuperRegClasses(const CodeGenSubRegIndex *SubIdx, 404 BitVector &Out) const; 405 406 // addSuperRegClass - Add a class containing only SubIdx super-registers. 407 void addSuperRegClass(CodeGenSubRegIndex *SubIdx, 408 CodeGenRegisterClass *SuperRC) { 409 SuperRegClasses[SubIdx].insert(SuperRC); 410 } 411 412 // getSubClasses - Returns a constant BitVector of subclasses indexed by 413 // EnumValue. 414 // The SubClasses vector includes an entry for this class. 415 const BitVector &getSubClasses() const { return SubClasses; } 416 417 // getSuperClasses - Returns a list of super classes ordered by EnumValue. 418 // The array does not include an entry for this class. 419 ArrayRef<CodeGenRegisterClass*> getSuperClasses() const { 420 return SuperClasses; 421 } 422 423 // Returns an ordered list of class members. 424 // The order of registers is the same as in the .td file. 425 // No = 0 is the default allocation order, No = 1 is the first alternative. 426 ArrayRef<Record*> getOrder(unsigned No = 0) const { 427 return Orders[No]; 428 } 429 430 // Return the total number of allocation orders available. 431 unsigned getNumOrders() const { return Orders.size(); } 432 433 // Get the set of registers. This set contains the same registers as 434 // getOrder(0). 435 const CodeGenRegister::Vec &getMembers() const { return Members; } 436 437 // Get a bit vector of TopoSigs present in this register class. 438 const BitVector &getTopoSigs() const { return TopoSigs; } 439 440 // Populate a unique sorted list of units from a register set. 441 void buildRegUnitSet(const CodeGenRegBank &RegBank, 442 std::vector<unsigned> &RegUnits) const; 443 444 CodeGenRegisterClass(CodeGenRegBank&, Record *R); 445 446 // A key representing the parts of a register class used for forming 447 // sub-classes. Note the ordering provided by this key is not the same as 448 // the topological order used for the EnumValues. 449 struct Key { 450 const CodeGenRegister::Vec *Members; 451 RegSizeInfoByHwMode RSI; 452 453 Key(const CodeGenRegister::Vec *M, const RegSizeInfoByHwMode &I) 454 : Members(M), RSI(I) {} 455 456 Key(const CodeGenRegisterClass &RC) 457 : Members(&RC.getMembers()), RSI(RC.RSI) {} 458 459 // Lexicographical order of (Members, RegSizeInfoByHwMode). 460 bool operator<(const Key&) const; 461 }; 462 463 // Create a non-user defined register class. 464 CodeGenRegisterClass(CodeGenRegBank&, StringRef Name, Key Props); 465 466 // Called by CodeGenRegBank::CodeGenRegBank(). 467 static void computeSubClasses(CodeGenRegBank&); 468 }; 469 470 // Register units are used to model interference and register pressure. 471 // Every register is assigned one or more register units such that two 472 // registers overlap if and only if they have a register unit in common. 473 // 474 // Normally, one register unit is created per leaf register. Non-leaf 475 // registers inherit the units of their sub-registers. 476 struct RegUnit { 477 // Weight assigned to this RegUnit for estimating register pressure. 478 // This is useful when equalizing weights in register classes with mixed 479 // register topologies. 480 unsigned Weight; 481 482 // Each native RegUnit corresponds to one or two root registers. The full 483 // set of registers containing this unit can be computed as the union of 484 // these two registers and their super-registers. 485 const CodeGenRegister *Roots[2]; 486 487 // Index into RegClassUnitSets where we can find the list of UnitSets that 488 // contain this unit. 489 unsigned RegClassUnitSetsIdx; 490 // A register unit is artificial if at least one of its roots is 491 // artificial. 492 bool Artificial; 493 494 RegUnit() : Weight(0), RegClassUnitSetsIdx(0), Artificial(false) { 495 Roots[0] = Roots[1] = nullptr; 496 } 497 498 ArrayRef<const CodeGenRegister*> getRoots() const { 499 assert(!(Roots[1] && !Roots[0]) && "Invalid roots array"); 500 return makeArrayRef(Roots, !!Roots[0] + !!Roots[1]); 501 } 502 }; 503 504 // Each RegUnitSet is a sorted vector with a name. 505 struct RegUnitSet { 506 typedef std::vector<unsigned>::const_iterator iterator; 507 508 std::string Name; 509 std::vector<unsigned> Units; 510 unsigned Weight = 0; // Cache the sum of all unit weights. 511 unsigned Order = 0; // Cache the sort key. 512 513 RegUnitSet() = default; 514 }; 515 516 // Base vector for identifying TopoSigs. The contents uniquely identify a 517 // TopoSig, only computeSuperRegs needs to know how. 518 typedef SmallVector<unsigned, 16> TopoSigId; 519 520 // CodeGenRegBank - Represent a target's registers and the relations between 521 // them. 522 class CodeGenRegBank { 523 SetTheory Sets; 524 525 const CodeGenHwModes &CGH; 526 527 std::deque<CodeGenSubRegIndex> SubRegIndices; 528 DenseMap<Record*, CodeGenSubRegIndex*> Def2SubRegIdx; 529 530 CodeGenSubRegIndex *createSubRegIndex(StringRef Name, StringRef NameSpace); 531 532 typedef std::map<SmallVector<CodeGenSubRegIndex*, 8>, 533 CodeGenSubRegIndex*> ConcatIdxMap; 534 ConcatIdxMap ConcatIdx; 535 536 // Registers. 537 std::deque<CodeGenRegister> Registers; 538 StringMap<CodeGenRegister*> RegistersByName; 539 DenseMap<Record*, CodeGenRegister*> Def2Reg; 540 unsigned NumNativeRegUnits; 541 542 std::map<TopoSigId, unsigned> TopoSigs; 543 544 // Includes native (0..NumNativeRegUnits-1) and adopted register units. 545 SmallVector<RegUnit, 8> RegUnits; 546 547 // Register classes. 548 std::list<CodeGenRegisterClass> RegClasses; 549 DenseMap<Record*, CodeGenRegisterClass*> Def2RC; 550 typedef std::map<CodeGenRegisterClass::Key, CodeGenRegisterClass*> RCKeyMap; 551 RCKeyMap Key2RC; 552 553 // Remember each unique set of register units. Initially, this contains a 554 // unique set for each register class. Simliar sets are coalesced with 555 // pruneUnitSets and new supersets are inferred during computeRegUnitSets. 556 std::vector<RegUnitSet> RegUnitSets; 557 558 // Map RegisterClass index to the index of the RegUnitSet that contains the 559 // class's units and any inferred RegUnit supersets. 560 // 561 // NOTE: This could grow beyond the number of register classes when we map 562 // register units to lists of unit sets. If the list of unit sets does not 563 // already exist for a register class, we create a new entry in this vector. 564 std::vector<std::vector<unsigned>> RegClassUnitSets; 565 566 // Give each register unit set an order based on sorting criteria. 567 std::vector<unsigned> RegUnitSetOrder; 568 569 // Keep track of synthesized definitions generated in TupleExpander. 570 std::vector<std::unique_ptr<Record>> SynthDefs; 571 572 // Add RC to *2RC maps. 573 void addToMaps(CodeGenRegisterClass*); 574 575 // Create a synthetic sub-class if it is missing. 576 CodeGenRegisterClass *getOrCreateSubClass(const CodeGenRegisterClass *RC, 577 const CodeGenRegister::Vec *Membs, 578 StringRef Name); 579 580 // Infer missing register classes. 581 void computeInferredRegisterClasses(); 582 void inferCommonSubClass(CodeGenRegisterClass *RC); 583 void inferSubClassWithSubReg(CodeGenRegisterClass *RC); 584 585 void inferMatchingSuperRegClass(CodeGenRegisterClass *RC) { 586 inferMatchingSuperRegClass(RC, RegClasses.begin()); 587 } 588 589 void inferMatchingSuperRegClass( 590 CodeGenRegisterClass *RC, 591 std::list<CodeGenRegisterClass>::iterator FirstSubRegRC); 592 593 // Iteratively prune unit sets. 594 void pruneUnitSets(); 595 596 // Compute a weight for each register unit created during getSubRegs. 597 void computeRegUnitWeights(); 598 599 // Create a RegUnitSet for each RegClass and infer superclasses. 600 void computeRegUnitSets(); 601 602 // Populate the Composite map from sub-register relationships. 603 void computeComposites(); 604 605 // Compute a lane mask for each sub-register index. 606 void computeSubRegLaneMasks(); 607 608 /// Computes a lane mask for each register unit enumerated by a physical 609 /// register. 610 void computeRegUnitLaneMasks(); 611 612 public: 613 CodeGenRegBank(RecordKeeper&, const CodeGenHwModes&); 614 615 SetTheory &getSets() { return Sets; } 616 617 const CodeGenHwModes &getHwModes() const { return CGH; } 618 619 // Sub-register indices. The first NumNamedIndices are defined by the user 620 // in the .td files. The rest are synthesized such that all sub-registers 621 // have a unique name. 622 const std::deque<CodeGenSubRegIndex> &getSubRegIndices() const { 623 return SubRegIndices; 624 } 625 626 // Find a SubRegIndex form its Record def. 627 CodeGenSubRegIndex *getSubRegIdx(Record*); 628 629 // Find or create a sub-register index representing the A+B composition. 630 CodeGenSubRegIndex *getCompositeSubRegIndex(CodeGenSubRegIndex *A, 631 CodeGenSubRegIndex *B); 632 633 // Find or create a sub-register index representing the concatenation of 634 // non-overlapping sibling indices. 635 CodeGenSubRegIndex * 636 getConcatSubRegIndex(const SmallVector<CodeGenSubRegIndex *, 8>&); 637 638 const std::deque<CodeGenRegister> &getRegisters() const { 639 return Registers; 640 } 641 642 const StringMap<CodeGenRegister *> &getRegistersByName() const { 643 return RegistersByName; 644 } 645 646 // Find a register from its Record def. 647 CodeGenRegister *getReg(Record*); 648 649 // Get a Register's index into the Registers array. 650 unsigned getRegIndex(const CodeGenRegister *Reg) const { 651 return Reg->EnumValue - 1; 652 } 653 654 // Return the number of allocated TopoSigs. The first TopoSig representing 655 // leaf registers is allocated number 0. 656 unsigned getNumTopoSigs() const { 657 return TopoSigs.size(); 658 } 659 660 // Find or create a TopoSig for the given TopoSigId. 661 // This function is only for use by CodeGenRegister::computeSuperRegs(). 662 // Others should simply use Reg->getTopoSig(). 663 unsigned getTopoSig(const TopoSigId &Id) { 664 return TopoSigs.insert(std::make_pair(Id, TopoSigs.size())).first->second; 665 } 666 667 // Create a native register unit that is associated with one or two root 668 // registers. 669 unsigned newRegUnit(CodeGenRegister *R0, CodeGenRegister *R1 = nullptr) { 670 RegUnits.resize(RegUnits.size() + 1); 671 RegUnit &RU = RegUnits.back(); 672 RU.Roots[0] = R0; 673 RU.Roots[1] = R1; 674 RU.Artificial = R0->Artificial; 675 if (R1) 676 RU.Artificial |= R1->Artificial; 677 return RegUnits.size() - 1; 678 } 679 680 // Create a new non-native register unit that can be adopted by a register 681 // to increase its pressure. Note that NumNativeRegUnits is not increased. 682 unsigned newRegUnit(unsigned Weight) { 683 RegUnits.resize(RegUnits.size() + 1); 684 RegUnits.back().Weight = Weight; 685 return RegUnits.size() - 1; 686 } 687 688 // Native units are the singular unit of a leaf register. Register aliasing 689 // is completely characterized by native units. Adopted units exist to give 690 // register additional weight but don't affect aliasing. 691 bool isNativeUnit(unsigned RUID) const { 692 return RUID < NumNativeRegUnits; 693 } 694 695 unsigned getNumNativeRegUnits() const { 696 return NumNativeRegUnits; 697 } 698 699 RegUnit &getRegUnit(unsigned RUID) { return RegUnits[RUID]; } 700 const RegUnit &getRegUnit(unsigned RUID) const { return RegUnits[RUID]; } 701 702 std::list<CodeGenRegisterClass> &getRegClasses() { return RegClasses; } 703 704 const std::list<CodeGenRegisterClass> &getRegClasses() const { 705 return RegClasses; 706 } 707 708 // Find a register class from its def. 709 CodeGenRegisterClass *getRegClass(Record*); 710 711 /// getRegisterClassForRegister - Find the register class that contains the 712 /// specified physical register. If the register is not in a register 713 /// class, return null. If the register is in multiple classes, and the 714 /// classes have a superset-subset relationship and the same set of types, 715 /// return the superclass. Otherwise return null. 716 const CodeGenRegisterClass* getRegClassForRegister(Record *R); 717 718 // Analog of TargetRegisterInfo::getMinimalPhysRegClass. Unlike 719 // getRegClassForRegister, this tries to find the smallest class containing 720 // the physical register. If \p VT is specified, it will only find classes 721 // with a matching type 722 const CodeGenRegisterClass * 723 getMinimalPhysRegClass(Record *RegRecord, ValueTypeByHwMode *VT = nullptr); 724 725 // Get the sum of unit weights. 726 unsigned getRegUnitSetWeight(const std::vector<unsigned> &Units) const { 727 unsigned Weight = 0; 728 for (std::vector<unsigned>::const_iterator 729 I = Units.begin(), E = Units.end(); I != E; ++I) 730 Weight += getRegUnit(*I).Weight; 731 return Weight; 732 } 733 734 unsigned getRegSetIDAt(unsigned Order) const { 735 return RegUnitSetOrder[Order]; 736 } 737 738 const RegUnitSet &getRegSetAt(unsigned Order) const { 739 return RegUnitSets[RegUnitSetOrder[Order]]; 740 } 741 742 // Increase a RegUnitWeight. 743 void increaseRegUnitWeight(unsigned RUID, unsigned Inc) { 744 getRegUnit(RUID).Weight += Inc; 745 } 746 747 // Get the number of register pressure dimensions. 748 unsigned getNumRegPressureSets() const { return RegUnitSets.size(); } 749 750 // Get a set of register unit IDs for a given dimension of pressure. 751 const RegUnitSet &getRegPressureSet(unsigned Idx) const { 752 return RegUnitSets[Idx]; 753 } 754 755 // The number of pressure set lists may be larget than the number of 756 // register classes if some register units appeared in a list of sets that 757 // did not correspond to an existing register class. 758 unsigned getNumRegClassPressureSetLists() const { 759 return RegClassUnitSets.size(); 760 } 761 762 // Get a list of pressure set IDs for a register class. Liveness of a 763 // register in this class impacts each pressure set in this list by the 764 // weight of the register. An exact solution requires all registers in a 765 // class to have the same class, but it is not strictly guaranteed. 766 ArrayRef<unsigned> getRCPressureSetIDs(unsigned RCIdx) const { 767 return RegClassUnitSets[RCIdx]; 768 } 769 770 // Computed derived records such as missing sub-register indices. 771 void computeDerivedInfo(); 772 773 // Compute the set of registers completely covered by the registers in Regs. 774 // The returned BitVector will have a bit set for each register in Regs, 775 // all sub-registers, and all super-registers that are covered by the 776 // registers in Regs. 777 // 778 // This is used to compute the mask of call-preserved registers from a list 779 // of callee-saves. 780 BitVector computeCoveredRegisters(ArrayRef<Record*> Regs); 781 782 // Bit mask of lanes that cover their registers. A sub-register index whose 783 // LaneMask is contained in CoveringLanes will be completely covered by 784 // another sub-register with the same or larger lane mask. 785 LaneBitmask CoveringLanes; 786 787 // Helper function for printing debug information. Handles artificial 788 // (non-native) reg units. 789 void printRegUnitName(unsigned Unit) const; 790 }; 791 792} // end namespace llvm 793 794#endif // LLVM_UTILS_TABLEGEN_CODEGENREGISTERS_H 795