X86ScheduleSLM.td revision 360784
1139804Simp//=- X86ScheduleSLM.td - X86 Silvermont Scheduling -----------*- tablegen -*-=// 246197Sphk// 346197Sphk// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 446197Sphk// See https://llvm.org/LICENSE.txt for license information. 546197Sphk// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 646197Sphk// 746197Sphk//===----------------------------------------------------------------------===// 846197Sphk// 946155Sphk// This file defines the machine model for Intel Silvermont to support 10116182Sobrien// instruction scheduling and other instruction cost heuristics. 11116182Sobrien// 12116182Sobrien//===----------------------------------------------------------------------===// 13131177Spjd 14131177Spjddef SLMModel : SchedMachineModel { 1546155Sphk // All x86 instructions are modeled as a single micro-op, and SLM can decode 2 1646155Sphk // instructions per cycle. 1746155Sphk let IssueWidth = 2; 1846155Sphk let MicroOpBufferSize = 32; // Based on the reorder buffer. 1946155Sphk let LoadLatency = 3; 2046155Sphk let MispredictPenalty = 10; 2146155Sphk let PostRAScheduler = 1; 22164032Srwatson 2346155Sphk // For small loops, expand by a small factor to hide the backedge cost. 24124882Srwatson let LoopMicroOpBufferSize = 10; 2546155Sphk 2687275Srwatson // FIXME: SSE4 is unimplemented. This flag is set to allow 2787275Srwatson // the scheduler to assign a default model to unrecognized opcodes. 28113275Smike let CompleteModel = 0; 29147185Spjd} 30113275Smike 3146155Sphklet SchedModel = SLMModel in { 32113275Smike 3357163Srwatson// Silvermont has 5 reservation stations for micro-ops 34113275Smikedef SLM_IEC_RSV0 : ProcResource<1>; 3546155Sphkdef SLM_IEC_RSV1 : ProcResource<1>; 3646155Sphkdef SLM_FPC_RSV0 : ProcResource<1> { let BufferSize = 1; } 3746155Sphkdef SLM_FPC_RSV1 : ProcResource<1> { let BufferSize = 1; } 38163606Srwatsondef SLM_MEC_RSV : ProcResource<1>; 39163606Srwatson 4046155Sphk// Many micro-ops are capable of issuing on multiple ports. 4146155Sphkdef SLM_IEC_RSV01 : ProcResGroup<[SLM_IEC_RSV0, SLM_IEC_RSV1]>; 4289414Sarrdef SLM_FPC_RSV01 : ProcResGroup<[SLM_FPC_RSV0, SLM_FPC_RSV1]>; 4357163Srwatson 4457163Srwatsondef SLMDivider : ProcResource<1>; 4557163Srwatsondef SLMFPMultiplier : ProcResource<1>; 4689414Sarrdef SLMFPDivider : ProcResource<1>; 4757163Srwatson 4857163Srwatson// Loads are 3 cycles, so ReadAfterLd registers needn't be available until 3 4957163Srwatson// cycles after the memory operand. 5061235Srwatsondef : ReadAdvance<ReadAfterLd, 3>; 5189414Sarrdef : ReadAdvance<ReadAfterVecLd, 3>; 5261235Srwatsondef : ReadAdvance<ReadAfterVecXLd, 3>; 5361235Srwatsondef : ReadAdvance<ReadAfterVecYLd, 3>; 5461235Srwatson 5568024Srwatsondef : ReadAdvance<ReadInt2Fpu, 0>; 5689414Sarr 5768024Srwatson// Many SchedWrites are defined in pairs with and without a folded load. 5868024Srwatson// Instructions with folded loads are usually micro-fused, so they only appear 5968024Srwatson// as two micro-ops when queued in the reservation station. 60147185Spjd// This multiclass defines the resource usage for variants with and without 61147185Spjd// folded loads. 62147185Spjdmulticlass SLMWriteResPair<X86FoldableSchedWrite SchedRW, 63147185Spjd list<ProcResourceKind> ExePorts, 64125804Srwatson int Lat, list<int> Res = [1], int UOps = 1, 65128664Sbmilekic int LoadLat = 3> { 66128664Sbmilekic // Register variant is using a single cycle on ExePort. 67128664Sbmilekic def : WriteRes<SchedRW, ExePorts> { 68128664Sbmilekic let Latency = Lat; 69128664Sbmilekic let ResourceCycles = Res; 70141543Scperciva let NumMicroOps = UOps; 71141543Scperciva } 72141543Scperciva 73141543Scperciva // Memory variant also uses a cycle on MEC_RSV and adds LoadLat cycles to 74141543Scperciva // the latency (default = 3). 75113275Smike def : WriteRes<SchedRW.Folded, !listconcat([SLM_MEC_RSV], ExePorts)> { 76113275Smike let Latency = !add(Lat, LoadLat); 77113275Smike let ResourceCycles = !listconcat([1], Res); 78113275Smike let NumMicroOps = UOps; 79113275Smike } 80113275Smike} 81113275Smike 82124882Srwatson// A folded store needs a cycle on MEC_RSV for the store data, but it does not 83113275Smike// need an extra port cycle to recompute the address. 84113275Smikedef : WriteRes<WriteRMW, [SLM_MEC_RSV]>; 85113275Smike 86113275Smikedef : WriteRes<WriteStore, [SLM_IEC_RSV01, SLM_MEC_RSV]>; 87113275Smikedef : WriteRes<WriteStoreNT, [SLM_IEC_RSV01, SLM_MEC_RSV]>; 88113275Smikedef : WriteRes<WriteLoad, [SLM_MEC_RSV]> { let Latency = 3; } 89113275Smikedef : WriteRes<WriteMove, [SLM_IEC_RSV01]>; 90113275Smikedef : WriteRes<WriteZero, []>; 91113275Smike 92113275Smike// Load/store MXCSR. 93113275Smike// FIXME: These are probably wrong. They are copy pasted from WriteStore/Load. 94113275Smikedef : WriteRes<WriteSTMXCSR, [SLM_IEC_RSV01, SLM_MEC_RSV]>; 95113275Smikedef : WriteRes<WriteLDMXCSR, [SLM_MEC_RSV]> { let Latency = 3; } 9682710Sdillon 97114168Smike// Treat misc copies as a move. 98114168Smikedef : InstRW<[WriteMove], (instrs COPY)>; 99114168Smike 10082710Sdillondefm : SLMWriteResPair<WriteALU, [SLM_IEC_RSV01], 1>; 10146155Sphkdefm : SLMWriteResPair<WriteADC, [SLM_IEC_RSV01], 1>; 102114168Smike 10346155Sphkdefm : SLMWriteResPair<WriteIMul8, [SLM_IEC_RSV1], 3>; 104113275Smikedefm : SLMWriteResPair<WriteIMul16, [SLM_IEC_RSV1], 3>; 105113275Smikedefm : SLMWriteResPair<WriteIMul16Imm, [SLM_IEC_RSV1], 3>; 10646155Sphkdefm : SLMWriteResPair<WriteIMul16Reg, [SLM_IEC_RSV1], 3>; 107113275Smikedefm : SLMWriteResPair<WriteIMul32, [SLM_IEC_RSV1], 3>; 108150652Scsjpdefm : SLMWriteResPair<WriteIMul32Imm, [SLM_IEC_RSV1], 3>; 10946155Sphkdefm : SLMWriteResPair<WriteIMul32Reg, [SLM_IEC_RSV1], 3>; 110114168Smikedefm : SLMWriteResPair<WriteIMul64, [SLM_IEC_RSV1], 3>; 11146155Sphkdefm : SLMWriteResPair<WriteIMul64Imm, [SLM_IEC_RSV1], 3>; 11284828Sjhbdefm : SLMWriteResPair<WriteIMul64Reg, [SLM_IEC_RSV1], 3>; 11384828Sjhb 11484828Sjhbdefm : X86WriteRes<WriteBSWAP32, [SLM_IEC_RSV01], 1, [1], 1>; 11584828Sjhbdefm : X86WriteRes<WriteBSWAP64, [SLM_IEC_RSV01], 1, [1], 1>; 116114168Smikedefm : X86WriteRes<WriteCMPXCHG, [SLM_IEC_RSV01], 1, [1], 1>; 11793818Sjhbdefm : X86WriteRes<WriteCMPXCHGRMW, [SLM_IEC_RSV01, SLM_MEC_RSV], 4, [1, 2], 2>; 118113275Smikedefm : X86WriteRes<WriteXCHG, [SLM_IEC_RSV01], 1, [1], 1>; 119114168Smike 120113275Smikedefm : SLMWriteResPair<WriteShift, [SLM_IEC_RSV0], 1>; 121113275Smikedefm : SLMWriteResPair<WriteShiftCL, [SLM_IEC_RSV0], 1>; 122150652Scsjpdefm : SLMWriteResPair<WriteRotate, [SLM_IEC_RSV0], 1>; 123150652Scsjpdefm : SLMWriteResPair<WriteRotateCL, [SLM_IEC_RSV0], 1>; 124113275Smike 125150652Scsjpdefm : X86WriteRes<WriteSHDrri, [SLM_IEC_RSV0], 1, [1], 1>; 126113275Smikedefm : X86WriteRes<WriteSHDrrcl,[SLM_IEC_RSV0], 1, [1], 1>; 127150652Scsjpdefm : X86WriteRes<WriteSHDmri, [SLM_MEC_RSV, SLM_IEC_RSV0], 4, [2, 1], 2>; 128113275Smikedefm : X86WriteRes<WriteSHDmrcl,[SLM_MEC_RSV, SLM_IEC_RSV0], 4, [2, 1], 2>; 129113275Smike 130113275Smikedefm : SLMWriteResPair<WriteJump, [SLM_IEC_RSV1], 1>; 131150652Scsjpdefm : SLMWriteResPair<WriteCRC32, [SLM_IEC_RSV1], 3>; 132114168Smike 13384828Sjhbdefm : SLMWriteResPair<WriteCMOV, [SLM_IEC_RSV01], 2, [2]>; 134113275Smikedefm : X86WriteRes<WriteFCMOV, [SLM_FPC_RSV1], 3, [1], 1>; // x87 conditional move. 135113275Smikedef : WriteRes<WriteSETCC, [SLM_IEC_RSV01]>; 136113275Smikedef : WriteRes<WriteSETCCStore, [SLM_IEC_RSV01, SLM_MEC_RSV]> { 137113275Smike // FIXME Latency and NumMicrOps? 138113275Smike let ResourceCycles = [2,1]; 139113275Smike} 140113275Smikedefm : X86WriteRes<WriteLAHFSAHF, [SLM_IEC_RSV01], 1, [1], 1>; 141113275Smikedefm : X86WriteRes<WriteBitTest, [SLM_IEC_RSV01], 1, [1], 1>; 142113275Smikedefm : X86WriteRes<WriteBitTestImmLd, [SLM_IEC_RSV01, SLM_MEC_RSV], 4, [1,1], 1>; 143113275Smikedefm : X86WriteRes<WriteBitTestRegLd, [SLM_IEC_RSV01, SLM_MEC_RSV], 4, [1,1], 1>; 144113275Smikedefm : X86WriteRes<WriteBitTestSet, [SLM_IEC_RSV01], 1, [1], 1>; 145113275Smikedefm : X86WriteRes<WriteBitTestSetImmLd, [SLM_IEC_RSV01, SLM_MEC_RSV], 3, [1,1], 1>; 146113275Smikedefm : X86WriteRes<WriteBitTestSetRegLd, [SLM_IEC_RSV01, SLM_MEC_RSV], 3, [1,1], 1>; 147113275Smike 148113275Smike// This is for simple LEAs with one or two input operands. 149113275Smike// The complex ones can only execute on port 1, and they require two cycles on 150113275Smike// the port to read all inputs. We don't model that. 151113275Smikedef : WriteRes<WriteLEA, [SLM_IEC_RSV1]>; 152113275Smike 153113275Smike// Bit counts. 154113275Smikedefm : SLMWriteResPair<WriteBSF, [SLM_IEC_RSV01], 10, [20], 10>; 155113275Smikedefm : SLMWriteResPair<WriteBSR, [SLM_IEC_RSV01], 10, [20], 10>; 156113275Smikedefm : SLMWriteResPair<WriteLZCNT, [SLM_IEC_RSV0], 3>; 157113275Smikedefm : SLMWriteResPair<WriteTZCNT, [SLM_IEC_RSV0], 3>; 158113275Smikedefm : SLMWriteResPair<WritePOPCNT, [SLM_IEC_RSV0], 3>; 159113275Smike 160113275Smike// BMI1 BEXTR/BLS, BMI2 BZHI 161113275Smikedefm : X86WriteResPairUnsupported<WriteBEXTR>; 162113275Smikedefm : X86WriteResPairUnsupported<WriteBLS>; 163113275Smikedefm : X86WriteResPairUnsupported<WriteBZHI>; 164113275Smike 165113275Smikedefm : SLMWriteResPair<WriteDiv8, [SLM_IEC_RSV01, SLMDivider], 25, [1,25], 1, 4>; 166113275Smikedefm : SLMWriteResPair<WriteDiv16, [SLM_IEC_RSV01, SLMDivider], 25, [1,25], 1, 4>; 167113275Smikedefm : SLMWriteResPair<WriteDiv32, [SLM_IEC_RSV01, SLMDivider], 25, [1,25], 1, 4>; 168113275Smikedefm : SLMWriteResPair<WriteDiv64, [SLM_IEC_RSV01, SLMDivider], 25, [1,25], 1, 4>; 169113275Smikedefm : SLMWriteResPair<WriteIDiv8, [SLM_IEC_RSV01, SLMDivider], 25, [1,25], 1, 4>; 170113275Smikedefm : SLMWriteResPair<WriteIDiv16, [SLM_IEC_RSV01, SLMDivider], 25, [1,25], 1, 4>; 171113275Smikedefm : SLMWriteResPair<WriteIDiv32, [SLM_IEC_RSV01, SLMDivider], 25, [1,25], 1, 4>; 172113275Smikedefm : SLMWriteResPair<WriteIDiv64, [SLM_IEC_RSV01, SLMDivider], 25, [1,25], 1, 4>; 173113275Smike 174113275Smike// Scalar and vector floating point. 175150652Scsjpdefm : X86WriteRes<WriteFLD0, [SLM_FPC_RSV01], 1, [1], 1>; 176113275Smikedefm : X86WriteRes<WriteFLD1, [SLM_FPC_RSV01], 1, [1], 1>; 177150652Scsjpdefm : X86WriteRes<WriteFLDC, [SLM_FPC_RSV01], 1, [2], 2>; 178113275Smikedef : WriteRes<WriteFLoad, [SLM_MEC_RSV]> { let Latency = 3; } 179113275Smikedef : WriteRes<WriteFLoadX, [SLM_MEC_RSV]> { let Latency = 3; } 180113275Smikedef : WriteRes<WriteFLoadY, [SLM_MEC_RSV]> { let Latency = 3; } 181113275Smikedef : WriteRes<WriteFMaskedLoad, [SLM_MEC_RSV]> { let Latency = 3; } 182113275Smikedef : WriteRes<WriteFMaskedLoadY, [SLM_MEC_RSV]> { let Latency = 3; } 183113275Smikedef : WriteRes<WriteFStore, [SLM_MEC_RSV]>; 184113275Smikedef : WriteRes<WriteFStoreX, [SLM_MEC_RSV]>; 185114168Smikedef : WriteRes<WriteFStoreY, [SLM_MEC_RSV]>; 186114168Smikedef : WriteRes<WriteFStoreNT, [SLM_MEC_RSV]>; 187114168Smikedef : WriteRes<WriteFStoreNTX, [SLM_MEC_RSV]>; 188113275Smikedef : WriteRes<WriteFStoreNTY, [SLM_MEC_RSV]>; 189113275Smike 190114168Smikedef : WriteRes<WriteFMaskedStore32, [SLM_MEC_RSV]>; 191113275Smikedef : WriteRes<WriteFMaskedStore32Y, [SLM_MEC_RSV]>; 192113275Smikedef : WriteRes<WriteFMaskedStore64, [SLM_MEC_RSV]>; 193113275Smikedef : WriteRes<WriteFMaskedStore64Y, [SLM_MEC_RSV]>; 194113275Smike 195150652Scsjpdef : WriteRes<WriteFMove, [SLM_FPC_RSV01]>; 196167309Spjddef : WriteRes<WriteFMoveX, [SLM_FPC_RSV01]>; 197126023Snectardef : WriteRes<WriteFMoveY, [SLM_FPC_RSV01]>; 198126023Snectardefm : X86WriteRes<WriteEMMS, [SLM_FPC_RSV01], 10, [10], 9>; 199126023Snectar 200126023Snectardefm : SLMWriteResPair<WriteFAdd, [SLM_FPC_RSV1], 3>; 201126023Snectardefm : SLMWriteResPair<WriteFAddX, [SLM_FPC_RSV1], 3>; 202126023Snectardefm : SLMWriteResPair<WriteFAddY, [SLM_FPC_RSV1], 3>; 203126023Snectardefm : X86WriteResPairUnsupported<WriteFAddZ>; 204126023Snectardefm : SLMWriteResPair<WriteFAdd64, [SLM_FPC_RSV1], 3>; 205164032Srwatsondefm : SLMWriteResPair<WriteFAdd64X, [SLM_FPC_RSV1], 4, [2]>; 206126023Snectardefm : SLMWriteResPair<WriteFAdd64Y, [SLM_FPC_RSV1], 4, [2]>; 207126023Snectardefm : X86WriteResPairUnsupported<WriteFAdd64Z>; 208126023Snectardefm : SLMWriteResPair<WriteFCmp, [SLM_FPC_RSV1], 3>; 209113275Smikedefm : SLMWriteResPair<WriteFCmpX, [SLM_FPC_RSV1], 3>; 210113275Smikedefm : SLMWriteResPair<WriteFCmpY, [SLM_FPC_RSV1], 3>; 211113275Smikedefm : X86WriteResPairUnsupported<WriteFCmpZ>; 212113275Smikedefm : SLMWriteResPair<WriteFCmp64, [SLM_FPC_RSV1], 3>; 213113275Smikedefm : SLMWriteResPair<WriteFCmp64X, [SLM_FPC_RSV1], 3>; 214113275Smikedefm : SLMWriteResPair<WriteFCmp64Y, [SLM_FPC_RSV1], 3>; 215113275Smikedefm : X86WriteResPairUnsupported<WriteFCmp64Z>; 216113275Smikedefm : SLMWriteResPair<WriteFCom, [SLM_FPC_RSV1], 3>; 217113275Smikedefm : SLMWriteResPair<WriteFMul, [SLM_FPC_RSV0, SLMFPMultiplier], 5, [1,2]>; 218113275Smikedefm : SLMWriteResPair<WriteFMulX, [SLM_FPC_RSV0, SLMFPMultiplier], 5, [1,2]>; 219113275Smikedefm : SLMWriteResPair<WriteFMulY, [SLM_FPC_RSV0, SLMFPMultiplier], 5, [1,2]>; 220150652Scsjpdefm : X86WriteResPairUnsupported<WriteFMulZ>; 221113275Smikedefm : SLMWriteResPair<WriteFMul64, [SLM_FPC_RSV0, SLMFPMultiplier], 5, [1,2]>; 222113275Smikedefm : SLMWriteResPair<WriteFMul64X, [SLM_FPC_RSV0, SLMFPMultiplier], 7, [1,4]>; 223113275Smikedefm : SLMWriteResPair<WriteFMul64Y, [SLM_FPC_RSV0, SLMFPMultiplier], 7, [1,4]>; 224113275Smikedefm : X86WriteResPairUnsupported<WriteFMul64Z>; 225113275Smikedefm : SLMWriteResPair<WriteFDiv, [SLM_FPC_RSV0, SLMFPDivider], 19, [1,17]>; 226113275Smikedefm : SLMWriteResPair<WriteFDivX, [SLM_FPC_RSV0, SLMFPDivider], 39, [1,39]>; 227113275Smikedefm : SLMWriteResPair<WriteFDivY, [SLM_FPC_RSV0, SLMFPDivider], 39, [1,39]>; 228113275Smikedefm : X86WriteResPairUnsupported<WriteFDivZ>; 229113275Smikedefm : SLMWriteResPair<WriteFDiv64, [SLM_FPC_RSV0, SLMFPDivider], 34, [1,32]>; 230150652Scsjpdefm : SLMWriteResPair<WriteFDiv64X, [SLM_FPC_RSV0, SLMFPDivider], 69, [1,69]>; 231113275Smikedefm : SLMWriteResPair<WriteFDiv64Y, [SLM_FPC_RSV0, SLMFPDivider], 69, [1,69]>; 23284828Sjhbdefm : X86WriteResPairUnsupported<WriteFDiv64Z>; 23384828Sjhbdefm : SLMWriteResPair<WriteFRcp, [SLM_FPC_RSV0], 5>; 23484828Sjhbdefm : SLMWriteResPair<WriteFRcpX, [SLM_FPC_RSV0], 5>; 235113275Smikedefm : SLMWriteResPair<WriteFRcpY, [SLM_FPC_RSV0], 5>; 23684828Sjhbdefm : X86WriteResPairUnsupported<WriteFRcpZ>; 237113630Sjhbdefm : SLMWriteResPair<WriteFRsqrt, [SLM_FPC_RSV0], 5>; 23884828Sjhbdefm : SLMWriteResPair<WriteFRsqrtX, [SLM_FPC_RSV0], 5>; 23984828Sjhbdefm : SLMWriteResPair<WriteFRsqrtY, [SLM_FPC_RSV0], 5>; 24084828Sjhbdefm : X86WriteResPairUnsupported<WriteFRsqrtZ>; 24146155Sphkdefm : SLMWriteResPair<WriteFSqrt, [SLM_FPC_RSV0,SLMFPDivider], 20, [1,20], 1, 3>; 242113275Smikedefm : SLMWriteResPair<WriteFSqrtX, [SLM_FPC_RSV0,SLMFPDivider], 41, [1,40], 1, 3>; 243113275Smikedefm : SLMWriteResPair<WriteFSqrtY, [SLM_FPC_RSV0,SLMFPDivider], 41, [1,40], 1, 3>; 244150652Scsjpdefm : X86WriteResPairUnsupported<WriteFSqrtZ>; 245113275Smikedefm : SLMWriteResPair<WriteFSqrt64, [SLM_FPC_RSV0,SLMFPDivider], 35, [1,35], 1, 3>; 246113275Smikedefm : SLMWriteResPair<WriteFSqrt64X, [SLM_FPC_RSV0,SLMFPDivider], 71, [1,70], 1, 3>; 247113275Smikedefm : SLMWriteResPair<WriteFSqrt64Y, [SLM_FPC_RSV0,SLMFPDivider], 71, [1,70], 1, 3>; 24846155Sphkdefm : X86WriteResPairUnsupported<WriteFSqrt64Z>; 24946155Sphkdefm : SLMWriteResPair<WriteFSqrt80, [SLM_FPC_RSV0,SLMFPDivider], 40, [1,40]>; 25046155Sphkdefm : SLMWriteResPair<WriteDPPD, [SLM_FPC_RSV1], 3>; 251113275Smikedefm : SLMWriteResPair<WriteDPPS, [SLM_FPC_RSV1], 3>; 252113275Smikedefm : SLMWriteResPair<WriteDPPSY, [SLM_FPC_RSV1], 3>; 253113275Smikedefm : X86WriteResPairUnsupported<WriteDPPSZ>; 254113275Smikedefm : SLMWriteResPair<WriteFSign, [SLM_FPC_RSV01], 1>; 255113275Smikedefm : SLMWriteResPair<WriteFRnd, [SLM_FPC_RSV1], 3>; 256113275Smikedefm : SLMWriteResPair<WriteFRndY, [SLM_FPC_RSV1], 3>; 257113275Smikedefm : X86WriteResPairUnsupported<WriteFRndZ>; 258113275Smikedefm : SLMWriteResPair<WriteFLogic, [SLM_FPC_RSV01], 1>; 259113275Smikedefm : SLMWriteResPair<WriteFLogicY, [SLM_FPC_RSV01], 1>; 260113275Smikedefm : X86WriteResPairUnsupported<WriteFLogicZ>; 261113275Smikedefm : SLMWriteResPair<WriteFTest, [SLM_FPC_RSV01], 1>; 262113275Smikedefm : SLMWriteResPair<WriteFTestY, [SLM_FPC_RSV01], 1>; 263113275Smikedefm : X86WriteResPairUnsupported<WriteFTestZ>; 264113275Smikedefm : SLMWriteResPair<WriteFShuffle, [SLM_FPC_RSV0], 1>; 265113275Smikedefm : SLMWriteResPair<WriteFShuffleY, [SLM_FPC_RSV0], 1>; 266113275Smikedefm : X86WriteResPairUnsupported<WriteFShuffleZ>; 267113275Smikedefm : SLMWriteResPair<WriteFVarShuffle, [SLM_FPC_RSV0], 1>; 268113275Smikedefm : SLMWriteResPair<WriteFVarShuffleY,[SLM_FPC_RSV0], 1>; 26972786Srwatsondefm : X86WriteResPairUnsupported<WriteFVarShuffleZ>; 27072786Srwatsondefm : SLMWriteResPair<WriteFBlend, [SLM_FPC_RSV0], 1>; 27172786Srwatson 27272786Srwatson// Conversion between integer and float. 273113275Smikedefm : SLMWriteResPair<WriteCvtSS2I, [SLM_FPC_RSV01], 4>; 27487275Srwatsondefm : SLMWriteResPair<WriteCvtPS2I, [SLM_FPC_RSV01], 4>; 27572786Srwatsondefm : SLMWriteResPair<WriteCvtPS2IY, [SLM_FPC_RSV01], 4>; 27672786Srwatsondefm : X86WriteResPairUnsupported<WriteCvtPS2IZ>; 277113275Smikedefm : SLMWriteResPair<WriteCvtSD2I, [SLM_FPC_RSV01], 4>; 27887275Srwatsondefm : SLMWriteResPair<WriteCvtPD2I, [SLM_FPC_RSV01], 4>; 279113275Smikedefm : SLMWriteResPair<WriteCvtPD2IY, [SLM_FPC_RSV01], 4>; 280113275Smikedefm : X86WriteResPairUnsupported<WriteCvtPD2IZ>; 281124882Srwatson 282124882Srwatsondefm : SLMWriteResPair<WriteCvtI2SS, [SLM_FPC_RSV01], 4>; 283144660Sjeffdefm : SLMWriteResPair<WriteCvtI2PS, [SLM_FPC_RSV01], 4>; 28487275Srwatsondefm : SLMWriteResPair<WriteCvtI2PSY, [SLM_FPC_RSV01], 4>; 28572786Srwatsondefm : X86WriteResPairUnsupported<WriteCvtI2PSZ>; 28687275Srwatsondefm : SLMWriteResPair<WriteCvtI2SD, [SLM_FPC_RSV01], 4>; 287113275Smikedefm : SLMWriteResPair<WriteCvtI2PD, [SLM_FPC_RSV01], 4>; 28872786Srwatsondefm : SLMWriteResPair<WriteCvtI2PDY, [SLM_FPC_RSV01], 4>; 28972786Srwatsondefm : X86WriteResPairUnsupported<WriteCvtI2PDZ>; 290124882Srwatson 291124882Srwatsondefm : SLMWriteResPair<WriteCvtSS2SD, [SLM_FPC_RSV01], 4>; 292124882Srwatsondefm : SLMWriteResPair<WriteCvtPS2PD, [SLM_FPC_RSV01], 4>; 293124882Srwatsondefm : SLMWriteResPair<WriteCvtPS2PDY, [SLM_FPC_RSV01], 4>; 294150652Scsjpdefm : X86WriteResPairUnsupported<WriteCvtPS2PDZ>; 295124882Srwatsondefm : SLMWriteResPair<WriteCvtSD2SS, [SLM_FPC_RSV01], 4>; 296124882Srwatsondefm : SLMWriteResPair<WriteCvtPD2PS, [SLM_FPC_RSV01], 4>; 297124882Srwatsondefm : SLMWriteResPair<WriteCvtPD2PSY, [SLM_FPC_RSV01], 4>; 298150652Scsjpdefm : X86WriteResPairUnsupported<WriteCvtPD2PSZ>; 299124882Srwatson 300150652Scsjp// Vector integer operations. 301124882Srwatsondef : WriteRes<WriteVecLoad, [SLM_MEC_RSV]> { let Latency = 3; } 302124882Srwatsondef : WriteRes<WriteVecLoadX, [SLM_MEC_RSV]> { let Latency = 3; } 303124882Srwatsondef : WriteRes<WriteVecLoadY, [SLM_MEC_RSV]> { let Latency = 3; } 304124882Srwatsondef : WriteRes<WriteVecLoadNT, [SLM_MEC_RSV]> { let Latency = 3; } 305124882Srwatsondef : WriteRes<WriteVecLoadNTY, [SLM_MEC_RSV]> { let Latency = 3; } 306124882Srwatsondef : WriteRes<WriteVecMaskedLoad, [SLM_MEC_RSV]> { let Latency = 3; } 307124882Srwatsondef : WriteRes<WriteVecMaskedLoadY, [SLM_MEC_RSV]> { let Latency = 3; } 30872786Srwatsondef : WriteRes<WriteVecStore, [SLM_MEC_RSV]>; 30972786Srwatsondef : WriteRes<WriteVecStoreX, [SLM_MEC_RSV]>; 31072786Srwatsondef : WriteRes<WriteVecStoreY, [SLM_MEC_RSV]>; 31172786Srwatsondef : WriteRes<WriteVecStoreNT, [SLM_MEC_RSV]>; 31287275Srwatsondef : WriteRes<WriteVecStoreNTY, [SLM_MEC_RSV]>; 31372786Srwatsondef : WriteRes<WriteVecMaskedStore, [SLM_MEC_RSV]>; 31487275Srwatsondef : WriteRes<WriteVecMaskedStoreY, [SLM_MEC_RSV]>; 31572786Srwatsondef : WriteRes<WriteVecMove, [SLM_FPC_RSV01]>; 31672786Srwatsondef : WriteRes<WriteVecMoveX, [SLM_FPC_RSV01]>; 31787275Srwatsondef : WriteRes<WriteVecMoveY, [SLM_FPC_RSV01]>; 31887275Srwatsondef : WriteRes<WriteVecMoveToGpr, [SLM_IEC_RSV01]>; 31987275Srwatsondef : WriteRes<WriteVecMoveFromGpr, [SLM_IEC_RSV01]>; 32087275Srwatson 32187275Srwatsondefm : SLMWriteResPair<WriteVecShift, [SLM_FPC_RSV0], 1>; 32287275Srwatsondefm : SLMWriteResPair<WriteVecShiftX, [SLM_FPC_RSV0], 1>; 32387275Srwatsondefm : SLMWriteResPair<WriteVecShiftY, [SLM_FPC_RSV0], 1>; 32446155Sphkdefm : X86WriteResPairUnsupported<WriteVecShiftZ>; 32572786Srwatsondefm : SLMWriteResPair<WriteVecShiftImm, [SLM_FPC_RSV0], 1>; 32646155Sphkdefm : SLMWriteResPair<WriteVecShiftImmX,[SLM_FPC_RSV0], 1>; 32746155Sphkdefm : SLMWriteResPair<WriteVecShiftImmY,[SLM_FPC_RSV0], 1>; 32846155Sphkdefm : X86WriteResPairUnsupported<WriteVecShiftImmZ>; 32972786Srwatsondefm : SLMWriteResPair<WriteVecLogic, [SLM_FPC_RSV01], 1>; 33046155Sphkdefm : SLMWriteResPair<WriteVecLogicX,[SLM_FPC_RSV01], 1>; 331167309Spjddefm : SLMWriteResPair<WriteVecLogicY,[SLM_FPC_RSV01], 1>; 33246155Sphkdefm : X86WriteResPairUnsupported<WriteVecLogicZ>; 33346155Sphkdefm : SLMWriteResPair<WriteVecTest, [SLM_FPC_RSV01], 1>; 33446155Sphkdefm : SLMWriteResPair<WriteVecTestY, [SLM_FPC_RSV01], 1>; 33546155Sphkdefm : X86WriteResPairUnsupported<WriteVecTestZ>; 336167309Spjddefm : SLMWriteResPair<WriteVecALU, [SLM_FPC_RSV01], 1>; 33772786Srwatsondefm : SLMWriteResPair<WriteVecALUX, [SLM_FPC_RSV01], 1>; 33846155Sphkdefm : SLMWriteResPair<WriteVecALUY, [SLM_FPC_RSV01], 1>; 33972786Srwatsondefm : X86WriteResPairUnsupported<WriteVecALUZ>; 34046155Sphkdefm : SLMWriteResPair<WriteVecIMul, [SLM_FPC_RSV0], 4>; 34146155Sphkdefm : SLMWriteResPair<WriteVecIMulX, [SLM_FPC_RSV0], 4>; 34281114Srwatsondefm : SLMWriteResPair<WriteVecIMulY, [SLM_FPC_RSV0], 4>; 34381114Srwatsondefm : X86WriteResPairUnsupported<WriteVecIMulZ>; 34481114Srwatson// FIXME: The below is closer to correct, but caused some perf regressions. 34581114Srwatson//defm : SLMWriteResPair<WritePMULLD, [SLM_FPC_RSV0], 11, [11], 7>; 34681114Srwatsondefm : SLMWriteResPair<WritePMULLD, [SLM_FPC_RSV0], 4>; 34781114Srwatsondefm : SLMWriteResPair<WritePMULLDY, [SLM_FPC_RSV0], 4>; 34881114Srwatsondefm : X86WriteResPairUnsupported<WritePMULLDZ>; 34972786Srwatsondefm : SLMWriteResPair<WriteShuffle, [SLM_FPC_RSV0], 1>; 35046155Sphkdefm : SLMWriteResPair<WriteShuffleY, [SLM_FPC_RSV0], 1>; 35146155Sphkdefm : X86WriteResPairUnsupported<WriteShuffleZ>; 35246155Sphkdefm : SLMWriteResPair<WriteShuffleX, [SLM_FPC_RSV0], 1>; 35346155Sphkdefm : SLMWriteResPair<WriteVarShuffle, [SLM_FPC_RSV0], 1>; 35446155Sphkdefm : SLMWriteResPair<WriteVarShuffleX, [SLM_FPC_RSV0], 1>; 35572786Srwatsondefm : SLMWriteResPair<WriteVarShuffleY, [SLM_FPC_RSV0], 1>; 35646155Sphkdefm : X86WriteResPairUnsupported<WriteVarShuffleZ>; 35746155Sphkdefm : SLMWriteResPair<WriteBlend, [SLM_FPC_RSV0], 1>; 35846155Sphkdefm : SLMWriteResPair<WriteBlendY, [SLM_FPC_RSV0], 1>; 35972786Srwatsondefm : X86WriteResPairUnsupported<WriteBlendZ>; 36046155Sphkdefm : SLMWriteResPair<WriteMPSAD, [SLM_FPC_RSV0], 7>; 36146155Sphkdefm : SLMWriteResPair<WriteMPSADY, [SLM_FPC_RSV0], 7>; 36246155Sphkdefm : X86WriteResPairUnsupported<WriteMPSADZ>; 36346155Sphkdefm : SLMWriteResPair<WritePSADBW, [SLM_FPC_RSV0], 4>; 36446155Sphkdefm : SLMWriteResPair<WritePSADBWX, [SLM_FPC_RSV0], 4>; 36581114Srwatsondefm : SLMWriteResPair<WritePSADBWY, [SLM_FPC_RSV0], 4>; 36646155Sphkdefm : X86WriteResPairUnsupported<WritePSADBWZ>; 36772786Srwatsondefm : SLMWriteResPair<WritePHMINPOS, [SLM_FPC_RSV0], 4>; 36846155Sphk 36972786Srwatson// Vector insert/extract operations. 37046155Sphkdefm : SLMWriteResPair<WriteVecInsert, [SLM_FPC_RSV0], 1>; 37146155Sphk 37246155Sphkdef : WriteRes<WriteVecExtract, [SLM_FPC_RSV0]>; 37346155Sphkdef : WriteRes<WriteVecExtractSt, [SLM_FPC_RSV0, SLM_MEC_RSV]> { 37446155Sphk let Latency = 4; 37546155Sphk let NumMicroOps = 2; 37672786Srwatson let ResourceCycles = [1, 2]; 37746155Sphk} 378114168Smike 37946155Sphk//////////////////////////////////////////////////////////////////////////////// 38046155Sphk// Horizontal add/sub instructions. 381114168Smike//////////////////////////////////////////////////////////////////////////////// 38261235Srwatson 38361235Srwatsondefm : SLMWriteResPair<WriteFHAdd, [SLM_FPC_RSV01], 6, [6], 4>; 38461235Srwatsondefm : SLMWriteResPair<WriteFHAddY, [SLM_FPC_RSV01], 6, [6], 4>; 38546155Sphkdefm : X86WriteResPairUnsupported<WriteFHAddZ>; 38672786Srwatsondefm : SLMWriteResPair<WritePHAdd, [SLM_FPC_RSV01], 1>; 38746155Sphkdefm : SLMWriteResPair<WritePHAddX, [SLM_FPC_RSV01], 1>; 38846155Sphkdefm : SLMWriteResPair<WritePHAddY, [SLM_FPC_RSV01], 1>; 38946155Sphkdefm : X86WriteResPairUnsupported<WritePHAddZ>; 39046155Sphk 39146155Sphk// String instructions. 39272786Srwatson// Packed Compare Implicit Length Strings, Return Mask 39372786Srwatsondef : WriteRes<WritePCmpIStrM, [SLM_FPC_RSV0]> { 39472786Srwatson let Latency = 13; 39572786Srwatson let ResourceCycles = [13]; 39672786Srwatson} 397114168Smikedef : WriteRes<WritePCmpIStrMLd, [SLM_FPC_RSV0, SLM_MEC_RSV]> { 39872786Srwatson let Latency = 13; 39972786Srwatson let ResourceCycles = [13, 1]; 40072786Srwatson} 40172786Srwatson 40272786Srwatson// Packed Compare Explicit Length Strings, Return Mask 40372786Srwatsondef : WriteRes<WritePCmpEStrM, [SLM_FPC_RSV0]> { 40472786Srwatson let Latency = 17; 40572786Srwatson let ResourceCycles = [17]; 40672786Srwatson} 40772786Srwatsondef : WriteRes<WritePCmpEStrMLd, [SLM_FPC_RSV0, SLM_MEC_RSV]> { 40872786Srwatson let Latency = 17; 40972786Srwatson let ResourceCycles = [17, 1]; 41072786Srwatson} 41172786Srwatson 41272786Srwatson// Packed Compare Implicit Length Strings, Return Index 41372786Srwatsondef : WriteRes<WritePCmpIStrI, [SLM_FPC_RSV0]> { 414114168Smike let Latency = 17; 41572786Srwatson let ResourceCycles = [17]; 41672786Srwatson} 41772786Srwatsondef : WriteRes<WritePCmpIStrILd, [SLM_FPC_RSV0, SLM_MEC_RSV]> { 41872786Srwatson let Latency = 17; 41991384Srobert let ResourceCycles = [17, 1]; 42091384Srobert} 42191384Srobert 42291384Srobert// Packed Compare Explicit Length Strings, Return Index 42391391Srobertdef : WriteRes<WritePCmpEStrI, [SLM_FPC_RSV0]> { 424114168Smike let Latency = 21; 42591384Srobert let ResourceCycles = [21]; 42691384Srobert} 42791391Srobertdef : WriteRes<WritePCmpEStrILd, [SLM_FPC_RSV0, SLM_MEC_RSV]> { 42891391Srobert let Latency = 21; 429105354Srobert let ResourceCycles = [21, 1]; 43091391Srobert} 431114168Smike 432105354Srobert// MOVMSK Instructions. 43391384Srobertdef : WriteRes<WriteFMOVMSK, [SLM_FPC_RSV1]> { let Latency = 4; } 434113275Smikedef : WriteRes<WriteVecMOVMSK, [SLM_FPC_RSV1]> { let Latency = 4; } 435125804Srwatsondef : WriteRes<WriteVecMOVMSKY, [SLM_FPC_RSV1]> { let Latency = 4; } 436147185Spjddef : WriteRes<WriteMMXMOVMSK, [SLM_FPC_RSV1]> { let Latency = 4; } 437147185Spjd 438147185Spjd// AES Instructions. 439147185Spjddef : WriteRes<WriteAESDecEnc, [SLM_FPC_RSV0]> { 440147185Spjd let Latency = 8; 441125804Srwatson let ResourceCycles = [5]; 442125804Srwatson} 443147185Spjddef : WriteRes<WriteAESDecEncLd, [SLM_FPC_RSV0, SLM_MEC_RSV]> { 444125804Srwatson let Latency = 8; 445147185Spjd let ResourceCycles = [5, 1]; 446147185Spjd} 447147185Spjd 448125804Srwatsondef : WriteRes<WriteAESIMC, [SLM_FPC_RSV0]> { 449147185Spjd let Latency = 8; 450147185Spjd let ResourceCycles = [5]; 451147185Spjd} 452147185Spjddef : WriteRes<WriteAESIMCLd, [SLM_FPC_RSV0, SLM_MEC_RSV]> { 453147185Spjd let Latency = 8; 454147185Spjd let ResourceCycles = [5, 1]; 455147185Spjd} 456147185Spjd 457147185Spjddef : WriteRes<WriteAESKeyGen, [SLM_FPC_RSV0]> { 458147185Spjd let Latency = 8; 459147185Spjd let ResourceCycles = [5]; 460147185Spjd} 461147185Spjddef : WriteRes<WriteAESKeyGenLd, [SLM_FPC_RSV0, SLM_MEC_RSV]> { 462147185Spjd let Latency = 8; 463147185Spjd let ResourceCycles = [5, 1]; 464147185Spjd} 465147185Spjd 466147185Spjd// Carry-less multiplication instructions. 467147185Spjddef : WriteRes<WriteCLMul, [SLM_FPC_RSV0]> { 468147185Spjd let Latency = 10; 469147185Spjd let ResourceCycles = [10]; 470147185Spjd} 471147185Spjddef : WriteRes<WriteCLMulLd, [SLM_FPC_RSV0, SLM_MEC_RSV]> { 472147185Spjd let Latency = 10; 473147185Spjd let ResourceCycles = [10, 1]; 474147185Spjd} 475147185Spjd 476147185Spjddef : WriteRes<WriteSystem, [SLM_FPC_RSV0]> { let Latency = 100; } 477147185Spjddef : WriteRes<WriteMicrocoded, [SLM_FPC_RSV0]> { let Latency = 100; } 478147185Spjddef : WriteRes<WriteFence, [SLM_MEC_RSV]>; 479147185Spjddef : WriteRes<WriteNop, []>; 480147185Spjd 481147185Spjd// AVX/FMA is not supported on that architecture, but we should define the basic 482147185Spjd// scheduling resources anyway. 483147185Spjddef : WriteRes<WriteIMulH, [SLM_FPC_RSV0]>; 484147185Spjddefm : X86WriteResPairUnsupported<WriteFBlendY>; 485147185Spjddefm : X86WriteResPairUnsupported<WriteFBlendZ>; 486147185Spjddefm : SLMWriteResPair<WriteVarBlend, [SLM_FPC_RSV0], 1>; 487147185Spjddefm : X86WriteResPairUnsupported<WriteVarBlendY>; 488147185Spjddefm : X86WriteResPairUnsupported<WriteVarBlendZ>; 489147185Spjddefm : SLMWriteResPair<WriteFVarBlend, [SLM_FPC_RSV0], 4, [4], 3>; 490147185Spjddefm : X86WriteResPairUnsupported<WriteFVarBlendY>; 491147185Spjddefm : X86WriteResPairUnsupported<WriteFVarBlendZ>; 492125804Srwatsondefm : X86WriteResPairUnsupported<WriteFShuffle256>; 493147185Spjddefm : X86WriteResPairUnsupported<WriteFVarShuffle256>; 494147185Spjddefm : X86WriteResPairUnsupported<WriteShuffle256>; 495147185Spjddefm : X86WriteResPairUnsupported<WriteVarShuffle256>; 496147185Spjddefm : SLMWriteResPair<WriteVarVecShift, [SLM_FPC_RSV0], 1>; 497147185Spjddefm : X86WriteResPairUnsupported<WriteVarVecShiftY>; 498147185Spjddefm : X86WriteResPairUnsupported<WriteVarVecShiftZ>; 499147185Spjddefm : X86WriteResPairUnsupported<WriteFMA>; 500147185Spjddefm : X86WriteResPairUnsupported<WriteFMAX>; 501147185Spjddefm : X86WriteResPairUnsupported<WriteFMAY>; 502147185Spjddefm : X86WriteResPairUnsupported<WriteFMAZ>; 503147185Spjd 504147185Spjddefm : X86WriteResPairUnsupported<WriteCvtPH2PS>; 505147185Spjddefm : X86WriteResPairUnsupported<WriteCvtPH2PSY>; 506147185Spjddefm : X86WriteResPairUnsupported<WriteCvtPH2PSZ>; 507147185Spjddefm : X86WriteResUnsupported<WriteCvtPS2PH>; 508147185Spjddefm : X86WriteResUnsupported<WriteCvtPS2PHY>; 509147185Spjddefm : X86WriteResUnsupported<WriteCvtPS2PHZ>; 510147185Spjddefm : X86WriteResUnsupported<WriteCvtPS2PHSt>; 511147185Spjddefm : X86WriteResUnsupported<WriteCvtPS2PHYSt>; 512147185Spjddefm : X86WriteResUnsupported<WriteCvtPS2PHZSt>; 513147185Spjd 514147185Spjd// Remaining SLM instrs. 515147185Spjd 516147185Spjddef SLMWriteResGroup1rr : SchedWriteRes<[SLM_FPC_RSV01]> { 517147185Spjd let Latency = 4; 518147185Spjd let NumMicroOps = 2; 519147185Spjd let ResourceCycles = [4]; 520147185Spjd} 521125804Srwatsondef: InstRW<[SLMWriteResGroup1rr], (instrs PADDQrr, PSUBQrr, PCMPEQQrr)>; 522125804Srwatson 523164032Srwatsondef SLMWriteResGroup1rm : SchedWriteRes<[SLM_MEC_RSV,SLM_FPC_RSV01]> { 524164032Srwatson let Latency = 7; 525164032Srwatson let NumMicroOps = 3; 526164032Srwatson let ResourceCycles = [1,4]; 527164032Srwatson} 528164032Srwatsondef: InstRW<[SLMWriteResGroup1rm], (instrs PADDQrm, PSUBQrm, PCMPEQQrm)>; 529164032Srwatson 530164032Srwatson} // SchedModel 531164032Srwatson