X86InstrSystem.td revision 360784
1184610Salfred//===-- X86InstrSystem.td - System Instructions ------------*- tablegen -*-===// 2184610Salfred// 3201705Sthompsa// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4184610Salfred// See https://llvm.org/LICENSE.txt for license information. 5184610Salfred// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6184610Salfred// 7184610Salfred//===----------------------------------------------------------------------===// 8184610Salfred// 9184610Salfred// This file describes the X86 instructions that are generally used in 10184610Salfred// privileged modes. These are not typically used by the compiler, but are 11184610Salfred// supported for the assembler and disassembler. 12184610Salfred// 13184610Salfred//===----------------------------------------------------------------------===// 14184610Salfred 15184610Salfredlet SchedRW = [WriteSystem] in { 16184610Salfredlet Defs = [RAX, RDX] in 17184610Salfreddef RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", []>, TB; 18184610Salfred 19184610Salfredlet Defs = [RAX, RCX, RDX] in 20184610Salfreddef RDTSCP : I<0x01, MRM_F9, (outs), (ins), "rdtscp", []>, TB; 21184610Salfred 22184610Salfred// CPU flow control instructions 23184610Salfred 24184610Salfredlet mayLoad = 1, mayStore = 0, hasSideEffects = 1, isTrap = 1 in { 25184610Salfred def TRAP : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB; 26184610Salfred def UD2B : I<0xB9, RawFrm, (outs), (ins), "ud2b", []>, TB; 27184610Salfred} 28184610Salfred 29184610Salfreddef HLT : I<0xF4, RawFrm, (outs), (ins), "hlt", []>; 30184610Salfreddef RSM : I<0xAA, RawFrm, (outs), (ins), "rsm", []>, TB; 31184610Salfred 32184610Salfred// Interrupt and SysCall Instructions. 33184610Salfredlet Uses = [EFLAGS] in 34184610Salfred def INTO : I<0xce, RawFrm, (outs), (ins), "into", []>, Requires<[Not64BitMode]>; 35185087Salfred 36184610Salfreddef INT3 : I<0xcc, RawFrm, (outs), (ins), "int3", [(int_x86_int (i8 3))]>; 37184610Salfred} // SchedRW 38184610Salfred 39184610Salfred// The long form of "int $3" turns into int3 as a size optimization. 40184610Salfred// FIXME: This doesn't work because InstAlias can't match immediate constants. 41184610Salfred//def : InstAlias<"int\t$3", (INT3)>; 42184610Salfred 43184610Salfredlet SchedRW = [WriteSystem] in { 44185087Salfred 45188987Sthompsadef INT : Ii8<0xcd, RawFrm, (outs), (ins u8imm:$trap), "int\t$trap", 46184610Salfred [(int_x86_int timm:$trap)]>; 47184610Salfred 48184610Salfred 49184610Salfreddef SYSCALL : I<0x05, RawFrm, (outs), (ins), "syscall", []>, TB; 50185087Salfreddef SYSRET : I<0x07, RawFrm, (outs), (ins), "sysret{l}", []>, TB; 51184610Salfreddef SYSRET64 :RI<0x07, RawFrm, (outs), (ins), "sysretq", []>, TB, 52184610Salfred Requires<[In64BitMode]>; 53184610Salfred 54184610Salfreddef SYSENTER : I<0x34, RawFrm, (outs), (ins), "sysenter", []>, TB; 55184610Salfred 56184610Salfreddef SYSEXIT : I<0x35, RawFrm, (outs), (ins), "sysexit{l}", []>, TB; 57184610Salfreddef SYSEXIT64 :RI<0x35, RawFrm, (outs), (ins), "sysexitq", []>, TB, 58185087Salfred Requires<[In64BitMode]>; 59184610Salfred} // SchedRW 60184610Salfred 61184610Salfreddef : Pat<(debugtrap), 62184610Salfred (INT3)>, Requires<[NotPS4]>; 63184610Salfreddef : Pat<(debugtrap), 64184610Salfred (INT (i8 0x41))>, Requires<[IsPS4]>; 65184610Salfred 66184610Salfred//===----------------------------------------------------------------------===// 67188987Sthompsa// Input/Output Instructions. 68188987Sthompsa// 69184610Salfredlet SchedRW = [WriteSystem] in { 70184610Salfredlet Defs = [AL], Uses = [DX] in 71184610Salfreddef IN8rr : I<0xEC, RawFrm, (outs), (ins), "in{b}\t{%dx, %al|al, dx}", []>; 72184610Salfredlet Defs = [AX], Uses = [DX] in 73184610Salfreddef IN16rr : I<0xED, RawFrm, (outs), (ins), "in{w}\t{%dx, %ax|ax, dx}", []>, 74184610Salfred OpSize16; 75184610Salfredlet Defs = [EAX], Uses = [DX] in 76184610Salfreddef IN32rr : I<0xED, RawFrm, (outs), (ins), "in{l}\t{%dx, %eax|eax, dx}", []>, 77184610Salfred OpSize32; 78184610Salfred 79184610Salfredlet Defs = [AL] in 80184610Salfreddef IN8ri : Ii8<0xE4, RawFrm, (outs), (ins u8imm:$port), 81188622Sthompsa "in{b}\t{$port, %al|al, $port}", []>; 82184610Salfredlet Defs = [AX] in 83184610Salfreddef IN16ri : Ii8<0xE5, RawFrm, (outs), (ins u8imm:$port), 84201705Sthompsa "in{w}\t{$port, %ax|ax, $port}", []>, OpSize16; 85201705Sthompsalet Defs = [EAX] in 86185087Salfreddef IN32ri : Ii8<0xE5, RawFrm, (outs), (ins u8imm:$port), 87185087Salfred "in{l}\t{$port, %eax|eax, $port}", []>, OpSize32; 88184610Salfred 89184610Salfredlet Uses = [DX, AL] in 90184610Salfreddef OUT8rr : I<0xEE, RawFrm, (outs), (ins), "out{b}\t{%al, %dx|dx, al}", []>; 91184610Salfredlet Uses = [DX, AX] in 92184610Salfreddef OUT16rr : I<0xEF, RawFrm, (outs), (ins), "out{w}\t{%ax, %dx|dx, ax}", []>, 93184610Salfred OpSize16; 94184610Salfredlet Uses = [DX, EAX] in 95184610Salfreddef OUT32rr : I<0xEF, RawFrm, (outs), (ins), "out{l}\t{%eax, %dx|dx, eax}", []>, 96184610Salfred OpSize32; 97184610Salfred 98184610Salfredlet Uses = [AL] in 99201705Sthompsadef OUT8ir : Ii8<0xE6, RawFrm, (outs), (ins u8imm:$port), 100184610Salfred "out{b}\t{%al, $port|$port, al}", []>; 101184610Salfredlet Uses = [AX] in 102184610Salfreddef OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins u8imm:$port), 103188987Sthompsa "out{w}\t{%ax, $port|$port, ax}", []>, OpSize16; 104188987Sthompsalet Uses = [EAX] in 105184610Salfreddef OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins u8imm:$port), 106184610Salfred "out{l}\t{%eax, $port|$port, eax}", []>, OpSize32; 107201705Sthompsa 108201705Sthompsa} // SchedRW 109188622Sthompsa 110184610Salfred//===----------------------------------------------------------------------===// 111184610Salfred// Moves to and from debug registers 112184610Salfred 113184610Salfredlet SchedRW = [WriteSystem] in { 114184610Salfreddef MOV32rd : I<0x21, MRMDestReg, (outs GR32:$dst), (ins DEBUG_REG:$src), 115185087Salfred "mov{l}\t{$src, $dst|$dst, $src}", []>, TB, 116184610Salfred Requires<[Not64BitMode]>; 117184610Salfreddef MOV64rd : I<0x21, MRMDestReg, (outs GR64:$dst), (ins DEBUG_REG:$src), 118184610Salfred "mov{q}\t{$src, $dst|$dst, $src}", []>, TB, 119184610Salfred Requires<[In64BitMode]>; 120184610Salfred 121184610Salfreddef MOV32dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR32:$src), 122184610Salfred "mov{l}\t{$src, $dst|$dst, $src}", []>, TB, 123184610Salfred Requires<[Not64BitMode]>; 124185087Salfreddef MOV64dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR64:$src), 125184610Salfred "mov{q}\t{$src, $dst|$dst, $src}", []>, TB, 126184610Salfred Requires<[In64BitMode]>; 127184610Salfred} // SchedRW 128184610Salfred 129184610Salfred//===----------------------------------------------------------------------===// 130184610Salfred// Moves to and from control registers 131184610Salfred 132201705Sthompsalet SchedRW = [WriteSystem] in { 133184610Salfreddef MOV32rc : I<0x20, MRMDestReg, (outs GR32:$dst), (ins CONTROL_REG:$src), 134184610Salfred "mov{l}\t{$src, $dst|$dst, $src}", []>, TB, 135184610Salfred Requires<[Not64BitMode]>; 136188987Sthompsadef MOV64rc : I<0x20, MRMDestReg, (outs GR64:$dst), (ins CONTROL_REG:$src), 137188987Sthompsa "mov{q}\t{$src, $dst|$dst, $src}", []>, TB, 138184610Salfred Requires<[In64BitMode]>; 139184610Salfred 140201705Sthompsadef MOV32cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR32:$src), 141201705Sthompsa "mov{l}\t{$src, $dst|$dst, $src}", []>, TB, 142184610Salfred Requires<[Not64BitMode]>; 143184610Salfreddef MOV64cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR64:$src), 144184610Salfred "mov{q}\t{$src, $dst|$dst, $src}", []>, TB, 145184610Salfred Requires<[In64BitMode]>; 146184610Salfred} // SchedRW 147185087Salfred 148184610Salfred//===----------------------------------------------------------------------===// 149188622Sthompsa// Segment override instruction prefixes 150184610Salfred 151184610Salfredlet SchedRW = [WriteNop] in { 152184610Salfreddef CS_PREFIX : I<0x2E, RawFrm, (outs), (ins), "cs", []>; 153184610Salfreddef SS_PREFIX : I<0x36, RawFrm, (outs), (ins), "ss", []>; 154184610Salfreddef DS_PREFIX : I<0x3E, RawFrm, (outs), (ins), "ds", []>; 155184610Salfreddef ES_PREFIX : I<0x26, RawFrm, (outs), (ins), "es", []>; 156184610Salfreddef FS_PREFIX : I<0x64, RawFrm, (outs), (ins), "fs", []>; 157185087Salfreddef GS_PREFIX : I<0x65, RawFrm, (outs), (ins), "gs", []>; 158184610Salfred} // SchedRW 159184610Salfred 160184610Salfred//===----------------------------------------------------------------------===// 161184610Salfred// Moves to and from segment registers. 162184610Salfred// 163184610Salfred 164184610Salfredlet SchedRW = [WriteMove] in { 165184610Salfreddef MOV16rs : I<0x8C, MRMDestReg, (outs GR16:$dst), (ins SEGMENT_REG:$src), 166185087Salfred "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize16; 167184610Salfreddef MOV32rs : I<0x8C, MRMDestReg, (outs GR32:$dst), (ins SEGMENT_REG:$src), 168184610Salfred "mov{l}\t{$src, $dst|$dst, $src}", []>, OpSize32; 169184610Salfreddef MOV64rs : RI<0x8C, MRMDestReg, (outs GR64:$dst), (ins SEGMENT_REG:$src), 170184610Salfred "mov{q}\t{$src, $dst|$dst, $src}", []>; 171184610Salfredlet mayStore = 1 in { 172184610Salfreddef MOV16ms : I<0x8C, MRMDestMem, (outs), (ins i16mem:$dst, SEGMENT_REG:$src), 173184610Salfred "mov{w}\t{$src, $dst|$dst, $src}", []>; 174184610Salfred} 175184610Salfreddef MOV16sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR16:$src), 176185087Salfred "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize16; 177185087Salfreddef MOV32sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR32:$src), 178184610Salfred "mov{l}\t{$src, $dst|$dst, $src}", []>, OpSize32; 179184610Salfreddef MOV64sr : RI<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR64:$src), 180184610Salfred "mov{q}\t{$src, $dst|$dst, $src}", []>; 181184610Salfredlet mayLoad = 1 in { 182184610Salfreddef MOV16sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i16mem:$src), 183184610Salfred "mov{w}\t{$src, $dst|$dst, $src}", []>; 184184610Salfred} 185184610Salfred} // SchedRW 186184610Salfred 187184610Salfred//===----------------------------------------------------------------------===// 188184610Salfred// Segmentation support instructions. 189185087Salfred 190184610Salfredlet SchedRW = [WriteSystem] in { 191184610Salfreddef SWAPGS : I<0x01, MRM_F8, (outs), (ins), "swapgs", []>, TB; 192184610Salfred 193184610Salfredlet mayLoad = 1 in 194184610Salfreddef LAR16rm : I<0x02, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 195184610Salfred "lar{w}\t{$src, $dst|$dst, $src}", []>, TB, 196184610Salfred OpSize16, NotMemoryFoldable; 197184610Salfreddef LAR16rr : I<0x02, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), 198184610Salfred "lar{w}\t{$src, $dst|$dst, $src}", []>, TB, 199185087Salfred OpSize16, NotMemoryFoldable; 200185087Salfred 201184610Salfred// i16mem operand in LAR32rm and GR32 operand in LAR32rr is not a typo. 202184610Salfredlet mayLoad = 1 in 203184610Salfreddef LAR32rm : I<0x02, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src), 204184610Salfred "lar{l}\t{$src, $dst|$dst, $src}", []>, TB, 205184610Salfred OpSize32, NotMemoryFoldable; 206184610Salfreddef LAR32rr : I<0x02, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), 207184610Salfred "lar{l}\t{$src, $dst|$dst, $src}", []>, TB, 208184610Salfred OpSize32, NotMemoryFoldable; 209184610Salfred// i16mem operand in LAR64rm and GR32 operand in LAR64rr is not a typo. 210184610Salfredlet mayLoad = 1 in 211184610Salfreddef LAR64rm : RI<0x02, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src), 212184610Salfred "lar{q}\t{$src, $dst|$dst, $src}", []>, TB, NotMemoryFoldable; 213184610Salfreddef LAR64rr : RI<0x02, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src), 214185087Salfred "lar{q}\t{$src, $dst|$dst, $src}", []>, TB, NotMemoryFoldable; 215184610Salfred 216184610Salfred// i16mem operand in LSL32rm and GR32 operand in LSL32rr is not a typo. 217184610Salfredlet mayLoad = 1 in 218184610Salfreddef LSL16rm : I<0x03, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 219184610Salfred "lsl{w}\t{$src, $dst|$dst, $src}", []>, TB, 220184610Salfred OpSize16, NotMemoryFoldable; 221184610Salfreddef LSL16rr : I<0x03, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), 222184610Salfred "lsl{w}\t{$src, $dst|$dst, $src}", []>, TB, 223184610Salfred OpSize16, NotMemoryFoldable; 224184610Salfred// i16mem operand in LSL64rm and GR32 operand in LSL64rr is not a typo. 225184610Salfredlet mayLoad = 1 in 226184610Salfreddef LSL32rm : I<0x03, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src), 227184610Salfred "lsl{l}\t{$src, $dst|$dst, $src}", []>, TB, 228184610Salfred OpSize32, NotMemoryFoldable; 229184610Salfreddef LSL32rr : I<0x03, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), 230184610Salfred "lsl{l}\t{$src, $dst|$dst, $src}", []>, TB, 231184610Salfred OpSize32, NotMemoryFoldable; 232184610Salfredlet mayLoad = 1 in 233184610Salfreddef LSL64rm : RI<0x03, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src), 234184610Salfred "lsl{q}\t{$src, $dst|$dst, $src}", []>, TB, NotMemoryFoldable; 235184610Salfreddef LSL64rr : RI<0x03, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src), 236184610Salfred "lsl{q}\t{$src, $dst|$dst, $src}", []>, TB, NotMemoryFoldable; 237184610Salfred 238184610Salfreddef INVLPG : I<0x01, MRM7m, (outs), (ins i8mem:$addr), "invlpg\t$addr", []>, TB; 239184610Salfred 240189110Sthompsadef STR16r : I<0x00, MRM1r, (outs GR16:$dst), (ins), 241189110Sthompsa "str{w}\t$dst", []>, TB, OpSize16; 242184610Salfreddef STR32r : I<0x00, MRM1r, (outs GR32:$dst), (ins), 243189110Sthompsa "str{l}\t$dst", []>, TB, OpSize32; 244184610Salfreddef STR64r : RI<0x00, MRM1r, (outs GR64:$dst), (ins), 245184610Salfred "str{q}\t$dst", []>, TB; 246184610Salfredlet mayStore = 1 in 247189110Sthompsadef STRm : I<0x00, MRM1m, (outs), (ins i16mem:$dst), "str{w}\t$dst", []>, TB; 248184610Salfred 249184610Salfreddef LTRr : I<0x00, MRM3r, (outs), (ins GR16:$src), "ltr{w}\t$src", []>, TB, NotMemoryFoldable; 250184610Salfredlet mayLoad = 1 in 251184610Salfreddef LTRm : I<0x00, MRM3m, (outs), (ins i16mem:$src), "ltr{w}\t$src", []>, TB, NotMemoryFoldable; 252189110Sthompsa 253184610Salfreddef PUSHCS16 : I<0x0E, RawFrm, (outs), (ins), "push{w}\t{%cs|cs}", []>, 254184610Salfred OpSize16, Requires<[Not64BitMode]>; 255184610Salfreddef PUSHCS32 : I<0x0E, RawFrm, (outs), (ins), "push{l}\t{%cs|cs}", []>, 256184610Salfred OpSize32, Requires<[Not64BitMode]>; 257184610Salfreddef PUSHSS16 : I<0x16, RawFrm, (outs), (ins), "push{w}\t{%ss|ss}", []>, 258201705Sthompsa OpSize16, Requires<[Not64BitMode]>; 259201705Sthompsadef PUSHSS32 : I<0x16, RawFrm, (outs), (ins), "push{l}\t{%ss|ss}", []>, 260201705Sthompsa OpSize32, Requires<[Not64BitMode]>; 261201705Sthompsadef PUSHDS16 : I<0x1E, RawFrm, (outs), (ins), "push{w}\t{%ds|ds}", []>, 262201705Sthompsa OpSize16, Requires<[Not64BitMode]>; 263201705Sthompsadef PUSHDS32 : I<0x1E, RawFrm, (outs), (ins), "push{l}\t{%ds|ds}", []>, 264201705Sthompsa OpSize32, Requires<[Not64BitMode]>; 265201705Sthompsadef PUSHES16 : I<0x06, RawFrm, (outs), (ins), "push{w}\t{%es|es}", []>, 266184610Salfred OpSize16, Requires<[Not64BitMode]>; 267184610Salfreddef PUSHES32 : I<0x06, RawFrm, (outs), (ins), "push{l}\t{%es|es}", []>, 268184610Salfred OpSize32, Requires<[Not64BitMode]>; 269184610Salfreddef PUSHFS16 : I<0xa0, RawFrm, (outs), (ins), "push{w}\t{%fs|fs}", []>, 270184610Salfred OpSize16, TB; 271201705Sthompsadef PUSHFS32 : I<0xa0, RawFrm, (outs), (ins), "push{l}\t{%fs|fs}", []>, TB, 272184610Salfred OpSize32, Requires<[Not64BitMode]>; 273185087Salfreddef PUSHGS16 : I<0xa8, RawFrm, (outs), (ins), "push{w}\t{%gs|gs}", []>, 274185087Salfred OpSize16, TB; 275188987Sthompsadef PUSHGS32 : I<0xa8, RawFrm, (outs), (ins), "push{l}\t{%gs|gs}", []>, TB, 276188987Sthompsa OpSize32, Requires<[Not64BitMode]>; 277184610Salfreddef PUSHFS64 : I<0xa0, RawFrm, (outs), (ins), "push{q}\t{%fs|fs}", []>, TB, 278184610Salfred OpSize32, Requires<[In64BitMode]>; 279201705Sthompsadef PUSHGS64 : I<0xa8, RawFrm, (outs), (ins), "push{q}\t{%gs|gs}", []>, TB, 280201705Sthompsa OpSize32, Requires<[In64BitMode]>; 281184610Salfred 282184610Salfred// No "pop cs" instruction. 283184610Salfreddef POPSS16 : I<0x17, RawFrm, (outs), (ins), "pop{w}\t{%ss|ss}", []>, 284184610Salfred OpSize16, Requires<[Not64BitMode]>; 285184610Salfreddef POPSS32 : I<0x17, RawFrm, (outs), (ins), "pop{l}\t{%ss|ss}", []>, 286185087Salfred OpSize32, Requires<[Not64BitMode]>; 287184610Salfred 288188622Sthompsadef POPDS16 : I<0x1F, RawFrm, (outs), (ins), "pop{w}\t{%ds|ds}", []>, 289184610Salfred OpSize16, Requires<[Not64BitMode]>; 290184610Salfreddef POPDS32 : I<0x1F, RawFrm, (outs), (ins), "pop{l}\t{%ds|ds}", []>, 291184610Salfred OpSize32, Requires<[Not64BitMode]>; 292184610Salfred 293184610Salfreddef POPES16 : I<0x07, RawFrm, (outs), (ins), "pop{w}\t{%es|es}", []>, 294184610Salfred OpSize16, Requires<[Not64BitMode]>; 295184610Salfreddef POPES32 : I<0x07, RawFrm, (outs), (ins), "pop{l}\t{%es|es}", []>, 296185087Salfred OpSize32, Requires<[Not64BitMode]>; 297184610Salfred 298184610Salfreddef POPFS16 : I<0xa1, RawFrm, (outs), (ins), "pop{w}\t{%fs|fs}", []>, 299184610Salfred OpSize16, TB; 300184610Salfreddef POPFS32 : I<0xa1, RawFrm, (outs), (ins), "pop{l}\t{%fs|fs}", []>, TB, 301184610Salfred OpSize32, Requires<[Not64BitMode]>; 302184610Salfreddef POPFS64 : I<0xa1, RawFrm, (outs), (ins), "pop{q}\t{%fs|fs}", []>, TB, 303184610Salfred OpSize32, Requires<[In64BitMode]>; 304185087Salfred 305185087Salfreddef POPGS16 : I<0xa9, RawFrm, (outs), (ins), "pop{w}\t{%gs|gs}", []>, 306184610Salfred OpSize16, TB; 307184610Salfreddef POPGS32 : I<0xa9, RawFrm, (outs), (ins), "pop{l}\t{%gs|gs}", []>, TB, 308184610Salfred OpSize32, Requires<[Not64BitMode]>; 309184610Salfreddef POPGS64 : I<0xa9, RawFrm, (outs), (ins), "pop{q}\t{%gs|gs}", []>, TB, 310184610Salfred OpSize32, Requires<[In64BitMode]>; 311184610Salfred 312184610Salfreddef LDS16rm : I<0xc5, MRMSrcMem, (outs GR16:$dst), (ins opaquemem:$src), 313184610Salfred "lds{w}\t{$src, $dst|$dst, $src}", []>, OpSize16, 314184610Salfred Requires<[Not64BitMode]>; 315184610Salfreddef LDS32rm : I<0xc5, MRMSrcMem, (outs GR32:$dst), (ins opaquemem:$src), 316184610Salfred "lds{l}\t{$src, $dst|$dst, $src}", []>, OpSize32, 317184610Salfred Requires<[Not64BitMode]>; 318184610Salfred 319184610Salfreddef LSS16rm : I<0xb2, MRMSrcMem, (outs GR16:$dst), (ins opaquemem:$src), 320184610Salfred "lss{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize16; 321184610Salfreddef LSS32rm : I<0xb2, MRMSrcMem, (outs GR32:$dst), (ins opaquemem:$src), 322184610Salfred "lss{l}\t{$src, $dst|$dst, $src}", []>, TB, OpSize32; 323184610Salfreddef LSS64rm : RI<0xb2, MRMSrcMem, (outs GR64:$dst), (ins opaquemem:$src), 324184610Salfred "lss{q}\t{$src, $dst|$dst, $src}", []>, TB; 325184610Salfred 326187168Sthompsadef LES16rm : I<0xc4, MRMSrcMem, (outs GR16:$dst), (ins opaquemem:$src), 327184610Salfred "les{w}\t{$src, $dst|$dst, $src}", []>, OpSize16, 328184610Salfred Requires<[Not64BitMode]>; 329184610Salfreddef LES32rm : I<0xc4, MRMSrcMem, (outs GR32:$dst), (ins opaquemem:$src), 330184610Salfred "les{l}\t{$src, $dst|$dst, $src}", []>, OpSize32, 331184610Salfred Requires<[Not64BitMode]>; 332184610Salfred 333184610Salfreddef LFS16rm : I<0xb4, MRMSrcMem, (outs GR16:$dst), (ins opaquemem:$src), 334184610Salfred "lfs{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize16; 335184610Salfreddef LFS32rm : I<0xb4, MRMSrcMem, (outs GR32:$dst), (ins opaquemem:$src), 336184610Salfred "lfs{l}\t{$src, $dst|$dst, $src}", []>, TB, OpSize32; 337184610Salfreddef LFS64rm : RI<0xb4, MRMSrcMem, (outs GR64:$dst), (ins opaquemem:$src), 338184610Salfred "lfs{q}\t{$src, $dst|$dst, $src}", []>, TB; 339184610Salfred 340184610Salfreddef LGS16rm : I<0xb5, MRMSrcMem, (outs GR16:$dst), (ins opaquemem:$src), 341184610Salfred "lgs{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize16; 342184610Salfreddef LGS32rm : I<0xb5, MRMSrcMem, (outs GR32:$dst), (ins opaquemem:$src), 343184610Salfred "lgs{l}\t{$src, $dst|$dst, $src}", []>, TB, OpSize32; 344184610Salfred 345184610Salfreddef LGS64rm : RI<0xb5, MRMSrcMem, (outs GR64:$dst), (ins opaquemem:$src), 346184610Salfred "lgs{q}\t{$src, $dst|$dst, $src}", []>, TB; 347184610Salfred 348184610Salfreddef VERRr : I<0x00, MRM4r, (outs), (ins GR16:$seg), "verr\t$seg", []>, TB, NotMemoryFoldable; 349188987Sthompsadef VERWr : I<0x00, MRM5r, (outs), (ins GR16:$seg), "verw\t$seg", []>, TB, NotMemoryFoldable; 350188987Sthompsalet mayLoad = 1 in { 351188987Sthompsadef VERRm : I<0x00, MRM4m, (outs), (ins i16mem:$seg), "verr\t$seg", []>, TB, NotMemoryFoldable; 352188987Sthompsadef VERWm : I<0x00, MRM5m, (outs), (ins i16mem:$seg), "verw\t$seg", []>, TB, NotMemoryFoldable; 353188987Sthompsa} 354188987Sthompsa} // SchedRW 355188987Sthompsa 356188987Sthompsa//===----------------------------------------------------------------------===// 357188987Sthompsa// Descriptor-table support instructions 358188987Sthompsa 359188987Sthompsalet SchedRW = [WriteSystem] in { 360188987Sthompsadef SGDT16m : I<0x01, MRM0m, (outs), (ins opaquemem:$dst), 361188987Sthompsa "sgdtw\t$dst", []>, TB, OpSize16, Requires<[Not64BitMode]>; 362188987Sthompsadef SGDT32m : I<0x01, MRM0m, (outs), (ins opaquemem:$dst), 363184610Salfred "sgdt{l|d}\t$dst", []>, OpSize32, TB, Requires <[Not64BitMode]>; 364184610Salfreddef SGDT64m : I<0x01, MRM0m, (outs), (ins opaquemem:$dst), 365184610Salfred "sgdt{q}\t$dst", []>, TB, Requires <[In64BitMode]>; 366184610Salfreddef SIDT16m : I<0x01, MRM1m, (outs), (ins opaquemem:$dst), 367184610Salfred "sidtw\t$dst", []>, TB, OpSize16, Requires<[Not64BitMode]>; 368184610Salfreddef SIDT32m : I<0x01, MRM1m, (outs), (ins opaquemem:$dst), 369184610Salfred "sidt{l|d}\t$dst", []>, OpSize32, TB, Requires <[Not64BitMode]>; 370184610Salfreddef SIDT64m : I<0x01, MRM1m, (outs), (ins opaquemem:$dst), 371184610Salfred "sidt{q}\t$dst", []>, TB, Requires <[In64BitMode]>; 372184610Salfreddef SLDT16r : I<0x00, MRM0r, (outs GR16:$dst), (ins), 373184610Salfred "sldt{w}\t$dst", []>, TB, OpSize16; 374184610Salfredlet mayStore = 1 in 375184610Salfreddef SLDT16m : I<0x00, MRM0m, (outs), (ins i16mem:$dst), 376184610Salfred "sldt{w}\t$dst", []>, TB; 377184610Salfreddef SLDT32r : I<0x00, MRM0r, (outs GR32:$dst), (ins), 378184610Salfred "sldt{l}\t$dst", []>, OpSize32, TB; 379184610Salfred 380184610Salfred// LLDT is not interpreted specially in 64-bit mode because there is no sign 381184610Salfred// extension. 382201705Sthompsadef SLDT64r : RI<0x00, MRM0r, (outs GR64:$dst), (ins), 383201705Sthompsa "sldt{q}\t$dst", []>, TB, Requires<[In64BitMode]>; 384201705Sthompsa 385201705Sthompsadef LGDT16m : I<0x01, MRM2m, (outs), (ins opaquemem:$src), 386201705Sthompsa "lgdtw\t$src", []>, TB, OpSize16, Requires<[Not64BitMode]>; 387201705Sthompsadef LGDT32m : I<0x01, MRM2m, (outs), (ins opaquemem:$src), 388201705Sthompsa "lgdt{l|d}\t$src", []>, OpSize32, TB, Requires<[Not64BitMode]>; 389201705Sthompsadef LGDT64m : I<0x01, MRM2m, (outs), (ins opaquemem:$src), 390201705Sthompsa "lgdt{q}\t$src", []>, TB, Requires<[In64BitMode]>; 391201705Sthompsadef LIDT16m : I<0x01, MRM3m, (outs), (ins opaquemem:$src), 392201705Sthompsa "lidtw\t$src", []>, TB, OpSize16, Requires<[Not64BitMode]>; 393201705Sthompsadef LIDT32m : I<0x01, MRM3m, (outs), (ins opaquemem:$src), 394201705Sthompsa "lidt{l|d}\t$src", []>, OpSize32, TB, Requires<[Not64BitMode]>; 395201705Sthompsadef LIDT64m : I<0x01, MRM3m, (outs), (ins opaquemem:$src), 396201705Sthompsa "lidt{q}\t$src", []>, TB, Requires<[In64BitMode]>; 397201705Sthompsadef LLDT16r : I<0x00, MRM2r, (outs), (ins GR16:$src), 398201705Sthompsa "lldt{w}\t$src", []>, TB, NotMemoryFoldable; 399201705Sthompsalet mayLoad = 1 in 400201705Sthompsadef LLDT16m : I<0x00, MRM2m, (outs), (ins i16mem:$src), 401201705Sthompsa "lldt{w}\t$src", []>, TB, NotMemoryFoldable; 402201705Sthompsa} // SchedRW 403201705Sthompsa 404184610Salfred//===----------------------------------------------------------------------===// 405184610Salfred// Specialized register support 406184610Salfredlet SchedRW = [WriteSystem] in { 407185087Salfredlet Uses = [EAX, ECX, EDX] in 408201705Sthompsadef WRMSR : I<0x30, RawFrm, (outs), (ins), "wrmsr", []>, TB; 409185087Salfredlet Defs = [EAX, EDX], Uses = [ECX] in 410185087Salfreddef RDMSR : I<0x32, RawFrm, (outs), (ins), "rdmsr", []>, TB; 411185087Salfred 412185087Salfredlet Defs = [RAX, RDX], Uses = [ECX] in 413185087Salfreddef RDPMC : I<0x33, RawFrm, (outs), (ins), "rdpmc", []>, TB; 414185087Salfred 415185087Salfreddef SMSW16r : I<0x01, MRM4r, (outs GR16:$dst), (ins), 416185087Salfred "smsw{w}\t$dst", []>, OpSize16, TB; 417185087Salfreddef SMSW32r : I<0x01, MRM4r, (outs GR32:$dst), (ins), 418185087Salfred "smsw{l}\t$dst", []>, OpSize32, TB; 419185087Salfred// no m form encodable; use SMSW16m 420185087Salfreddef SMSW64r : RI<0x01, MRM4r, (outs GR64:$dst), (ins), 421185087Salfred "smsw{q}\t$dst", []>, TB; 422185087Salfred 423185087Salfred// For memory operands, there is only a 16-bit form 424185087Salfreddef SMSW16m : I<0x01, MRM4m, (outs), (ins i16mem:$dst), 425185087Salfred "smsw{w}\t$dst", []>, TB; 426185087Salfred 427185087Salfreddef LMSW16r : I<0x01, MRM6r, (outs), (ins GR16:$src), 428185087Salfred "lmsw{w}\t$src", []>, TB, NotMemoryFoldable; 429185087Salfredlet mayLoad = 1 in 430185087Salfreddef LMSW16m : I<0x01, MRM6m, (outs), (ins i16mem:$src), 431185087Salfred "lmsw{w}\t$src", []>, TB, NotMemoryFoldable; 432185087Salfred 433185087Salfredlet Defs = [EAX, EBX, ECX, EDX], Uses = [EAX, ECX] in 434185087Salfred def CPUID : I<0xA2, RawFrm, (outs), (ins), "cpuid", []>, TB; 435185087Salfred} // SchedRW 436185087Salfred 437185087Salfred//===----------------------------------------------------------------------===// 438185087Salfred// Cache instructions 439185087Salfredlet SchedRW = [WriteSystem] in { 440185087Salfreddef INVD : I<0x08, RawFrm, (outs), (ins), "invd", []>, TB; 441184610Salfreddef WBINVD : I<0x09, RawFrm, (outs), (ins), "wbinvd", [(int_x86_wbinvd)]>, TB; 442184610Salfred 443184610Salfred// wbnoinvd is like wbinvd, except without invalidation 444184610Salfred// encoding: like wbinvd + an 0xF3 prefix 445184610Salfreddef WBNOINVD : I<0x09, RawFrm, (outs), (ins), "wbnoinvd", 446184610Salfred [(int_x86_wbnoinvd)]>, XS, 447184610Salfred Requires<[HasWBNOINVD]>; 448185087Salfred} // SchedRW 449185087Salfred 450184610Salfred//===----------------------------------------------------------------------===// 451184610Salfred// CET instructions 452184610Salfred// Use with caution, availability is not predicated on features. 453184610Salfredlet SchedRW = [WriteSystem] in { 454184610Salfred let Uses = [SSP] in { 455184610Salfred let Defs = [SSP] in { 456184610Salfred def INCSSPD : I<0xAE, MRM5r, (outs), (ins GR32:$src), "incsspd\t$src", 457184610Salfred [(int_x86_incsspd GR32:$src)]>, XS; 458184610Salfred def INCSSPQ : RI<0xAE, MRM5r, (outs), (ins GR64:$src), "incsspq\t$src", 459185087Salfred [(int_x86_incsspq GR64:$src)]>, XS; 460185087Salfred } // Defs SSP 461184610Salfred 462184610Salfred let Constraints = "$src = $dst" in { 463184610Salfred def RDSSPD : I<0x1E, MRM1r, (outs GR32:$dst), (ins GR32:$src), 464184610Salfred "rdsspd\t$dst", 465185087Salfred [(set GR32:$dst, (int_x86_rdsspd GR32:$src))]>, XS; 466185087Salfred def RDSSPQ : RI<0x1E, MRM1r, (outs GR64:$dst), (ins GR64:$src), 467184610Salfred "rdsspq\t$dst", 468184610Salfred [(set GR64:$dst, (int_x86_rdsspq GR64:$src))]>, XS; 469184610Salfred } 470184610Salfred 471185087Salfred let Defs = [SSP] in { 472185087Salfred def SAVEPREVSSP : I<0x01, MRM_EA, (outs), (ins), "saveprevssp", 473184610Salfred [(int_x86_saveprevssp)]>, XS; 474184610Salfred def RSTORSSP : I<0x01, MRM5m, (outs), (ins i32mem:$src), 475184610Salfred "rstorssp\t$src", 476184610Salfred [(int_x86_rstorssp addr:$src)]>, XS; 477185087Salfred } // Defs SSP 478185087Salfred } // Uses SSP 479184610Salfred 480184610Salfred def WRSSD : I<0xF6, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), 481184610Salfred "wrssd\t{$src, $dst|$dst, $src}", 482184610Salfred [(int_x86_wrssd GR32:$src, addr:$dst)]>, T8PS; 483185087Salfred def WRSSQ : RI<0xF6, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), 484185087Salfred "wrssq\t{$src, $dst|$dst, $src}", 485184610Salfred [(int_x86_wrssq GR64:$src, addr:$dst)]>, T8PS; 486184610Salfred def WRUSSD : I<0xF5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), 487184610Salfred "wrussd\t{$src, $dst|$dst, $src}", 488184610Salfred [(int_x86_wrussd GR32:$src, addr:$dst)]>, T8PD; 489184610Salfred def WRUSSQ : RI<0xF5, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), 490184610Salfred "wrussq\t{$src, $dst|$dst, $src}", 491184610Salfred [(int_x86_wrussq GR64:$src, addr:$dst)]>, T8PD; 492189110Sthompsa 493184610Salfred let Defs = [SSP] in { 494184610Salfred let Uses = [SSP] in { 495188622Sthompsa def SETSSBSY : I<0x01, MRM_E8, (outs), (ins), "setssbsy", 496188622Sthompsa [(int_x86_setssbsy)]>, XS; 497184610Salfred } // Uses SSP 498184610Salfred 499184610Salfred def CLRSSBSY : I<0xAE, MRM6m, (outs), (ins i32mem:$src), 500184610Salfred "clrssbsy\t$src", 501184610Salfred [(int_x86_clrssbsy addr:$src)]>, XS; 502184610Salfred } // Defs SSP 503184610Salfred} // SchedRW 504184610Salfred 505184610Salfredlet SchedRW = [WriteSystem] in { 506184610Salfred def ENDBR64 : I<0x1E, MRM_FA, (outs), (ins), "endbr64", []>, XS; 507184610Salfred def ENDBR32 : I<0x1E, MRM_FB, (outs), (ins), "endbr32", []>, XS; 508184610Salfred} // SchedRW 509184610Salfred 510184610Salfred//===----------------------------------------------------------------------===// 511184610Salfred// XSAVE instructions 512184610Salfredlet SchedRW = [WriteSystem] in { 513184610Salfredlet Predicates = [HasXSAVE] in { 514184610Salfredlet Defs = [EDX, EAX], Uses = [ECX] in 515184610Salfred def XGETBV : I<0x01, MRM_D0, (outs), (ins), "xgetbv", []>, TB; 516184610Salfred 517184610Salfredlet Uses = [EDX, EAX, ECX] in 518187162Sthompsa def XSETBV : I<0x01, MRM_D1, (outs), (ins), 519184610Salfred "xsetbv", 520184610Salfred [(int_x86_xsetbv ECX, EDX, EAX)]>, TB; 521184610Salfred 522184610Salfred} // HasXSAVE 523184610Salfred 524184610Salfredlet Uses = [EDX, EAX] in { 525184610Salfreddef XSAVE : I<0xAE, MRM4m, (outs), (ins opaquemem:$dst), 526184610Salfred "xsave\t$dst", 527184610Salfred [(int_x86_xsave addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVE]>; 528184610Salfreddef XSAVE64 : RI<0xAE, MRM4m, (outs), (ins opaquemem:$dst), 529184610Salfred "xsave64\t$dst", 530184610Salfred [(int_x86_xsave64 addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVE, In64BitMode]>; 531201705Sthompsadef XRSTOR : I<0xAE, MRM5m, (outs), (ins opaquemem:$dst), 532201705Sthompsa "xrstor\t$dst", 533201705Sthompsa [(int_x86_xrstor addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVE]>; 534184610Salfreddef XRSTOR64 : RI<0xAE, MRM5m, (outs), (ins opaquemem:$dst), 535184610Salfred "xrstor64\t$dst", 536184610Salfred [(int_x86_xrstor64 addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVE, In64BitMode]>; 537184610Salfreddef XSAVEOPT : I<0xAE, MRM6m, (outs), (ins opaquemem:$dst), 538184610Salfred "xsaveopt\t$dst", 539184610Salfred [(int_x86_xsaveopt addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVEOPT]>; 540184610Salfreddef XSAVEOPT64 : RI<0xAE, MRM6m, (outs), (ins opaquemem:$dst), 541184610Salfred "xsaveopt64\t$dst", 542184610Salfred [(int_x86_xsaveopt64 addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVEOPT, In64BitMode]>; 543184610Salfreddef XSAVEC : I<0xC7, MRM4m, (outs), (ins opaquemem:$dst), 544184610Salfred "xsavec\t$dst", 545184610Salfred [(int_x86_xsavec addr:$dst, EDX, EAX)]>, TB, Requires<[HasXSAVEC]>; 546184610Salfreddef XSAVEC64 : RI<0xC7, MRM4m, (outs), (ins opaquemem:$dst), 547184610Salfred "xsavec64\t$dst", 548184610Salfred [(int_x86_xsavec64 addr:$dst, EDX, EAX)]>, TB, Requires<[HasXSAVEC, In64BitMode]>; 549184610Salfreddef XSAVES : I<0xC7, MRM5m, (outs), (ins opaquemem:$dst), 550184610Salfred "xsaves\t$dst", 551201705Sthompsa [(int_x86_xsaves addr:$dst, EDX, EAX)]>, TB, Requires<[HasXSAVES]>; 552201705Sthompsadef XSAVES64 : RI<0xC7, MRM5m, (outs), (ins opaquemem:$dst), 553201705Sthompsa "xsaves64\t$dst", 554201705Sthompsa [(int_x86_xsaves64 addr:$dst, EDX, EAX)]>, TB, Requires<[HasXSAVE, In64BitMode]>; 555201705Sthompsadef XRSTORS : I<0xC7, MRM3m, (outs), (ins opaquemem:$dst), 556201705Sthompsa "xrstors\t$dst", 557201705Sthompsa [(int_x86_xrstors addr:$dst, EDX, EAX)]>, TB, Requires<[HasXSAVES]>; 558201705Sthompsadef XRSTORS64 : RI<0xC7, MRM3m, (outs), (ins opaquemem:$dst), 559201705Sthompsa "xrstors64\t$dst", 560201705Sthompsa [(int_x86_xrstors64 addr:$dst, EDX, EAX)]>, TB, Requires<[HasXSAVES, In64BitMode]>; 561201705Sthompsa} // Uses 562201705Sthompsa} // SchedRW 563201705Sthompsa 564201705Sthompsa//===----------------------------------------------------------------------===// 565201705Sthompsa// VIA PadLock crypto instructions 566201705Sthompsalet Defs = [RAX, RDI], Uses = [RDX, RDI], SchedRW = [WriteSystem] in 567201705Sthompsa def XSTORE : I<0xa7, MRM_C0, (outs), (ins), "xstore", []>, TB; 568201705Sthompsa 569201705Sthompsadef : InstAlias<"xstorerng", (XSTORE)>; 570201705Sthompsa 571201705Sthompsalet SchedRW = [WriteSystem] in { 572201705Sthompsalet Defs = [RSI, RDI], Uses = [RBX, RDX, RSI, RDI] in { 573184610Salfred def XCRYPTECB : I<0xa7, MRM_C8, (outs), (ins), "xcryptecb", []>, TB; 574184610Salfred def XCRYPTCBC : I<0xa7, MRM_D0, (outs), (ins), "xcryptcbc", []>, TB; 575184610Salfred def XCRYPTCTR : I<0xa7, MRM_D8, (outs), (ins), "xcryptctr", []>, TB; 576184610Salfred def XCRYPTCFB : I<0xa7, MRM_E0, (outs), (ins), "xcryptcfb", []>, TB; 577184610Salfred def XCRYPTOFB : I<0xa7, MRM_E8, (outs), (ins), "xcryptofb", []>, TB; 578184610Salfred} 579184610Salfred 580184610Salfredlet Defs = [RAX, RSI, RDI], Uses = [RAX, RSI, RDI] in { 581184610Salfred def XSHA1 : I<0xa6, MRM_C8, (outs), (ins), "xsha1", []>, TB; 582184610Salfred def XSHA256 : I<0xa6, MRM_D0, (outs), (ins), "xsha256", []>, TB; 583184610Salfred} 584184610Salfredlet Defs = [RAX, RDX, RSI], Uses = [RAX, RSI] in 585184610Salfred def MONTMUL : I<0xa6, MRM_C0, (outs), (ins), "montmul", []>, TB; 586184610Salfred} // SchedRW 587184610Salfred 588184610Salfred//==-----------------------------------------------------------------------===// 589184610Salfred// PKU - enable protection key 590184610Salfredlet SchedRW = [WriteSystem] in { 591184610Salfredlet Defs = [EAX, EDX], Uses = [ECX] in 592184610Salfred def RDPKRUr : I<0x01, MRM_EE, (outs), (ins), "rdpkru", 593184610Salfred [(set EAX, (X86rdpkru ECX)), (implicit EDX)]>, TB; 594184610Salfredlet Uses = [EAX, ECX, EDX] in 595184610Salfred def WRPKRUr : I<0x01, MRM_EF, (outs), (ins), "wrpkru", 596184610Salfred [(X86wrpkru EAX, EDX, ECX)]>, TB; 597184610Salfred} // SchedRW 598184610Salfred 599184610Salfred//===----------------------------------------------------------------------===// 600184610Salfred// FS/GS Base Instructions 601184610Salfredlet Predicates = [HasFSGSBase, In64BitMode], SchedRW = [WriteSystem] in { 602184610Salfred def RDFSBASE : I<0xAE, MRM0r, (outs GR32:$dst), (ins), 603201705Sthompsa "rdfsbase{l}\t$dst", 604201705Sthompsa [(set GR32:$dst, (int_x86_rdfsbase_32))]>, XS; 605184610Salfred def RDFSBASE64 : RI<0xAE, MRM0r, (outs GR64:$dst), (ins), 606184610Salfred "rdfsbase{q}\t$dst", 607184610Salfred [(set GR64:$dst, (int_x86_rdfsbase_64))]>, XS; 608184610Salfred def RDGSBASE : I<0xAE, MRM1r, (outs GR32:$dst), (ins), 609184610Salfred "rdgsbase{l}\t$dst", 610201705Sthompsa [(set GR32:$dst, (int_x86_rdgsbase_32))]>, XS; 611201705Sthompsa def RDGSBASE64 : RI<0xAE, MRM1r, (outs GR64:$dst), (ins), 612184610Salfred "rdgsbase{q}\t$dst", 613184610Salfred [(set GR64:$dst, (int_x86_rdgsbase_64))]>, XS; 614184610Salfred def WRFSBASE : I<0xAE, MRM2r, (outs), (ins GR32:$src), 615184610Salfred "wrfsbase{l}\t$src", 616188622Sthompsa [(int_x86_wrfsbase_32 GR32:$src)]>, XS; 617188622Sthompsa def WRFSBASE64 : RI<0xAE, MRM2r, (outs), (ins GR64:$src), 618188622Sthompsa "wrfsbase{q}\t$src", 619188622Sthompsa [(int_x86_wrfsbase_64 GR64:$src)]>, XS; 620201705Sthompsa def WRGSBASE : I<0xAE, MRM3r, (outs), (ins GR32:$src), 621201705Sthompsa "wrgsbase{l}\t$src", 622201705Sthompsa [(int_x86_wrgsbase_32 GR32:$src)]>, XS; 623201705Sthompsa def WRGSBASE64 : RI<0xAE, MRM3r, (outs), (ins GR64:$src), 624201705Sthompsa "wrgsbase{q}\t$src", 625201705Sthompsa [(int_x86_wrgsbase_64 GR64:$src)]>, XS; 626201705Sthompsa} 627201705Sthompsa 628201705Sthompsa//===----------------------------------------------------------------------===// 629201705Sthompsa// INVPCID Instruction 630201705Sthompsalet SchedRW = [WriteSystem] in { 631201705Sthompsadef INVPCID32 : I<0x82, MRMSrcMem, (outs), (ins GR32:$src1, i128mem:$src2), 632201705Sthompsa "invpcid\t{$src2, $src1|$src1, $src2}", 633201705Sthompsa [(int_x86_invpcid GR32:$src1, addr:$src2)]>, T8PD, 634201705Sthompsa Requires<[Not64BitMode, HasINVPCID]>; 635201705Sthompsadef INVPCID64 : I<0x82, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2), 636201705Sthompsa "invpcid\t{$src2, $src1|$src1, $src2}", []>, T8PD, 637201705Sthompsa Requires<[In64BitMode, HasINVPCID]>; 638201705Sthompsa} // SchedRW 639201705Sthompsa 640201705Sthompsalet Predicates = [In64BitMode, HasINVPCID] in { 641201705Sthompsa // The instruction can only use a 64 bit register as the register argument 642201705Sthompsa // in 64 bit mode, while the intrinsic only accepts a 32 bit argument 643201705Sthompsa // corresponding to it. 644201705Sthompsa // The accepted values for now are 0,1,2,3 anyways (see Intel SDM -- INVCPID 645201705Sthompsa // type),/ so it doesn't hurt us that one can't supply a 64 bit value here. 646201705Sthompsa def : Pat<(int_x86_invpcid GR32:$src1, addr:$src2), 647184610Salfred (INVPCID64 648184610Salfred (SUBREG_TO_REG (i64 0), (MOV32rr GR32:$src1), sub_32bit), 649184610Salfred addr:$src2)>; 650184610Salfred} 651184610Salfred 652184610Salfred 653184610Salfred//===----------------------------------------------------------------------===// 654184610Salfred// SMAP Instruction 655184610Salfredlet Defs = [EFLAGS], SchedRW = [WriteSystem] in { 656184610Salfred def CLAC : I<0x01, MRM_CA, (outs), (ins), "clac", []>, TB; 657184610Salfred def STAC : I<0x01, MRM_CB, (outs), (ins), "stac", []>, TB; 658184610Salfred} 659184610Salfred 660184610Salfred//===----------------------------------------------------------------------===// 661184610Salfred// SMX Instruction 662184610Salfredlet SchedRW = [WriteSystem] in { 663184610Salfredlet Uses = [RAX, RBX, RCX, RDX], Defs = [RAX, RBX, RCX] in { 664184610Salfred def GETSEC : I<0x37, RawFrm, (outs), (ins), "getsec", []>, TB; 665184610Salfred} // Uses, Defs 666184610Salfred} // SchedRW 667201705Sthompsa 668201705Sthompsa//===----------------------------------------------------------------------===// 669185087Salfred// TS flag control instruction. 670184610Salfredlet SchedRW = [WriteSystem] in { 671184610Salfreddef CLTS : I<0x06, RawFrm, (outs), (ins), "clts", []>, TB; 672184610Salfred} 673184610Salfred 674184610Salfred//===----------------------------------------------------------------------===// 675201705Sthompsa// IF (inside EFLAGS) management instructions. 676201705Sthompsalet SchedRW = [WriteSystem], Uses = [EFLAGS], Defs = [EFLAGS] in { 677185087Salfreddef CLI : I<0xFA, RawFrm, (outs), (ins), "cli", []>; 678184610Salfreddef STI : I<0xFB, RawFrm, (outs), (ins), "sti", []>; 679184610Salfred} 680184610Salfred 681184610Salfred//===----------------------------------------------------------------------===// 682188987Sthompsa// RDPID Instruction 683201705Sthompsalet SchedRW = [WriteSystem] in { 684201705Sthompsadef RDPID32 : I<0xC7, MRM7r, (outs GR32:$dst), (ins), 685189110Sthompsa "rdpid\t$dst", [(set GR32:$dst, (int_x86_rdpid))]>, XS, 686188987Sthompsa Requires<[Not64BitMode, HasRDPID]>; 687188987Sthompsadef RDPID64 : I<0xC7, MRM7r, (outs GR64:$dst), (ins), "rdpid\t$dst", []>, XS, 688188987Sthompsa Requires<[In64BitMode, HasRDPID]>; 689188987Sthompsa} // SchedRW 690188987Sthompsa 691201705Sthompsalet Predicates = [In64BitMode, HasRDPID] in { 692201705Sthompsa // Due to silly instruction definition, we have to compensate for the 693188987Sthompsa // instruction outputing a 64-bit register. 694188987Sthompsa def : Pat<(int_x86_rdpid), 695188987Sthompsa (EXTRACT_SUBREG (RDPID64), sub_32bit)>; 696184610Salfred} 697201705Sthompsa 698201705Sthompsa 699184610Salfred//===----------------------------------------------------------------------===// 700184610Salfred// PTWRITE Instruction - Write Data to a Processor Trace Packet 701184610Salfredlet SchedRW = [WriteSystem] in { 702184610Salfreddef PTWRITEm: I<0xAE, MRM4m, (outs), (ins i32mem:$dst), 703201705Sthompsa "ptwrite{l}\t$dst", [(int_x86_ptwrite32 (loadi32 addr:$dst))]>, XS, 704201705Sthompsa Requires<[HasPTWRITE]>; 705184610Salfreddef PTWRITE64m : RI<0xAE, MRM4m, (outs), (ins i64mem:$dst), 706184610Salfred "ptwrite{q}\t$dst", [(int_x86_ptwrite64 (loadi64 addr:$dst))]>, XS, 707184610Salfred Requires<[In64BitMode, HasPTWRITE]>; 708184610Salfred 709201705Sthompsadef PTWRITEr : I<0xAE, MRM4r, (outs), (ins GR32:$dst), 710201705Sthompsa "ptwrite{l}\t$dst", [(int_x86_ptwrite32 GR32:$dst)]>, XS, 711184610Salfred Requires<[HasPTWRITE]>; 712184610Salfreddef PTWRITE64r : RI<0xAE, MRM4r, (outs), (ins GR64:$dst), 713184610Salfred "ptwrite{q}\t$dst", [(int_x86_ptwrite64 GR64:$dst)]>, XS, 714184610Salfred Requires<[In64BitMode, HasPTWRITE]>; 715201705Sthompsa} // SchedRW 716201705Sthompsa 717184610Salfred//===----------------------------------------------------------------------===// 718184610Salfred// Platform Configuration instruction 719184610Salfred 720185087Salfred// From ISA docs: 721201705Sthompsa// "This instruction is used to execute functions for configuring platform 722201705Sthompsa// features. 723185087Salfred// EAX: Leaf function to be invoked. 724185087Salfred// RBX/RCX/RDX: Leaf-specific purpose." 725185087Salfred// "Successful execution of the leaf clears RAX (set to zero) and ZF, CF, PF, 726185087Salfred// AF, OF, and SF are cleared. In case of failure, the failure reason is 727185087Salfred// indicated in RAX with ZF set to 1 and CF, PF, AF, OF, and SF are cleared." 728184610Salfred// Thus all these mentioned registers are considered clobbered. 729201705Sthompsa 730201705Sthompsalet SchedRW = [WriteSystem] in { 731184610Salfredlet Uses = [RAX, RBX, RCX, RDX], Defs = [RAX, RBX, RCX, RDX, EFLAGS] in 732184610Salfred def PCONFIG : I<0x01, MRM_C5, (outs), (ins), "pconfig", []>, TB, 733184610Salfred Requires<[HasPCONFIG]>; 734184610Salfred} // SchedRW 735201705Sthompsa