X86InstrMMX.td revision 360784 
1//===-- X86InstrMMX.td - Describe the MMX Instruction Set --*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file describes the X86 MMX instruction set, defining the instructions,
10// and properties of the instructions which are needed for code generation,
11// machine code emission, and analysis.
12//
13// All instructions that use MMX should be in this file, even if they also use
14// SSE.
15//
16//===----------------------------------------------------------------------===//
17
18//===----------------------------------------------------------------------===//
19// MMX Multiclasses
20//===----------------------------------------------------------------------===//
21
22// Alias instruction that maps zero vector to pxor mmx.
23// This is expanded by ExpandPostRAPseudos to an pxor.
24// We set canFoldAsLoad because this can be converted to a constant-pool
25// load of an all-zeros value if folding it would be beneficial.
26let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
27    isPseudo = 1, SchedRW = [WriteZero] in {
28def MMX_SET0 : I<0, Pseudo, (outs VR64:$dst), (ins), "", []>;
29}
30
31let Constraints = "$src1 = $dst" in {
32  // MMXI_binop_rm_int - Simple MMX binary operator based on intrinsic.
33  multiclass MMXI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
34                               X86FoldableSchedWrite sched, bit Commutable = 0,
35                               X86MemOperand OType = i64mem> {
36    def irr : MMXI<opc, MRMSrcReg, (outs VR64:$dst),
37                 (ins VR64:$src1, VR64:$src2),
38                 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
39                 [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2))]>,
40              Sched<[sched]> {
41      let isCommutable = Commutable;
42    }
43    def irm : MMXI<opc, MRMSrcMem, (outs VR64:$dst),
44                 (ins VR64:$src1, OType:$src2),
45                 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
46                 [(set VR64:$dst, (IntId VR64:$src1,
47                                   (bitconvert (load_mmx addr:$src2))))]>,
48                 Sched<[sched.Folded, sched.ReadAfterFold]>;
49  }
50
51  multiclass MMXI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
52                                string OpcodeStr, Intrinsic IntId,
53                                Intrinsic IntId2, X86FoldableSchedWrite sched,
54                                X86FoldableSchedWrite schedImm> {
55    def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst),
56                                  (ins VR64:$src1, VR64:$src2),
57                  !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
58                  [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2))]>,
59             Sched<[sched]>;
60    def rm : MMXI<opc, MRMSrcMem, (outs VR64:$dst),
61                                  (ins VR64:$src1, i64mem:$src2),
62                  !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
63                  [(set VR64:$dst, (IntId VR64:$src1,
64                                    (bitconvert (load_mmx addr:$src2))))]>,
65                  Sched<[sched.Folded, sched.ReadAfterFold]>;
66    def ri : MMXIi8<opc2, ImmForm, (outs VR64:$dst),
67                                   (ins VR64:$src1, i32u8imm:$src2),
68                    !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
69           [(set VR64:$dst, (IntId2 VR64:$src1, timm:$src2))]>,
70           Sched<[schedImm]>;
71  }
72}
73
74/// Unary MMX instructions requiring SSSE3.
75multiclass SS3I_unop_rm_int_mm<bits<8> opc, string OpcodeStr,
76                               Intrinsic IntId64, X86FoldableSchedWrite sched> {
77  def rr : MMXSS38I<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
78                 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
79                 [(set VR64:$dst, (IntId64 VR64:$src))]>,
80           Sched<[sched]>;
81
82  def rm : MMXSS38I<opc, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src),
83                 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
84                 [(set VR64:$dst,
85                   (IntId64 (bitconvert (load_mmx addr:$src))))]>,
86                 Sched<[sched.Folded]>;
87}
88
89/// Binary MMX instructions requiring SSSE3.
90let ImmT = NoImm, Constraints = "$src1 = $dst" in {
91multiclass SS3I_binop_rm_int_mm<bits<8> opc, string OpcodeStr,
92                             Intrinsic IntId64, X86FoldableSchedWrite sched,
93                             bit Commutable = 0> {
94  let isCommutable = Commutable in
95  def rr : MMXSS38I<opc, MRMSrcReg, (outs VR64:$dst),
96       (ins VR64:$src1, VR64:$src2),
97        !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
98       [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]>,
99      Sched<[sched]>;
100  def rm : MMXSS38I<opc, MRMSrcMem, (outs VR64:$dst),
101       (ins VR64:$src1, i64mem:$src2),
102        !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
103       [(set VR64:$dst,
104         (IntId64 VR64:$src1,
105          (bitconvert (load_mmx addr:$src2))))]>,
106      Sched<[sched.Folded, sched.ReadAfterFold]>;
107}
108}
109
110/// PALIGN MMX instructions (require SSSE3).
111multiclass ssse3_palign_mm<string asm, Intrinsic IntId,
112                           X86FoldableSchedWrite sched> {
113  def rri  : MMXSS3AI<0x0F, MRMSrcReg, (outs VR64:$dst),
114      (ins VR64:$src1, VR64:$src2, u8imm:$src3),
115      !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
116      [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2, (i8 timm:$src3)))]>,
117      Sched<[sched]>;
118  def rmi  : MMXSS3AI<0x0F, MRMSrcMem, (outs VR64:$dst),
119      (ins VR64:$src1, i64mem:$src2, u8imm:$src3),
120      !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
121      [(set VR64:$dst, (IntId VR64:$src1,
122                       (bitconvert (load_mmx addr:$src2)), (i8 timm:$src3)))]>,
123      Sched<[sched.Folded, sched.ReadAfterFold]>;
124}
125
126multiclass sse12_cvt_pint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
127                         Intrinsic Int, X86MemOperand x86memop, PatFrag ld_frag,
128                         string asm, X86FoldableSchedWrite sched, Domain d> {
129  def irr : MMXPI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
130                  [(set DstRC:$dst, (Int SrcRC:$src))], d>,
131            Sched<[sched]>;
132  def irm : MMXPI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
133                  [(set DstRC:$dst, (Int (ld_frag addr:$src)))], d>,
134            Sched<[sched.Folded]>;
135}
136
137multiclass sse12_cvt_pint_3addr<bits<8> opc, RegisterClass SrcRC,
138                    RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
139                    PatFrag ld_frag, string asm, Domain d> {
140  def irr : MMXPI<opc, MRMSrcReg, (outs DstRC:$dst),
141                  (ins DstRC:$src1, SrcRC:$src2), asm,
142                  [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))], d>,
143                  Sched<[WriteCvtI2PS]>;
144  def irm : MMXPI<opc, MRMSrcMem, (outs DstRC:$dst),
145                  (ins DstRC:$src1, x86memop:$src2), asm,
146                  [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))], d>,
147                  Sched<[WriteCvtI2PS.Folded]>;
148}
149
150//===----------------------------------------------------------------------===//
151// MMX EMMS Instruction
152//===----------------------------------------------------------------------===//
153
154let SchedRW = [WriteEMMS],
155    Defs = [MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
156            ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7] in
157def MMX_EMMS  : MMXI<0x77, RawFrm, (outs), (ins), "emms", [(int_x86_mmx_emms)]>;
158
159//===----------------------------------------------------------------------===//
160// MMX Scalar Instructions
161//===----------------------------------------------------------------------===//
162
163// Data Transfer Instructions
164def MMX_MOVD64rr : MMXI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR32:$src),
165                        "movd\t{$src, $dst|$dst, $src}",
166                        [(set VR64:$dst,
167                         (x86mmx (scalar_to_vector GR32:$src)))]>,
168                        Sched<[WriteVecMoveFromGpr]>;
169def MMX_MOVD64rm : MMXI<0x6E, MRMSrcMem, (outs VR64:$dst), (ins i32mem:$src),
170                        "movd\t{$src, $dst|$dst, $src}",
171                        [(set VR64:$dst,
172                        (x86mmx (scalar_to_vector (loadi32 addr:$src))))]>,
173                        Sched<[WriteVecLoad]>;
174
175let Predicates = [HasMMX] in {
176  def : Pat<(x86mmx (MMX_X86movw2d GR32:$src)),
177            (MMX_MOVD64rr GR32:$src)>;
178  def : Pat<(x86mmx (MMX_X86movw2d (i32 0))),
179            (MMX_SET0)>;
180  def : Pat<(x86mmx (MMX_X86movw2d (loadi32 addr:$src))),
181            (MMX_MOVD64rm addr:$src)>;
182}
183
184let mayStore = 1 in
185def MMX_MOVD64mr : MMXI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR64:$src),
186                        "movd\t{$src, $dst|$dst, $src}", []>,
187                   Sched<[WriteVecStore]>;
188
189def MMX_MOVD64grr : MMXI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR64:$src),
190                         "movd\t{$src, $dst|$dst, $src}",
191                         [(set GR32:$dst,
192                          (MMX_X86movd2w (x86mmx VR64:$src)))]>,
193                         Sched<[WriteVecMoveToGpr]>, FoldGenData<"MMX_MOVD64rr">;
194
195let isBitcast = 1 in
196def MMX_MOVD64to64rr : MMXRI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR64:$src),
197                             "movq\t{$src, $dst|$dst, $src}",
198                             [(set VR64:$dst, (bitconvert GR64:$src))]>,
199                             Sched<[WriteVecMoveFromGpr]>;
200
201let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayLoad = 1 in
202def MMX_MOVD64to64rm : MMXRI<0x6E, MRMSrcMem, (outs VR64:$dst),
203                             (ins i64mem:$src), "movq\t{$src, $dst|$dst, $src}",
204                             []>, Sched<[SchedWriteVecMoveLS.MMX.RM]>;
205
206let isBitcast = 1 in {
207def MMX_MOVD64from64rr : MMXRI<0x7E, MRMDestReg,
208                               (outs GR64:$dst), (ins VR64:$src),
209                               "movq\t{$src, $dst|$dst, $src}",
210                               [(set GR64:$dst, (bitconvert VR64:$src))]>,
211                               Sched<[WriteVecMoveToGpr]>;
212let SchedRW = [WriteVecMove], hasSideEffects = 0, isMoveReg = 1 in {
213def MMX_MOVQ64rr : MMXI<0x6F, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
214                        "movq\t{$src, $dst|$dst, $src}", []>;
215let isCodeGenOnly = 1, ForceDisassemble = 1 in
216def MMX_MOVQ64rr_REV : MMXI<0x7F, MRMDestReg, (outs VR64:$dst), (ins VR64:$src),
217                            "movq\t{$src, $dst|$dst, $src}", []>,
218                            FoldGenData<"MMX_MOVQ64rr">;
219} // SchedRW, hasSideEffects, isMoveReg
220} // isBitcast
221
222def : InstAlias<"movq.s\t{$src, $dst|$dst, $src}",
223                (MMX_MOVQ64rr_REV VR64:$dst, VR64:$src), 0>;
224
225let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayStore = 1 in
226def MMX_MOVD64from64rm : MMXRI<0x7E, MRMDestMem,
227                               (outs), (ins i64mem:$dst, VR64:$src),
228                               "movq\t{$src, $dst|$dst, $src}", []>,
229                               Sched<[SchedWriteVecMoveLS.MMX.MR]>;
230
231let SchedRW = [SchedWriteVecMoveLS.MMX.RM] in {
232let canFoldAsLoad = 1 in
233def MMX_MOVQ64rm : MMXI<0x6F, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src),
234                        "movq\t{$src, $dst|$dst, $src}",
235                        [(set VR64:$dst, (load_mmx addr:$src))]>;
236} // SchedRW
237
238let SchedRW = [SchedWriteVecMoveLS.MMX.MR] in
239def MMX_MOVQ64mr : MMXI<0x7F, MRMDestMem, (outs), (ins i64mem:$dst, VR64:$src),
240                        "movq\t{$src, $dst|$dst, $src}",
241                        [(store (x86mmx VR64:$src), addr:$dst)]>;
242
243let SchedRW = [SchedWriteVecMoveLS.XMM.RR] in {
244def MMX_MOVDQ2Qrr : MMXSDIi8<0xD6, MRMSrcReg, (outs VR64:$dst),
245                             (ins VR128:$src), "movdq2q\t{$src, $dst|$dst, $src}",
246                             [(set VR64:$dst,
247                               (x86mmx (bitconvert
248                               (i64 (extractelt (v2i64 VR128:$src),
249                                     (iPTR 0))))))]>;
250
251def MMX_MOVQ2DQrr : MMXS2SIi8<0xD6, MRMSrcReg, (outs VR128:$dst),
252                              (ins VR64:$src), "movq2dq\t{$src, $dst|$dst, $src}",
253                              [(set VR128:$dst,
254                                (v2i64
255                                  (scalar_to_vector
256                                    (i64 (bitconvert (x86mmx VR64:$src))))))]>;
257
258let isCodeGenOnly = 1, hasSideEffects = 1 in {
259def MMX_MOVQ2FR64rr: MMXS2SIi8<0xD6, MRMSrcReg, (outs FR64:$dst),
260                               (ins VR64:$src), "movq2dq\t{$src, $dst|$dst, $src}",
261                               []>;
262
263def MMX_MOVFR642Qrr: MMXSDIi8<0xD6, MRMSrcReg, (outs VR64:$dst),
264                              (ins FR64:$src), "movdq2q\t{$src, $dst|$dst, $src}",
265                              []>;
266}
267} // SchedRW
268
269let Predicates = [HasMMX, HasSSE1] in
270def MMX_MOVNTQmr  : MMXI<0xE7, MRMDestMem, (outs), (ins i64mem:$dst, VR64:$src),
271                         "movntq\t{$src, $dst|$dst, $src}",
272                         [(int_x86_mmx_movnt_dq addr:$dst, VR64:$src)]>,
273                         Sched<[SchedWriteVecMoveLSNT.MMX.MR]>;
274
275let Predicates = [HasMMX] in {
276  // movd to MMX register zero-extends
277  def : Pat<(x86mmx (X86vzmovl (x86mmx (scalar_to_vector GR32:$src)))),
278            (MMX_MOVD64rr GR32:$src)>;
279  def : Pat<(x86mmx (X86vzmovl (x86mmx (scalar_to_vector (loadi32 addr:$src))))),
280            (MMX_MOVD64rm addr:$src)>;
281}
282
283// Arithmetic Instructions
284defm MMX_PABSB : SS3I_unop_rm_int_mm<0x1C, "pabsb", int_x86_ssse3_pabs_b,
285                                     SchedWriteVecALU.MMX>;
286defm MMX_PABSW : SS3I_unop_rm_int_mm<0x1D, "pabsw", int_x86_ssse3_pabs_w,
287                                     SchedWriteVecALU.MMX>;
288defm MMX_PABSD : SS3I_unop_rm_int_mm<0x1E, "pabsd", int_x86_ssse3_pabs_d,
289                                     SchedWriteVecALU.MMX>;
290// -- Addition
291defm MMX_PADDB : MMXI_binop_rm_int<0xFC, "paddb", int_x86_mmx_padd_b,
292                                   SchedWriteVecALU.MMX, 1>;
293defm MMX_PADDW : MMXI_binop_rm_int<0xFD, "paddw", int_x86_mmx_padd_w,
294                                   SchedWriteVecALU.MMX, 1>;
295defm MMX_PADDD : MMXI_binop_rm_int<0xFE, "paddd", int_x86_mmx_padd_d,
296                                   SchedWriteVecALU.MMX, 1>;
297let Predicates = [HasMMX, HasSSE2] in
298defm MMX_PADDQ : MMXI_binop_rm_int<0xD4, "paddq", int_x86_mmx_padd_q,
299                                   SchedWriteVecALU.MMX, 1>;
300defm MMX_PADDSB  : MMXI_binop_rm_int<0xEC, "paddsb" , int_x86_mmx_padds_b,
301                                     SchedWriteVecALU.MMX, 1>;
302defm MMX_PADDSW  : MMXI_binop_rm_int<0xED, "paddsw" , int_x86_mmx_padds_w,
303                                     SchedWriteVecALU.MMX, 1>;
304
305defm MMX_PADDUSB : MMXI_binop_rm_int<0xDC, "paddusb", int_x86_mmx_paddus_b,
306                                   SchedWriteVecALU.MMX, 1>;
307defm MMX_PADDUSW : MMXI_binop_rm_int<0xDD, "paddusw", int_x86_mmx_paddus_w,
308                                   SchedWriteVecALU.MMX, 1>;
309
310defm MMX_PHADDW  : SS3I_binop_rm_int_mm<0x01, "phaddw", int_x86_ssse3_phadd_w,
311                                        SchedWritePHAdd.MMX>;
312defm MMX_PHADDD  : SS3I_binop_rm_int_mm<0x02, "phaddd", int_x86_ssse3_phadd_d,
313                                        SchedWritePHAdd.MMX>;
314defm MMX_PHADDSW : SS3I_binop_rm_int_mm<0x03, "phaddsw",int_x86_ssse3_phadd_sw,
315                                        SchedWritePHAdd.MMX>;
316
317// -- Subtraction
318defm MMX_PSUBB : MMXI_binop_rm_int<0xF8, "psubb", int_x86_mmx_psub_b,
319                                   SchedWriteVecALU.MMX>;
320defm MMX_PSUBW : MMXI_binop_rm_int<0xF9, "psubw", int_x86_mmx_psub_w,
321                                   SchedWriteVecALU.MMX>;
322defm MMX_PSUBD : MMXI_binop_rm_int<0xFA, "psubd", int_x86_mmx_psub_d,
323                                   SchedWriteVecALU.MMX>;
324let Predicates = [HasMMX, HasSSE2] in
325defm MMX_PSUBQ : MMXI_binop_rm_int<0xFB, "psubq", int_x86_mmx_psub_q,
326                                   SchedWriteVecALU.MMX>;
327
328defm MMX_PSUBSB  : MMXI_binop_rm_int<0xE8, "psubsb" , int_x86_mmx_psubs_b,
329                                   SchedWriteVecALU.MMX>;
330defm MMX_PSUBSW  : MMXI_binop_rm_int<0xE9, "psubsw" , int_x86_mmx_psubs_w,
331                                   SchedWriteVecALU.MMX>;
332
333defm MMX_PSUBUSB : MMXI_binop_rm_int<0xD8, "psubusb", int_x86_mmx_psubus_b,
334                                   SchedWriteVecALU.MMX>;
335defm MMX_PSUBUSW : MMXI_binop_rm_int<0xD9, "psubusw", int_x86_mmx_psubus_w,
336                                   SchedWriteVecALU.MMX>;
337
338defm MMX_PHSUBW  : SS3I_binop_rm_int_mm<0x05, "phsubw", int_x86_ssse3_phsub_w,
339                                        SchedWritePHAdd.MMX>;
340defm MMX_PHSUBD  : SS3I_binop_rm_int_mm<0x06, "phsubd", int_x86_ssse3_phsub_d,
341                                        SchedWritePHAdd.MMX>;
342defm MMX_PHSUBSW : SS3I_binop_rm_int_mm<0x07, "phsubsw",int_x86_ssse3_phsub_sw,
343                                        SchedWritePHAdd.MMX>;
344
345// -- Multiplication
346defm MMX_PMULLW  : MMXI_binop_rm_int<0xD5, "pmullw", int_x86_mmx_pmull_w,
347                                     SchedWriteVecIMul.MMX, 1>;
348
349defm MMX_PMULHW  : MMXI_binop_rm_int<0xE5, "pmulhw",  int_x86_mmx_pmulh_w,
350                                     SchedWriteVecIMul.MMX, 1>;
351let Predicates = [HasMMX, HasSSE1] in
352defm MMX_PMULHUW : MMXI_binop_rm_int<0xE4, "pmulhuw", int_x86_mmx_pmulhu_w,
353                                     SchedWriteVecIMul.MMX, 1>;
354let Predicates = [HasMMX, HasSSE2] in
355defm MMX_PMULUDQ : MMXI_binop_rm_int<0xF4, "pmuludq", int_x86_mmx_pmulu_dq,
356                                     SchedWriteVecIMul.MMX, 1>;
357defm MMX_PMULHRSW : SS3I_binop_rm_int_mm<0x0B, "pmulhrsw",
358                                     int_x86_ssse3_pmul_hr_sw,
359                                     SchedWriteVecIMul.MMX, 1>;
360
361// -- Miscellanea
362defm MMX_PMADDWD : MMXI_binop_rm_int<0xF5, "pmaddwd", int_x86_mmx_pmadd_wd,
363                                     SchedWriteVecIMul.MMX, 1>;
364
365defm MMX_PMADDUBSW : SS3I_binop_rm_int_mm<0x04, "pmaddubsw",
366                                          int_x86_ssse3_pmadd_ub_sw,
367                                          SchedWriteVecIMul.MMX>;
368let Predicates = [HasMMX, HasSSE1] in {
369defm MMX_PAVGB   : MMXI_binop_rm_int<0xE0, "pavgb", int_x86_mmx_pavg_b,
370                                     SchedWriteVecALU.MMX, 1>;
371defm MMX_PAVGW   : MMXI_binop_rm_int<0xE3, "pavgw", int_x86_mmx_pavg_w,
372                                     SchedWriteVecALU.MMX, 1>;
373
374defm MMX_PMINUB  : MMXI_binop_rm_int<0xDA, "pminub", int_x86_mmx_pminu_b,
375                                     SchedWriteVecALU.MMX, 1>;
376defm MMX_PMINSW  : MMXI_binop_rm_int<0xEA, "pminsw", int_x86_mmx_pmins_w,
377                                     SchedWriteVecALU.MMX, 1>;
378
379defm MMX_PMAXUB  : MMXI_binop_rm_int<0xDE, "pmaxub", int_x86_mmx_pmaxu_b,
380                                     SchedWriteVecALU.MMX, 1>;
381defm MMX_PMAXSW  : MMXI_binop_rm_int<0xEE, "pmaxsw", int_x86_mmx_pmaxs_w,
382                                     SchedWriteVecALU.MMX, 1>;
383
384defm MMX_PSADBW  : MMXI_binop_rm_int<0xF6, "psadbw", int_x86_mmx_psad_bw,
385                                     SchedWritePSADBW.MMX, 1>;
386}
387
388defm MMX_PSIGNB :  SS3I_binop_rm_int_mm<0x08, "psignb", int_x86_ssse3_psign_b,
389                                        SchedWriteVecALU.MMX>;
390defm MMX_PSIGNW :  SS3I_binop_rm_int_mm<0x09, "psignw", int_x86_ssse3_psign_w,
391                                        SchedWriteVecALU.MMX>;
392defm MMX_PSIGND :  SS3I_binop_rm_int_mm<0x0A, "psignd", int_x86_ssse3_psign_d,
393                                        SchedWriteVecALU.MMX>;
394let Constraints = "$src1 = $dst" in
395  defm MMX_PALIGNR : ssse3_palign_mm<"palignr", int_x86_mmx_palignr_b,
396                                     SchedWriteShuffle.MMX>;
397
398// Logical Instructions
399defm MMX_PAND : MMXI_binop_rm_int<0xDB, "pand", int_x86_mmx_pand,
400                                  SchedWriteVecLogic.MMX, 1>;
401defm MMX_POR  : MMXI_binop_rm_int<0xEB, "por" , int_x86_mmx_por,
402                                  SchedWriteVecLogic.MMX, 1>;
403defm MMX_PXOR : MMXI_binop_rm_int<0xEF, "pxor", int_x86_mmx_pxor,
404                                  SchedWriteVecLogic.MMX, 1>;
405defm MMX_PANDN : MMXI_binop_rm_int<0xDF, "pandn", int_x86_mmx_pandn,
406                                   SchedWriteVecLogic.MMX>;
407
408// Shift Instructions
409defm MMX_PSRLW : MMXI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw",
410                                    int_x86_mmx_psrl_w, int_x86_mmx_psrli_w,
411                                    SchedWriteVecShift.MMX,
412                                    SchedWriteVecShiftImm.MMX>;
413defm MMX_PSRLD : MMXI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld",
414                                    int_x86_mmx_psrl_d, int_x86_mmx_psrli_d,
415                                    SchedWriteVecShift.MMX,
416                                    SchedWriteVecShiftImm.MMX>;
417defm MMX_PSRLQ : MMXI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq",
418                                    int_x86_mmx_psrl_q, int_x86_mmx_psrli_q,
419                                    SchedWriteVecShift.MMX,
420                                    SchedWriteVecShiftImm.MMX>;
421
422defm MMX_PSLLW : MMXI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw",
423                                    int_x86_mmx_psll_w, int_x86_mmx_pslli_w,
424                                    SchedWriteVecShift.MMX,
425                                    SchedWriteVecShiftImm.MMX>;
426defm MMX_PSLLD : MMXI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld",
427                                    int_x86_mmx_psll_d, int_x86_mmx_pslli_d,
428                                    SchedWriteVecShift.MMX,
429                                    SchedWriteVecShiftImm.MMX>;
430defm MMX_PSLLQ : MMXI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq",
431                                    int_x86_mmx_psll_q, int_x86_mmx_pslli_q,
432                                    SchedWriteVecShift.MMX,
433                                    SchedWriteVecShiftImm.MMX>;
434
435defm MMX_PSRAW : MMXI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw",
436                                    int_x86_mmx_psra_w, int_x86_mmx_psrai_w,
437                                    SchedWriteVecShift.MMX,
438                                    SchedWriteVecShiftImm.MMX>;
439defm MMX_PSRAD : MMXI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",
440                                    int_x86_mmx_psra_d, int_x86_mmx_psrai_d,
441                                    SchedWriteVecShift.MMX,
442                                    SchedWriteVecShiftImm.MMX>;
443
444// Comparison Instructions
445defm MMX_PCMPEQB : MMXI_binop_rm_int<0x74, "pcmpeqb", int_x86_mmx_pcmpeq_b,
446                                     SchedWriteVecALU.MMX>;
447defm MMX_PCMPEQW : MMXI_binop_rm_int<0x75, "pcmpeqw", int_x86_mmx_pcmpeq_w,
448                                     SchedWriteVecALU.MMX>;
449defm MMX_PCMPEQD : MMXI_binop_rm_int<0x76, "pcmpeqd", int_x86_mmx_pcmpeq_d,
450                                     SchedWriteVecALU.MMX>;
451
452defm MMX_PCMPGTB : MMXI_binop_rm_int<0x64, "pcmpgtb", int_x86_mmx_pcmpgt_b,
453                                     SchedWriteVecALU.MMX>;
454defm MMX_PCMPGTW : MMXI_binop_rm_int<0x65, "pcmpgtw", int_x86_mmx_pcmpgt_w,
455                                     SchedWriteVecALU.MMX>;
456defm MMX_PCMPGTD : MMXI_binop_rm_int<0x66, "pcmpgtd", int_x86_mmx_pcmpgt_d,
457                                     SchedWriteVecALU.MMX>;
458
459// -- Unpack Instructions
460defm MMX_PUNPCKHBW : MMXI_binop_rm_int<0x68, "punpckhbw",
461                                       int_x86_mmx_punpckhbw,
462                                       SchedWriteShuffle.MMX>;
463defm MMX_PUNPCKHWD : MMXI_binop_rm_int<0x69, "punpckhwd",
464                                       int_x86_mmx_punpckhwd,
465                                       SchedWriteShuffle.MMX>;
466defm MMX_PUNPCKHDQ : MMXI_binop_rm_int<0x6A, "punpckhdq",
467                                       int_x86_mmx_punpckhdq,
468                                       SchedWriteShuffle.MMX>;
469defm MMX_PUNPCKLBW : MMXI_binop_rm_int<0x60, "punpcklbw",
470                                       int_x86_mmx_punpcklbw,
471                                       SchedWriteShuffle.MMX,
472                                       0, i32mem>;
473defm MMX_PUNPCKLWD : MMXI_binop_rm_int<0x61, "punpcklwd",
474                                       int_x86_mmx_punpcklwd,
475                                       SchedWriteShuffle.MMX,
476                                       0, i32mem>;
477defm MMX_PUNPCKLDQ : MMXI_binop_rm_int<0x62, "punpckldq",
478                                       int_x86_mmx_punpckldq,
479                                       SchedWriteShuffle.MMX,
480                                       0, i32mem>;
481
482// -- Pack Instructions
483defm MMX_PACKSSWB : MMXI_binop_rm_int<0x63, "packsswb", int_x86_mmx_packsswb,
484                                      SchedWriteShuffle.MMX>;
485defm MMX_PACKSSDW : MMXI_binop_rm_int<0x6B, "packssdw", int_x86_mmx_packssdw,
486                                      SchedWriteShuffle.MMX>;
487defm MMX_PACKUSWB : MMXI_binop_rm_int<0x67, "packuswb", int_x86_mmx_packuswb,
488                                      SchedWriteShuffle.MMX>;
489
490// -- Shuffle Instructions
491defm MMX_PSHUFB : SS3I_binop_rm_int_mm<0x00, "pshufb", int_x86_ssse3_pshuf_b,
492                                       SchedWriteVarShuffle.MMX>;
493
494def MMX_PSHUFWri : MMXIi8<0x70, MRMSrcReg,
495                          (outs VR64:$dst), (ins VR64:$src1, u8imm:$src2),
496                          "pshufw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
497                          [(set VR64:$dst,
498                             (int_x86_sse_pshuf_w VR64:$src1, timm:$src2))]>,
499                          Sched<[SchedWriteShuffle.MMX]>;
500def MMX_PSHUFWmi : MMXIi8<0x70, MRMSrcMem,
501                          (outs VR64:$dst), (ins i64mem:$src1, u8imm:$src2),
502                          "pshufw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
503                          [(set VR64:$dst,
504                             (int_x86_sse_pshuf_w (load_mmx addr:$src1),
505                                                   timm:$src2))]>,
506                          Sched<[SchedWriteShuffle.MMX.Folded]>;
507
508// -- Conversion Instructions
509defm MMX_CVTPS2PI : sse12_cvt_pint<0x2D, VR128, VR64, int_x86_sse_cvtps2pi,
510                      f64mem, load, "cvtps2pi\t{$src, $dst|$dst, $src}",
511                      WriteCvtPS2I, SSEPackedSingle>, PS, SIMD_EXC;
512defm MMX_CVTPD2PI : sse12_cvt_pint<0x2D, VR128, VR64, int_x86_sse_cvtpd2pi,
513                      f128mem, memop, "cvtpd2pi\t{$src, $dst|$dst, $src}",
514                      WriteCvtPD2I, SSEPackedDouble>, PD, SIMD_EXC;
515defm MMX_CVTTPS2PI : sse12_cvt_pint<0x2C, VR128, VR64, int_x86_sse_cvttps2pi,
516                       f64mem, load, "cvttps2pi\t{$src, $dst|$dst, $src}",
517                       WriteCvtPS2I, SSEPackedSingle>, PS, SIMD_EXC;
518defm MMX_CVTTPD2PI : sse12_cvt_pint<0x2C, VR128, VR64, int_x86_sse_cvttpd2pi,
519                       f128mem, memop, "cvttpd2pi\t{$src, $dst|$dst, $src}",
520                       WriteCvtPD2I, SSEPackedDouble>, PD, SIMD_EXC;
521defm MMX_CVTPI2PD : sse12_cvt_pint<0x2A, VR64, VR128, int_x86_sse_cvtpi2pd,
522                         i64mem, load, "cvtpi2pd\t{$src, $dst|$dst, $src}",
523                         WriteCvtI2PD, SSEPackedDouble>, PD;
524let Constraints = "$src1 = $dst" in {
525  defm MMX_CVTPI2PS : sse12_cvt_pint_3addr<0x2A, VR64, VR128,
526                         int_x86_sse_cvtpi2ps,
527                         i64mem, load, "cvtpi2ps\t{$src2, $dst|$dst, $src2}",
528                         SSEPackedSingle>, PS, SIMD_EXC;
529}
530
531// Extract / Insert
532let Predicates = [HasMMX, HasSSE1] in
533def MMX_PEXTRWrr: MMXIi8<0xC5, MRMSrcReg,
534                     (outs GR32orGR64:$dst), (ins VR64:$src1, i32u8imm:$src2),
535                     "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
536                     [(set GR32orGR64:$dst, (int_x86_mmx_pextr_w VR64:$src1,
537                                             timm:$src2))]>,
538                     Sched<[WriteVecExtract]>;
539let Constraints = "$src1 = $dst" in {
540let Predicates = [HasMMX, HasSSE1] in {
541  def MMX_PINSRWrr : MMXIi8<0xC4, MRMSrcReg,
542                    (outs VR64:$dst),
543                    (ins VR64:$src1, GR32orGR64:$src2, i32u8imm:$src3),
544                    "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
545                    [(set VR64:$dst, (int_x86_mmx_pinsr_w VR64:$src1,
546                                      GR32orGR64:$src2, timm:$src3))]>,
547                    Sched<[WriteVecInsert, ReadDefault, ReadInt2Fpu]>;
548
549  def MMX_PINSRWrm : MMXIi8<0xC4, MRMSrcMem,
550                   (outs VR64:$dst),
551                   (ins VR64:$src1, i16mem:$src2, i32u8imm:$src3),
552                   "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
553                   [(set VR64:$dst, (int_x86_mmx_pinsr_w VR64:$src1,
554                                       (i32 (anyext (loadi16 addr:$src2))),
555                                     timm:$src3))]>,
556                   Sched<[WriteVecInsert.Folded, WriteVecInsert.ReadAfterFold]>;
557}
558}
559
560// Mask creation
561let Predicates = [HasMMX, HasSSE1] in
562def MMX_PMOVMSKBrr : MMXI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst),
563                          (ins VR64:$src),
564                          "pmovmskb\t{$src, $dst|$dst, $src}",
565                          [(set GR32orGR64:$dst,
566                                (int_x86_mmx_pmovmskb VR64:$src))]>,
567                          Sched<[WriteMMXMOVMSK]>;
568
569// MMX to XMM for vector types
570def MMX_X86movq2dq : SDNode<"X86ISD::MOVQ2DQ", SDTypeProfile<1, 1,
571                            [SDTCisVT<0, v2i64>, SDTCisVT<1, x86mmx>]>>;
572
573def : Pat<(v2i64 (MMX_X86movq2dq VR64:$src)),
574          (v2i64 (MMX_MOVQ2DQrr VR64:$src))>;
575
576// Low word of XMM to MMX.
577def MMX_X86movdq2q : SDNode<"X86ISD::MOVDQ2Q", SDTypeProfile<1, 1,
578                            [SDTCisVT<0, x86mmx>, SDTCisVT<1, v2i64>]>>;
579
580def : Pat<(x86mmx (MMX_X86movdq2q VR128:$src)),
581          (x86mmx (MMX_MOVDQ2Qrr VR128:$src))>;
582
583def : Pat<(x86mmx (MMX_X86movdq2q (v2i64 (simple_load addr:$src)))),
584          (x86mmx (MMX_MOVQ64rm addr:$src))>;
585
586def : Pat<(v2i64 (X86vzmovl (scalar_to_vector
587                             (i64 (bitconvert (x86mmx VR64:$src)))))),
588          (MMX_MOVQ2DQrr VR64:$src)>;
589
590// Misc.
591let SchedRW = [SchedWriteShuffle.MMX] in {
592let Uses = [EDI], Predicates = [HasMMX, HasSSE1,Not64BitMode] in
593def MMX_MASKMOVQ : MMXI32<0xF7, MRMSrcReg, (outs), (ins VR64:$src, VR64:$mask),
594                          "maskmovq\t{$mask, $src|$src, $mask}",
595                          [(int_x86_mmx_maskmovq VR64:$src, VR64:$mask, EDI)]>;
596let Uses = [RDI], Predicates = [HasMMX, HasSSE1,In64BitMode] in
597def MMX_MASKMOVQ64: MMXI64<0xF7, MRMSrcReg, (outs), (ins VR64:$src, VR64:$mask),
598                           "maskmovq\t{$mask, $src|$src, $mask}",
599                           [(int_x86_mmx_maskmovq VR64:$src, VR64:$mask, RDI)]>;
600}
601
602// 64-bit bit convert.
603let Predicates = [HasMMX, HasSSE2] in {
604def : Pat<(f64 (bitconvert (x86mmx VR64:$src))),
605          (MMX_MOVQ2FR64rr VR64:$src)>;
606def : Pat<(x86mmx (bitconvert (f64 FR64:$src))),
607          (MMX_MOVFR642Qrr FR64:$src)>;
608def : Pat<(x86mmx (MMX_X86movdq2q
609                   (bc_v2i64 (v4i32 (X86cvtp2Int (v4f32 VR128:$src)))))),
610          (MMX_CVTPS2PIirr VR128:$src)>;
611def : Pat<(x86mmx (MMX_X86movdq2q
612                   (bc_v2i64 (v4i32 (X86cvttp2si (v4f32 VR128:$src)))))),
613          (MMX_CVTTPS2PIirr VR128:$src)>;
614def : Pat<(x86mmx (MMX_X86movdq2q
615                   (bc_v2i64 (v4i32 (X86cvtp2Int (v2f64 VR128:$src)))))),
616          (MMX_CVTPD2PIirr VR128:$src)>;
617def : Pat<(x86mmx (MMX_X86movdq2q
618                   (bc_v2i64 (v4i32 (X86cvttp2si (v2f64 VR128:$src)))))),
619          (MMX_CVTTPD2PIirr VR128:$src)>;
620}
621