X86DisassemblerDecoder.h revision 360784 
1//===-- X86DisassemblerDecoderInternal.h - Disassembler decoder -*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file is part of the X86 Disassembler.
10// It contains the public interface of the instruction decoder.
11// Documentation for the disassembler can be found in X86Disassembler.h.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef LLVM_LIB_TARGET_X86_DISASSEMBLER_X86DISASSEMBLERDECODER_H
16#define LLVM_LIB_TARGET_X86_DISASSEMBLER_X86DISASSEMBLERDECODER_H
17
18#include "llvm/ADT/ArrayRef.h"
19#include "llvm/Support/X86DisassemblerDecoderCommon.h"
20
21namespace llvm {
22
23class MCInstrInfo;
24
25namespace X86Disassembler {
26
27// Accessor functions for various fields of an Intel instruction
28#define modFromModRM(modRM)  (((modRM) & 0xc0) >> 6)
29#define regFromModRM(modRM)  (((modRM) & 0x38) >> 3)
30#define rmFromModRM(modRM)   ((modRM) & 0x7)
31#define scaleFromSIB(sib)    (((sib) & 0xc0) >> 6)
32#define indexFromSIB(sib)    (((sib) & 0x38) >> 3)
33#define baseFromSIB(sib)     ((sib) & 0x7)
34#define wFromREX(rex)        (((rex) & 0x8) >> 3)
35#define rFromREX(rex)        (((rex) & 0x4) >> 2)
36#define xFromREX(rex)        (((rex) & 0x2) >> 1)
37#define bFromREX(rex)        ((rex) & 0x1)
38
39#define rFromEVEX2of4(evex)     (((~(evex)) & 0x80) >> 7)
40#define xFromEVEX2of4(evex)     (((~(evex)) & 0x40) >> 6)
41#define bFromEVEX2of4(evex)     (((~(evex)) & 0x20) >> 5)
42#define r2FromEVEX2of4(evex)    (((~(evex)) & 0x10) >> 4)
43#define mmFromEVEX2of4(evex)    ((evex) & 0x3)
44#define wFromEVEX3of4(evex)     (((evex) & 0x80) >> 7)
45#define vvvvFromEVEX3of4(evex)  (((~(evex)) & 0x78) >> 3)
46#define ppFromEVEX3of4(evex)    ((evex) & 0x3)
47#define zFromEVEX4of4(evex)     (((evex) & 0x80) >> 7)
48#define l2FromEVEX4of4(evex)    (((evex) & 0x40) >> 6)
49#define lFromEVEX4of4(evex)     (((evex) & 0x20) >> 5)
50#define bFromEVEX4of4(evex)     (((evex) & 0x10) >> 4)
51#define v2FromEVEX4of4(evex)    (((~evex) & 0x8) >> 3)
52#define aaaFromEVEX4of4(evex)   ((evex) & 0x7)
53
54#define rFromVEX2of3(vex)       (((~(vex)) & 0x80) >> 7)
55#define xFromVEX2of3(vex)       (((~(vex)) & 0x40) >> 6)
56#define bFromVEX2of3(vex)       (((~(vex)) & 0x20) >> 5)
57#define mmmmmFromVEX2of3(vex)   ((vex) & 0x1f)
58#define wFromVEX3of3(vex)       (((vex) & 0x80) >> 7)
59#define vvvvFromVEX3of3(vex)    (((~(vex)) & 0x78) >> 3)
60#define lFromVEX3of3(vex)       (((vex) & 0x4) >> 2)
61#define ppFromVEX3of3(vex)      ((vex) & 0x3)
62
63#define rFromVEX2of2(vex)       (((~(vex)) & 0x80) >> 7)
64#define vvvvFromVEX2of2(vex)    (((~(vex)) & 0x78) >> 3)
65#define lFromVEX2of2(vex)       (((vex) & 0x4) >> 2)
66#define ppFromVEX2of2(vex)      ((vex) & 0x3)
67
68#define rFromXOP2of3(xop)       (((~(xop)) & 0x80) >> 7)
69#define xFromXOP2of3(xop)       (((~(xop)) & 0x40) >> 6)
70#define bFromXOP2of3(xop)       (((~(xop)) & 0x20) >> 5)
71#define mmmmmFromXOP2of3(xop)   ((xop) & 0x1f)
72#define wFromXOP3of3(xop)       (((xop) & 0x80) >> 7)
73#define vvvvFromXOP3of3(vex)    (((~(vex)) & 0x78) >> 3)
74#define lFromXOP3of3(xop)       (((xop) & 0x4) >> 2)
75#define ppFromXOP3of3(xop)      ((xop) & 0x3)
76
77// These enums represent Intel registers for use by the decoder.
78#define REGS_8BIT     \
79  ENTRY(AL)           \
80  ENTRY(CL)           \
81  ENTRY(DL)           \
82  ENTRY(BL)           \
83  ENTRY(AH)           \
84  ENTRY(CH)           \
85  ENTRY(DH)           \
86  ENTRY(BH)           \
87  ENTRY(R8B)          \
88  ENTRY(R9B)          \
89  ENTRY(R10B)         \
90  ENTRY(R11B)         \
91  ENTRY(R12B)         \
92  ENTRY(R13B)         \
93  ENTRY(R14B)         \
94  ENTRY(R15B)         \
95  ENTRY(SPL)          \
96  ENTRY(BPL)          \
97  ENTRY(SIL)          \
98  ENTRY(DIL)
99
100#define EA_BASES_16BIT  \
101  ENTRY(BX_SI)          \
102  ENTRY(BX_DI)          \
103  ENTRY(BP_SI)          \
104  ENTRY(BP_DI)          \
105  ENTRY(SI)             \
106  ENTRY(DI)             \
107  ENTRY(BP)             \
108  ENTRY(BX)             \
109  ENTRY(R8W)            \
110  ENTRY(R9W)            \
111  ENTRY(R10W)           \
112  ENTRY(R11W)           \
113  ENTRY(R12W)           \
114  ENTRY(R13W)           \
115  ENTRY(R14W)           \
116  ENTRY(R15W)
117
118#define REGS_16BIT    \
119  ENTRY(AX)           \
120  ENTRY(CX)           \
121  ENTRY(DX)           \
122  ENTRY(BX)           \
123  ENTRY(SP)           \
124  ENTRY(BP)           \
125  ENTRY(SI)           \
126  ENTRY(DI)           \
127  ENTRY(R8W)          \
128  ENTRY(R9W)          \
129  ENTRY(R10W)         \
130  ENTRY(R11W)         \
131  ENTRY(R12W)         \
132  ENTRY(R13W)         \
133  ENTRY(R14W)         \
134  ENTRY(R15W)
135
136#define EA_BASES_32BIT  \
137  ENTRY(EAX)            \
138  ENTRY(ECX)            \
139  ENTRY(EDX)            \
140  ENTRY(EBX)            \
141  ENTRY(sib)            \
142  ENTRY(EBP)            \
143  ENTRY(ESI)            \
144  ENTRY(EDI)            \
145  ENTRY(R8D)            \
146  ENTRY(R9D)            \
147  ENTRY(R10D)           \
148  ENTRY(R11D)           \
149  ENTRY(R12D)           \
150  ENTRY(R13D)           \
151  ENTRY(R14D)           \
152  ENTRY(R15D)
153
154#define REGS_32BIT  \
155  ENTRY(EAX)        \
156  ENTRY(ECX)        \
157  ENTRY(EDX)        \
158  ENTRY(EBX)        \
159  ENTRY(ESP)        \
160  ENTRY(EBP)        \
161  ENTRY(ESI)        \
162  ENTRY(EDI)        \
163  ENTRY(R8D)        \
164  ENTRY(R9D)        \
165  ENTRY(R10D)       \
166  ENTRY(R11D)       \
167  ENTRY(R12D)       \
168  ENTRY(R13D)       \
169  ENTRY(R14D)       \
170  ENTRY(R15D)
171
172#define EA_BASES_64BIT  \
173  ENTRY(RAX)            \
174  ENTRY(RCX)            \
175  ENTRY(RDX)            \
176  ENTRY(RBX)            \
177  ENTRY(sib64)          \
178  ENTRY(RBP)            \
179  ENTRY(RSI)            \
180  ENTRY(RDI)            \
181  ENTRY(R8)             \
182  ENTRY(R9)             \
183  ENTRY(R10)            \
184  ENTRY(R11)            \
185  ENTRY(R12)            \
186  ENTRY(R13)            \
187  ENTRY(R14)            \
188  ENTRY(R15)
189
190#define REGS_64BIT  \
191  ENTRY(RAX)        \
192  ENTRY(RCX)        \
193  ENTRY(RDX)        \
194  ENTRY(RBX)        \
195  ENTRY(RSP)        \
196  ENTRY(RBP)        \
197  ENTRY(RSI)        \
198  ENTRY(RDI)        \
199  ENTRY(R8)         \
200  ENTRY(R9)         \
201  ENTRY(R10)        \
202  ENTRY(R11)        \
203  ENTRY(R12)        \
204  ENTRY(R13)        \
205  ENTRY(R14)        \
206  ENTRY(R15)
207
208#define REGS_MMX  \
209  ENTRY(MM0)      \
210  ENTRY(MM1)      \
211  ENTRY(MM2)      \
212  ENTRY(MM3)      \
213  ENTRY(MM4)      \
214  ENTRY(MM5)      \
215  ENTRY(MM6)      \
216  ENTRY(MM7)
217
218#define REGS_XMM  \
219  ENTRY(XMM0)     \
220  ENTRY(XMM1)     \
221  ENTRY(XMM2)     \
222  ENTRY(XMM3)     \
223  ENTRY(XMM4)     \
224  ENTRY(XMM5)     \
225  ENTRY(XMM6)     \
226  ENTRY(XMM7)     \
227  ENTRY(XMM8)     \
228  ENTRY(XMM9)     \
229  ENTRY(XMM10)    \
230  ENTRY(XMM11)    \
231  ENTRY(XMM12)    \
232  ENTRY(XMM13)    \
233  ENTRY(XMM14)    \
234  ENTRY(XMM15)    \
235  ENTRY(XMM16)    \
236  ENTRY(XMM17)    \
237  ENTRY(XMM18)    \
238  ENTRY(XMM19)    \
239  ENTRY(XMM20)    \
240  ENTRY(XMM21)    \
241  ENTRY(XMM22)    \
242  ENTRY(XMM23)    \
243  ENTRY(XMM24)    \
244  ENTRY(XMM25)    \
245  ENTRY(XMM26)    \
246  ENTRY(XMM27)    \
247  ENTRY(XMM28)    \
248  ENTRY(XMM29)    \
249  ENTRY(XMM30)    \
250  ENTRY(XMM31)
251
252#define REGS_YMM  \
253  ENTRY(YMM0)     \
254  ENTRY(YMM1)     \
255  ENTRY(YMM2)     \
256  ENTRY(YMM3)     \
257  ENTRY(YMM4)     \
258  ENTRY(YMM5)     \
259  ENTRY(YMM6)     \
260  ENTRY(YMM7)     \
261  ENTRY(YMM8)     \
262  ENTRY(YMM9)     \
263  ENTRY(YMM10)    \
264  ENTRY(YMM11)    \
265  ENTRY(YMM12)    \
266  ENTRY(YMM13)    \
267  ENTRY(YMM14)    \
268  ENTRY(YMM15)    \
269  ENTRY(YMM16)    \
270  ENTRY(YMM17)    \
271  ENTRY(YMM18)    \
272  ENTRY(YMM19)    \
273  ENTRY(YMM20)    \
274  ENTRY(YMM21)    \
275  ENTRY(YMM22)    \
276  ENTRY(YMM23)    \
277  ENTRY(YMM24)    \
278  ENTRY(YMM25)    \
279  ENTRY(YMM26)    \
280  ENTRY(YMM27)    \
281  ENTRY(YMM28)    \
282  ENTRY(YMM29)    \
283  ENTRY(YMM30)    \
284  ENTRY(YMM31)
285
286#define REGS_ZMM  \
287  ENTRY(ZMM0)     \
288  ENTRY(ZMM1)     \
289  ENTRY(ZMM2)     \
290  ENTRY(ZMM3)     \
291  ENTRY(ZMM4)     \
292  ENTRY(ZMM5)     \
293  ENTRY(ZMM6)     \
294  ENTRY(ZMM7)     \
295  ENTRY(ZMM8)     \
296  ENTRY(ZMM9)     \
297  ENTRY(ZMM10)    \
298  ENTRY(ZMM11)    \
299  ENTRY(ZMM12)    \
300  ENTRY(ZMM13)    \
301  ENTRY(ZMM14)    \
302  ENTRY(ZMM15)    \
303  ENTRY(ZMM16)    \
304  ENTRY(ZMM17)    \
305  ENTRY(ZMM18)    \
306  ENTRY(ZMM19)    \
307  ENTRY(ZMM20)    \
308  ENTRY(ZMM21)    \
309  ENTRY(ZMM22)    \
310  ENTRY(ZMM23)    \
311  ENTRY(ZMM24)    \
312  ENTRY(ZMM25)    \
313  ENTRY(ZMM26)    \
314  ENTRY(ZMM27)    \
315  ENTRY(ZMM28)    \
316  ENTRY(ZMM29)    \
317  ENTRY(ZMM30)    \
318  ENTRY(ZMM31)
319
320#define REGS_MASKS \
321  ENTRY(K0)        \
322  ENTRY(K1)        \
323  ENTRY(K2)        \
324  ENTRY(K3)        \
325  ENTRY(K4)        \
326  ENTRY(K5)        \
327  ENTRY(K6)        \
328  ENTRY(K7)
329
330#define REGS_MASK_PAIRS \
331  ENTRY(K0_K1)     \
332  ENTRY(K2_K3)     \
333  ENTRY(K4_K5)     \
334  ENTRY(K6_K7)
335
336#define REGS_SEGMENT \
337  ENTRY(ES)          \
338  ENTRY(CS)          \
339  ENTRY(SS)          \
340  ENTRY(DS)          \
341  ENTRY(FS)          \
342  ENTRY(GS)
343
344#define REGS_DEBUG  \
345  ENTRY(DR0)        \
346  ENTRY(DR1)        \
347  ENTRY(DR2)        \
348  ENTRY(DR3)        \
349  ENTRY(DR4)        \
350  ENTRY(DR5)        \
351  ENTRY(DR6)        \
352  ENTRY(DR7)        \
353  ENTRY(DR8)        \
354  ENTRY(DR9)        \
355  ENTRY(DR10)       \
356  ENTRY(DR11)       \
357  ENTRY(DR12)       \
358  ENTRY(DR13)       \
359  ENTRY(DR14)       \
360  ENTRY(DR15)
361
362#define REGS_CONTROL  \
363  ENTRY(CR0)          \
364  ENTRY(CR1)          \
365  ENTRY(CR2)          \
366  ENTRY(CR3)          \
367  ENTRY(CR4)          \
368  ENTRY(CR5)          \
369  ENTRY(CR6)          \
370  ENTRY(CR7)          \
371  ENTRY(CR8)          \
372  ENTRY(CR9)          \
373  ENTRY(CR10)         \
374  ENTRY(CR11)         \
375  ENTRY(CR12)         \
376  ENTRY(CR13)         \
377  ENTRY(CR14)         \
378  ENTRY(CR15)
379
380#define REGS_BOUND    \
381  ENTRY(BND0)         \
382  ENTRY(BND1)         \
383  ENTRY(BND2)         \
384  ENTRY(BND3)
385
386#define ALL_EA_BASES  \
387  EA_BASES_16BIT      \
388  EA_BASES_32BIT      \
389  EA_BASES_64BIT
390
391#define ALL_SIB_BASES \
392  REGS_32BIT          \
393  REGS_64BIT
394
395#define ALL_REGS      \
396  REGS_8BIT           \
397  REGS_16BIT          \
398  REGS_32BIT          \
399  REGS_64BIT          \
400  REGS_MMX            \
401  REGS_XMM            \
402  REGS_YMM            \
403  REGS_ZMM            \
404  REGS_MASKS          \
405  REGS_MASK_PAIRS     \
406  REGS_SEGMENT        \
407  REGS_DEBUG          \
408  REGS_CONTROL        \
409  REGS_BOUND          \
410  ENTRY(RIP)
411
412/// All possible values of the base field for effective-address
413/// computations, a.k.a. the Mod and R/M fields of the ModR/M byte.
414/// We distinguish between bases (EA_BASE_*) and registers that just happen
415/// to be referred to when Mod == 0b11 (EA_REG_*).
416enum EABase {
417  EA_BASE_NONE,
418#define ENTRY(x) EA_BASE_##x,
419  ALL_EA_BASES
420#undef ENTRY
421#define ENTRY(x) EA_REG_##x,
422  ALL_REGS
423#undef ENTRY
424  EA_max
425};
426
427/// All possible values of the SIB index field.
428/// borrows entries from ALL_EA_BASES with the special case that
429/// sib is synonymous with NONE.
430/// Vector SIB: index can be XMM or YMM.
431enum SIBIndex {
432  SIB_INDEX_NONE,
433#define ENTRY(x) SIB_INDEX_##x,
434  ALL_EA_BASES
435  REGS_XMM
436  REGS_YMM
437  REGS_ZMM
438#undef ENTRY
439  SIB_INDEX_max
440};
441
442/// All possible values of the SIB base field.
443enum SIBBase {
444  SIB_BASE_NONE,
445#define ENTRY(x) SIB_BASE_##x,
446  ALL_SIB_BASES
447#undef ENTRY
448  SIB_BASE_max
449};
450
451/// Possible displacement types for effective-address computations.
452enum EADisplacement {
453  EA_DISP_NONE,
454  EA_DISP_8,
455  EA_DISP_16,
456  EA_DISP_32
457};
458
459/// All possible values of the reg field in the ModR/M byte.
460enum Reg {
461#define ENTRY(x) MODRM_REG_##x,
462  ALL_REGS
463#undef ENTRY
464  MODRM_REG_max
465};
466
467/// All possible segment overrides.
468enum SegmentOverride {
469  SEG_OVERRIDE_NONE,
470  SEG_OVERRIDE_CS,
471  SEG_OVERRIDE_SS,
472  SEG_OVERRIDE_DS,
473  SEG_OVERRIDE_ES,
474  SEG_OVERRIDE_FS,
475  SEG_OVERRIDE_GS,
476  SEG_OVERRIDE_max
477};
478
479/// Possible values for the VEX.m-mmmm field
480enum VEXLeadingOpcodeByte {
481  VEX_LOB_0F = 0x1,
482  VEX_LOB_0F38 = 0x2,
483  VEX_LOB_0F3A = 0x3
484};
485
486enum XOPMapSelect {
487  XOP_MAP_SELECT_8 = 0x8,
488  XOP_MAP_SELECT_9 = 0x9,
489  XOP_MAP_SELECT_A = 0xA
490};
491
492/// Possible values for the VEX.pp/EVEX.pp field
493enum VEXPrefixCode {
494  VEX_PREFIX_NONE = 0x0,
495  VEX_PREFIX_66 = 0x1,
496  VEX_PREFIX_F3 = 0x2,
497  VEX_PREFIX_F2 = 0x3
498};
499
500enum VectorExtensionType {
501  TYPE_NO_VEX_XOP   = 0x0,
502  TYPE_VEX_2B       = 0x1,
503  TYPE_VEX_3B       = 0x2,
504  TYPE_EVEX         = 0x3,
505  TYPE_XOP          = 0x4
506};
507
508/// The specification for how to extract and interpret a full instruction and
509/// its operands.
510struct InstructionSpecifier {
511  uint16_t operands;
512};
513
514/// The x86 internal instruction, which is produced by the decoder.
515struct InternalInstruction {
516  // Opaque value passed to the reader
517  llvm::ArrayRef<uint8_t> bytes;
518  // The address of the next byte to read via the reader
519  uint64_t readerCursor;
520
521  // General instruction information
522
523  // The mode to disassemble for (64-bit, protected, real)
524  DisassemblerMode mode;
525  // The start of the instruction, usable with the reader
526  uint64_t startLocation;
527  // The length of the instruction, in bytes
528  size_t length;
529
530  // Prefix state
531
532  // The possible mandatory prefix
533  uint8_t mandatoryPrefix;
534  // The value of the vector extension prefix(EVEX/VEX/XOP), if present
535  uint8_t vectorExtensionPrefix[4];
536  // The type of the vector extension prefix
537  VectorExtensionType vectorExtensionType;
538  // The value of the REX prefix, if present
539  uint8_t rexPrefix;
540  // The segment override type
541  SegmentOverride segmentOverride;
542  // 1 if the prefix byte, 0xf2 or 0xf3 is xacquire or xrelease
543  bool xAcquireRelease;
544
545  // Address-size override
546  bool hasAdSize;
547  // Operand-size override
548  bool hasOpSize;
549  // Lock prefix
550  bool hasLockPrefix;
551  // The repeat prefix if any
552  uint8_t repeatPrefix;
553
554  // Sizes of various critical pieces of data, in bytes
555  uint8_t registerSize;
556  uint8_t addressSize;
557  uint8_t displacementSize;
558  uint8_t immediateSize;
559
560  // Offsets from the start of the instruction to the pieces of data, which is
561  // needed to find relocation entries for adding symbolic operands.
562  uint8_t displacementOffset;
563  uint8_t immediateOffset;
564
565  // opcode state
566
567  // The last byte of the opcode, not counting any ModR/M extension
568  uint8_t opcode;
569
570  // decode state
571
572  // The type of opcode, used for indexing into the array of decode tables
573  OpcodeType opcodeType;
574  // The instruction ID, extracted from the decode table
575  uint16_t instructionID;
576  // The specifier for the instruction, from the instruction info table
577  const InstructionSpecifier *spec;
578
579  // state for additional bytes, consumed during operand decode.  Pattern:
580  // consumed___ indicates that the byte was already consumed and does not
581  // need to be consumed again.
582
583  // The VEX.vvvv field, which contains a third register operand for some AVX
584  // instructions.
585  Reg                           vvvv;
586
587  // The writemask for AVX-512 instructions which is contained in EVEX.aaa
588  Reg                           writemask;
589
590  // The ModR/M byte, which contains most register operands and some portion of
591  // all memory operands.
592  bool                          consumedModRM;
593  uint8_t                       modRM;
594
595  // The SIB byte, used for more complex 32- or 64-bit memory operands
596  uint8_t                       sib;
597
598  // The displacement, used for memory operands
599  int32_t                       displacement;
600
601  // Immediates.  There can be two in some cases
602  uint8_t                       numImmediatesConsumed;
603  uint8_t                       numImmediatesTranslated;
604  uint64_t                      immediates[2];
605
606  // A register or immediate operand encoded into the opcode
607  Reg                           opcodeRegister;
608
609  // Portions of the ModR/M byte
610
611  // These fields determine the allowable values for the ModR/M fields, which
612  // depend on operand and address widths.
613  EABase                        eaRegBase;
614  Reg                           regBase;
615
616  // The Mod and R/M fields can encode a base for an effective address, or a
617  // register.  These are separated into two fields here.
618  EABase                        eaBase;
619  EADisplacement                eaDisplacement;
620  // The reg field always encodes a register
621  Reg                           reg;
622
623  // SIB state
624  SIBIndex                      sibIndexBase;
625  SIBIndex                      sibIndex;
626  uint8_t                       sibScale;
627  SIBBase                       sibBase;
628
629  // Embedded rounding control.
630  uint8_t                       RC;
631
632  ArrayRef<OperandSpecifier> operands;
633};
634
635} // namespace X86Disassembler
636} // namespace llvm
637
638#endif
639