SystemZTargetMachine.cpp revision 360784
11590Srgrimes//===-- SystemZTargetMachine.cpp - Define TargetMachine for SystemZ -------===// 21590Srgrimes// 31590Srgrimes// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 41590Srgrimes// See https://llvm.org/LICENSE.txt for license information. 51590Srgrimes// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 61590Srgrimes// 71590Srgrimes//===----------------------------------------------------------------------===// 81590Srgrimes 91590Srgrimes#include "SystemZTargetMachine.h" 101590Srgrimes#include "MCTargetDesc/SystemZMCTargetDesc.h" 111590Srgrimes#include "SystemZ.h" 121590Srgrimes#include "SystemZMachineScheduler.h" 131590Srgrimes#include "SystemZTargetTransformInfo.h" 141590Srgrimes#include "TargetInfo/SystemZTargetInfo.h" 151590Srgrimes#include "llvm/ADT/Optional.h" 161590Srgrimes#include "llvm/ADT/STLExtras.h" 171590Srgrimes#include "llvm/ADT/SmallVector.h" 181590Srgrimes#include "llvm/ADT/StringRef.h" 191590Srgrimes#include "llvm/Analysis/TargetTransformInfo.h" 201590Srgrimes#include "llvm/CodeGen/Passes.h" 211590Srgrimes#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" 221590Srgrimes#include "llvm/CodeGen/TargetPassConfig.h" 231590Srgrimes#include "llvm/IR/DataLayout.h" 241590Srgrimes#include "llvm/Support/CodeGen.h" 251590Srgrimes#include "llvm/Support/TargetRegistry.h" 261590Srgrimes#include "llvm/Target/TargetLoweringObjectFile.h" 271590Srgrimes#include "llvm/Transforms/Scalar.h" 281590Srgrimes#include <string> 291590Srgrimes 301590Srgrimesusing namespace llvm; 311590Srgrimes 321590Srgrimesextern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeSystemZTarget() { 331590Srgrimes // Register the target. 341590Srgrimes RegisterTargetMachine<SystemZTargetMachine> X(getTheSystemZTarget()); 3527314Scharnier} 361590Srgrimes 371590Srgrimes// Determine whether we use the vector ABI. 381590Srgrimesstatic bool UsesVectorABI(StringRef CPU, StringRef FS) { 391590Srgrimes // We use the vector ABI whenever the vector facility is avaiable. 401590Srgrimes // This is the case by default if CPU is z13 or later, and can be 4127314Scharnier // overridden via "[+-]vector" feature string elements. 4223693Speter bool VectorABI = true; 4327314Scharnier if (CPU.empty() || CPU == "generic" || 4427314Scharnier CPU == "z10" || CPU == "z196" || CPU == "zEC12") 4550477Speter VectorABI = false; 461590Srgrimes 471590Srgrimes SmallVector<StringRef, 3> Features; 481590Srgrimes FS.split(Features, ',', -1, false /* KeepEmpty */); 4923693Speter for (auto &Feature : Features) { 5023693Speter if (Feature == "vector" || Feature == "+vector") 5127314Scharnier VectorABI = true; 5223693Speter if (Feature == "-vector") 531590Srgrimes VectorABI = false; 541590Srgrimes } 5523693Speter 561590Srgrimes return VectorABI; 571590Srgrimes} 581590Srgrimes 591590Srgrimesstatic std::string computeDataLayout(const Triple &TT, StringRef CPU, 601590Srgrimes StringRef FS) { 611590Srgrimes bool VectorABI = UsesVectorABI(CPU, FS); 621590Srgrimes std::string Ret; 631590Srgrimes 6424665Salex // Big endian. 651590Srgrimes Ret += "E"; 661590Srgrimes 671590Srgrimes // Data mangling. 681590Srgrimes Ret += DataLayout::getManglingComponent(TT); 691590Srgrimes 701590Srgrimes // Make sure that global data has at least 16 bits of alignment by 711590Srgrimes // default, so that we can refer to it using LARL. We don't have any 721590Srgrimes // special requirements for stack variables though. 731590Srgrimes Ret += "-i1:8:16-i8:8:16"; 741590Srgrimes 7585859Salfred // 64-bit integers are naturally aligned. 761590Srgrimes Ret += "-i64:64"; 771590Srgrimes 781590Srgrimes // 128-bit floats are aligned only to 64 bits. 7924665Salex Ret += "-f128:64"; 801590Srgrimes 8124665Salex // When using the vector ABI, 128-bit vectors are also aligned to 64 bits. 8224665Salex if (VectorABI) 8324665Salex Ret += "-v128:64"; 8427314Scharnier 8524665Salex // We prefer 16 bits of aligned for all globals; see above. 861590Srgrimes Ret += "-a:8:16"; 871590Srgrimes 881590Srgrimes // Integer registers are 32 or 64 bits. 8927314Scharnier Ret += "-n32:64"; 901590Srgrimes 911590Srgrimes return Ret; 921590Srgrimes} 931590Srgrimes 941590Srgrimesstatic Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) { 951590Srgrimes // Static code is suitable for use in a dynamic executable; there is no 961590Srgrimes // separate DynamicNoPIC model. 971590Srgrimes if (!RM.hasValue() || *RM == Reloc::DynamicNoPIC) 9824665Salex return Reloc::Static; 9927314Scharnier return *RM; 10024665Salex} 10124665Salex 10224665Salex// For SystemZ we define the models as follows: 1031590Srgrimes// 1041590Srgrimes// Small: BRASL can call any function and will use a stub if necessary. 10527314Scharnier// Locally-binding symbols will always be in range of LARL. 10627328Scharnier// 1071590Srgrimes// Medium: BRASL can call any function and will use a stub if necessary. 1081590Srgrimes// GOT slots and locally-defined text will always be in range 1091590Srgrimes// of LARL, but other symbols might not be. 1101590Srgrimes// 1111590Srgrimes// Large: Equivalent to Medium for now. 1121590Srgrimes// 1131590Srgrimes// Kernel: Equivalent to Medium for now. 11424665Salex// 11524665Salex// This means that any PIC module smaller than 4GB meets the 11624665Salex// requirements of Small, so Small seems like the best default there. 11724665Salex// 1181590Srgrimes// All symbols bind locally in a non-PIC module, so the choice is less 1191590Srgrimes// obvious. There are two cases: 12085859Salfred// 12124665Salex// - When creating an executable, PLTs and copy relocations allow 1221590Srgrimes// us to treat external symbols as part of the executable. 12324665Salex// Any executable smaller than 4GB meets the requirements of Small, 12424665Salex// so that seems like the best default. 1251590Srgrimes// 1261590Srgrimes// - When creating JIT code, stubs will be in range of BRASL if the 1271590Srgrimes// image is less than 4GB in size. GOT entries will likewise be 1281590Srgrimes// in range of LARL. However, the JIT environment has no equivalent 1291590Srgrimes// of copy relocs, so locally-binding data symbols might not be in 1301590Srgrimes// the range of LARL. We need the Medium model in that case. 1311590Srgrimesstatic CodeModel::Model 1321590SrgrimesgetEffectiveSystemZCodeModel(Optional<CodeModel::Model> CM, Reloc::Model RM, 13385861Salfred bool JIT) { 13485861Salfred if (CM) { 1351590Srgrimes if (*CM == CodeModel::Tiny) 13685861Salfred report_fatal_error("Target does not support the tiny CodeModel", false); 13785861Salfred if (*CM == CodeModel::Kernel) 13885861Salfred report_fatal_error("Target does not support the kernel CodeModel", false); 13985861Salfred return *CM; 14085861Salfred } 14185861Salfred if (JIT) 1421590Srgrimes return RM == Reloc::PIC_ ? CodeModel::Small : CodeModel::Medium; 1431590Srgrimes return CodeModel::Small; 1441590Srgrimes} 14524665Salex 14685859SalfredSystemZTargetMachine::SystemZTargetMachine(const Target &T, const Triple &TT, 14785859Salfred StringRef CPU, StringRef FS, 14824665Salex const TargetOptions &Options, 14924665Salex Optional<Reloc::Model> RM, 15024665Salex Optional<CodeModel::Model> CM, 15124665Salex CodeGenOpt::Level OL, bool JIT) 15224665Salex : LLVMTargetMachine( 15324665Salex T, computeDataLayout(TT, CPU, FS), TT, CPU, FS, Options, 15424665Salex getEffectiveRelocModel(RM), 15524665Salex getEffectiveSystemZCodeModel(CM, getEffectiveRelocModel(RM), JIT), 15624665Salex OL), 15724665Salex TLOF(std::make_unique<TargetLoweringObjectFileELF>()), 15840114Sdes Subtarget(TT, CPU, FS, *this) { 15924665Salex initAsmInfo(); 16024665Salex} 16127314Scharnier 16224665SalexSystemZTargetMachine::~SystemZTargetMachine() = default; 16324665Salex 16424665Salexnamespace { 16524665Salex 16624665Salex/// SystemZ Code Generator Pass Configuration Options. 1671590Srgrimesclass SystemZPassConfig : public TargetPassConfig { 1681590Srgrimespublic: 1691590Srgrimes SystemZPassConfig(SystemZTargetMachine &TM, PassManagerBase &PM) 1701590Srgrimes : TargetPassConfig(TM, PM) {} 1711590Srgrimes 17224665Salex SystemZTargetMachine &getSystemZTargetMachine() const { 1731590Srgrimes return getTM<SystemZTargetMachine>(); 1741590Srgrimes } 1751590Srgrimes 1761590Srgrimes ScheduleDAGInstrs * 17727314Scharnier createPostMachineScheduler(MachineSchedContext *C) const override { 1781590Srgrimes return new ScheduleDAGMI(C, 1791590Srgrimes std::make_unique<SystemZPostRASchedStrategy>(C), 1801590Srgrimes /*RemoveKillFlags=*/true); 1811590Srgrimes } 1821590Srgrimes 1831590Srgrimes void addIRPasses() override; 1841590Srgrimes bool addInstSelector() override; 1851590Srgrimes bool addILPOpts() override; 1861590Srgrimes void addPostRewrite() override; 1871590Srgrimes void addPostRegAlloc() override; 18885859Salfred void addPreSched2() override; 18989767Sdwmalone void addPreEmitPass() override; 1901590Srgrimes}; 1911590Srgrimes 192} // end anonymous namespace 193 194void SystemZPassConfig::addIRPasses() { 195 if (getOptLevel() != CodeGenOpt::None) { 196 addPass(createSystemZTDCPass()); 197 addPass(createLoopDataPrefetchPass()); 198 } 199 200 TargetPassConfig::addIRPasses(); 201} 202 203bool SystemZPassConfig::addInstSelector() { 204 addPass(createSystemZISelDag(getSystemZTargetMachine(), getOptLevel())); 205 206 if (getOptLevel() != CodeGenOpt::None) 207 addPass(createSystemZLDCleanupPass(getSystemZTargetMachine())); 208 209 return false; 210} 211 212bool SystemZPassConfig::addILPOpts() { 213 addPass(&EarlyIfConverterID); 214 return true; 215} 216 217void SystemZPassConfig::addPostRewrite() { 218 addPass(createSystemZPostRewritePass(getSystemZTargetMachine())); 219} 220 221void SystemZPassConfig::addPostRegAlloc() { 222 // PostRewrite needs to be run at -O0 also (in which case addPostRewrite() 223 // is not called). 224 if (getOptLevel() == CodeGenOpt::None) 225 addPass(createSystemZPostRewritePass(getSystemZTargetMachine())); 226} 227 228void SystemZPassConfig::addPreSched2() { 229 if (getOptLevel() != CodeGenOpt::None) 230 addPass(&IfConverterID); 231} 232 233void SystemZPassConfig::addPreEmitPass() { 234 // Do instruction shortening before compare elimination because some 235 // vector instructions will be shortened into opcodes that compare 236 // elimination recognizes. 237 if (getOptLevel() != CodeGenOpt::None) 238 addPass(createSystemZShortenInstPass(getSystemZTargetMachine()), false); 239 240 // We eliminate comparisons here rather than earlier because some 241 // transformations can change the set of available CC values and we 242 // generally want those transformations to have priority. This is 243 // especially true in the commonest case where the result of the comparison 244 // is used by a single in-range branch instruction, since we will then 245 // be able to fuse the compare and the branch instead. 246 // 247 // For example, two-address NILF can sometimes be converted into 248 // three-address RISBLG. NILF produces a CC value that indicates whether 249 // the low word is zero, but RISBLG does not modify CC at all. On the 250 // other hand, 64-bit ANDs like NILL can sometimes be converted to RISBG. 251 // The CC value produced by NILL isn't useful for our purposes, but the 252 // value produced by RISBG can be used for any comparison with zero 253 // (not just equality). So there are some transformations that lose 254 // CC values (while still being worthwhile) and others that happen to make 255 // the CC result more useful than it was originally. 256 // 257 // Another reason is that we only want to use BRANCH ON COUNT in cases 258 // where we know that the count register is not going to be spilled. 259 // 260 // Doing it so late makes it more likely that a register will be reused 261 // between the comparison and the branch, but it isn't clear whether 262 // preventing that would be a win or not. 263 if (getOptLevel() != CodeGenOpt::None) 264 addPass(createSystemZElimComparePass(getSystemZTargetMachine()), false); 265 addPass(createSystemZLongBranchPass(getSystemZTargetMachine())); 266 267 // Do final scheduling after all other optimizations, to get an 268 // optimal input for the decoder (branch relaxation must happen 269 // after block placement). 270 if (getOptLevel() != CodeGenOpt::None) 271 addPass(&PostMachineSchedulerID); 272} 273 274TargetPassConfig *SystemZTargetMachine::createPassConfig(PassManagerBase &PM) { 275 return new SystemZPassConfig(*this, PM); 276} 277 278TargetTransformInfo 279SystemZTargetMachine::getTargetTransformInfo(const Function &F) { 280 return TargetTransformInfo(SystemZTTIImpl(this, F)); 281} 282