SystemZPatterns.td revision 360784 
1//===-- SystemZPatterns.td - SystemZ-specific pattern rules ---*- tblgen-*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9// Record that INSN performs a 64-bit version of unary operator OPERATOR
10// in which the operand is sign-extended from 32 to 64 bits.
11multiclass SXU<SDPatternOperator operator, Instruction insn> {
12  def : Pat<(operator (sext (i32 GR32:$src))),
13            (insn GR32:$src)>;
14  def : Pat<(operator (sext_inreg GR64:$src, i32)),
15            (insn (EXTRACT_SUBREG GR64:$src, subreg_l32))>;
16}
17
18// Record that INSN performs a 64-bit version of binary operator OPERATOR
19// in which the first operand has class CLS and which the second operand
20// is sign-extended from a 32-bit register.
21multiclass SXB<SDPatternOperator operator, RegisterOperand cls,
22               Instruction insn> {
23  def : Pat<(operator cls:$src1, (sext GR32:$src2)),
24            (insn cls:$src1, GR32:$src2)>;
25  def : Pat<(operator cls:$src1, (sext_inreg GR64:$src2, i32)),
26            (insn cls:$src1, (EXTRACT_SUBREG GR64:$src2, subreg_l32))>;
27}
28
29// Like SXB, but for zero extension.
30multiclass ZXB<SDPatternOperator operator, RegisterOperand cls,
31               Instruction insn> {
32  def : Pat<(operator cls:$src1, (zext GR32:$src2)),
33            (insn cls:$src1, GR32:$src2)>;
34  def : Pat<(operator cls:$src1, (and GR64:$src2, 0xffffffff)),
35            (insn cls:$src1, (EXTRACT_SUBREG GR64:$src2, subreg_l32))>;
36}
37
38// Record that INSN performs a binary read-modify-write operation,
39// with LOAD, OPERATOR and STORE being the read, modify and write
40// respectively.  MODE is the addressing mode and IMM is the type
41// of the second operand.
42class RMWI<SDPatternOperator load, SDPatternOperator operator,
43           SDPatternOperator store, AddressingMode mode,
44           PatFrag imm, Instruction insn>
45  : Pat<(store (operator (load mode:$addr), imm:$src), mode:$addr),
46        (insn mode:$addr, (UIMM8 imm:$src))>;
47
48// Record that INSN performs binary operation OPERATION on a byte
49// memory location.  IMM is the type of the second operand.
50multiclass RMWIByte<SDPatternOperator operator, AddressingMode mode,
51                    Instruction insn> {
52  def : RMWI<anyextloadi8, operator, truncstorei8, mode, imm32, insn>;
53  def : RMWI<anyextloadi8, operator, truncstorei8, mode, imm64, insn>;
54}
55
56// Record that INSN performs insertion TYPE into a register of class CLS.
57// The inserted operand is loaded using LOAD from an address of mode MODE.
58multiclass InsertMem<string type, Instruction insn, RegisterOperand cls,
59                     SDPatternOperator load, AddressingMode mode> {
60  def : Pat<(!cast<SDPatternOperator>("or_as_"##type)
61              cls:$src1, (load mode:$src2)),
62            (insn cls:$src1, mode:$src2)>;
63  def : Pat<(!cast<SDPatternOperator>("or_as_rev"##type)
64              (load mode:$src2), cls:$src1),
65            (insn cls:$src1, mode:$src2)>;
66}
67
68// INSN stores the low 32 bits of a GPR to a memory with addressing mode MODE.
69// Record that it is equivalent to using OPERATOR to store a GR64.
70class StoreGR64<Instruction insn, SDPatternOperator operator,
71                AddressingMode mode>
72  : Pat<(operator GR64:$R1, mode:$XBD2),
73        (insn (EXTRACT_SUBREG GR64:$R1, subreg_l32), mode:$XBD2)>;
74
75// INSN and INSNY are an RX/RXY pair of instructions that store the low
76// 32 bits of a GPR to memory.  Record that they are equivalent to using
77// OPERATOR to store a GR64.
78multiclass StoreGR64Pair<Instruction insn, Instruction insny,
79                         SDPatternOperator operator> {
80  def : StoreGR64<insn, operator, bdxaddr12pair>;
81  def : StoreGR64<insny, operator, bdxaddr20pair>;
82}
83
84// INSN stores the low 32 bits of a GPR using PC-relative addressing.
85// Record that it is equivalent to using OPERATOR to store a GR64.
86class StoreGR64PC<Instruction insn, SDPatternOperator operator>
87  : Pat<(operator GR64:$R1, pcrel32:$XBD2),
88        (insn (EXTRACT_SUBREG GR64:$R1, subreg_l32), pcrel32:$XBD2)> {
89  // We want PC-relative addresses to be tried ahead of BD and BDX addresses.
90  // However, BDXs have two extra operands and are therefore 6 units more
91  // complex.
92  let AddedComplexity = 7;
93}
94
95// INSN and INSNINV conditionally store the low 32 bits of a GPR to memory,
96// with INSN storing when the condition is true and INSNINV storing when the
97// condition is false.  Record that they are equivalent to a LOAD/select/STORE
98// sequence for GR64s.
99multiclass CondStores64<Instruction insn, Instruction insninv,
100                        SDPatternOperator store, SDPatternOperator load,
101                        AddressingMode mode> {
102  def : Pat<(store (z_select_ccmask GR64:$new, (load mode:$addr),
103                                    imm32zx4_timm:$valid, imm32zx4_timm:$cc),
104                   mode:$addr),
105            (insn (EXTRACT_SUBREG GR64:$new, subreg_l32), mode:$addr,
106                  imm32zx4:$valid, imm32zx4:$cc)>;
107  def : Pat<(store (z_select_ccmask (load mode:$addr), GR64:$new,
108                                    imm32zx4_timm:$valid, imm32zx4_timm:$cc),
109                   mode:$addr),
110            (insninv (EXTRACT_SUBREG GR64:$new, subreg_l32), mode:$addr,
111                     imm32zx4:$valid, imm32zx4:$cc)>;
112}
113
114// Try to use MVC instruction INSN for a load of type LOAD followed by a store
115// of the same size.  VT is the type of the intermediate (legalized) value and
116// LENGTH is the number of bytes loaded by LOAD.
117multiclass MVCLoadStore<SDPatternOperator load, ValueType vt, Instruction insn,
118                        bits<5> length> {
119  def : Pat<(mvc_store (vt (load bdaddr12only:$src)), bdaddr12only:$dest),
120            (insn bdaddr12only:$dest, bdaddr12only:$src, length)>;
121}
122
123// Use NC-like instruction INSN for block_op operation OPERATOR.
124// The other operand is a load of type LOAD, which accesses LENGTH bytes.
125// VT is the intermediate legalized type in which the binary operation
126// is actually done.
127multiclass BinaryLoadStore<SDPatternOperator operator, SDPatternOperator load,
128                           ValueType vt, Instruction insn, bits<5> length> {
129  def : Pat<(operator (vt (load bdaddr12only:$src)), bdaddr12only:$dest),
130            (insn bdaddr12only:$dest, bdaddr12only:$src, length)>;
131}
132
133// A convenient way of generating all block peepholes for a particular
134// LOAD/VT/LENGTH combination.
135multiclass BlockLoadStore<SDPatternOperator load, ValueType vt,
136                          Instruction mvc, Instruction nc, Instruction oc,
137                          Instruction xc, bits<5> length> {
138  defm : MVCLoadStore<load, vt, mvc, length>;
139  defm : BinaryLoadStore<block_and1, load, vt, nc, length>;
140  defm : BinaryLoadStore<block_and2, load, vt, nc, length>;
141  defm : BinaryLoadStore<block_or1,  load, vt, oc, length>;
142  defm : BinaryLoadStore<block_or2,  load, vt, oc, length>;
143  defm : BinaryLoadStore<block_xor1, load, vt, xc, length>;
144  defm : BinaryLoadStore<block_xor2, load, vt, xc, length>;
145}
146
147// Record that INSN is a LOAD AND TEST that can be used to compare
148// registers in CLS against zero.  The instruction has separate R1 and R2
149// operands, but they must be the same when the instruction is used like this.
150multiclass CompareZeroFP<Instruction insn, RegisterOperand cls> {
151  def : Pat<(z_any_fcmp cls:$reg, (fpimm0)), (insn cls:$reg, cls:$reg)>;
152  // The sign of the zero makes no difference.
153  def : Pat<(z_any_fcmp cls:$reg, (fpimmneg0)), (insn cls:$reg, cls:$reg)>;
154}
155
156// Use INSN for performing binary operation OPERATION of type VT
157// on registers of class CLS.
158class BinaryRRWithType<Instruction insn, RegisterOperand cls,
159                       SDPatternOperator operator, ValueType vt>
160  : Pat<(vt (operator cls:$x, cls:$y)), (insn cls:$x, cls:$y)>;
161
162// Use INSN to perform conversion operation OPERATOR, with the input being
163// TR2 and the output being TR1.  SUPPRESS is 4 to suppress inexact conditions
164// and 0 to allow them.  MODE is the rounding mode to use.
165class FPConversion<Instruction insn, SDPatternOperator operator, TypedReg tr1,
166                   TypedReg tr2, bits<3> suppress, bits<4> mode>
167  : Pat<(tr1.vt (operator (tr2.vt tr2.op:$vec))),
168        (insn tr2.op:$vec, suppress, mode)>;
169
170// Use INSN to perform mininum/maximum operation OPERATOR on type TR.
171// FUNCTION is the type of minimum/maximum function to perform.
172class FPMinMax<Instruction insn, SDPatternOperator operator, TypedReg tr,
173               bits<4> function>
174  : Pat<(tr.vt (operator (tr.vt tr.op:$vec1), (tr.vt tr.op:$vec2))),
175        (insn tr.op:$vec1, tr.op:$vec2, function)>;
176