RISCVAsmPrinter.cpp revision 360784 
1//===-- RISCVAsmPrinter.cpp - RISCV LLVM assembly writer ------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains a printer that converts from our internal representation
10// of machine-dependent LLVM code to the RISCV assembly language.
11//
12//===----------------------------------------------------------------------===//
13
14#include "RISCV.h"
15#include "MCTargetDesc/RISCVInstPrinter.h"
16#include "MCTargetDesc/RISCVMCExpr.h"
17#include "RISCVTargetMachine.h"
18#include "TargetInfo/RISCVTargetInfo.h"
19#include "llvm/ADT/Statistic.h"
20#include "llvm/CodeGen/AsmPrinter.h"
21#include "llvm/CodeGen/MachineConstantPool.h"
22#include "llvm/CodeGen/MachineFunctionPass.h"
23#include "llvm/CodeGen/MachineInstr.h"
24#include "llvm/CodeGen/MachineModuleInfo.h"
25#include "llvm/MC/MCAsmInfo.h"
26#include "llvm/MC/MCInst.h"
27#include "llvm/MC/MCStreamer.h"
28#include "llvm/MC/MCSymbol.h"
29#include "llvm/Support/TargetRegistry.h"
30#include "llvm/Support/raw_ostream.h"
31using namespace llvm;
32
33#define DEBUG_TYPE "asm-printer"
34
35STATISTIC(RISCVNumInstrsCompressed,
36          "Number of RISC-V Compressed instructions emitted");
37
38namespace {
39class RISCVAsmPrinter : public AsmPrinter {
40public:
41  explicit RISCVAsmPrinter(TargetMachine &TM,
42                           std::unique_ptr<MCStreamer> Streamer)
43      : AsmPrinter(TM, std::move(Streamer)) {}
44
45  StringRef getPassName() const override { return "RISCV Assembly Printer"; }
46
47  void EmitInstruction(const MachineInstr *MI) override;
48
49  bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
50                       const char *ExtraCode, raw_ostream &OS) override;
51  bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
52                             const char *ExtraCode, raw_ostream &OS) override;
53
54  void EmitToStreamer(MCStreamer &S, const MCInst &Inst);
55  bool emitPseudoExpansionLowering(MCStreamer &OutStreamer,
56                                   const MachineInstr *MI);
57
58  // Wrapper needed for tblgenned pseudo lowering.
59  bool lowerOperand(const MachineOperand &MO, MCOperand &MCOp) const {
60    return LowerRISCVMachineOperandToMCOperand(MO, MCOp, *this);
61  }
62};
63}
64
65#define GEN_COMPRESS_INSTR
66#include "RISCVGenCompressInstEmitter.inc"
67void RISCVAsmPrinter::EmitToStreamer(MCStreamer &S, const MCInst &Inst) {
68  MCInst CInst;
69  bool Res = compressInst(CInst, Inst, *TM.getMCSubtargetInfo(),
70                          OutStreamer->getContext());
71  if (Res)
72    ++RISCVNumInstrsCompressed;
73  AsmPrinter::EmitToStreamer(*OutStreamer, Res ? CInst : Inst);
74}
75
76// Simple pseudo-instructions have their lowering (with expansion to real
77// instructions) auto-generated.
78#include "RISCVGenMCPseudoLowering.inc"
79
80void RISCVAsmPrinter::EmitInstruction(const MachineInstr *MI) {
81  // Do any auto-generated pseudo lowerings.
82  if (emitPseudoExpansionLowering(*OutStreamer, MI))
83    return;
84
85  MCInst TmpInst;
86  LowerRISCVMachineInstrToMCInst(MI, TmpInst, *this);
87  EmitToStreamer(*OutStreamer, TmpInst);
88}
89
90bool RISCVAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
91                                      const char *ExtraCode, raw_ostream &OS) {
92  // First try the generic code, which knows about modifiers like 'c' and 'n'.
93  if (!AsmPrinter::PrintAsmOperand(MI, OpNo, ExtraCode, OS))
94    return false;
95
96  const MachineOperand &MO = MI->getOperand(OpNo);
97  if (ExtraCode && ExtraCode[0]) {
98    if (ExtraCode[1] != 0)
99      return true; // Unknown modifier.
100
101    switch (ExtraCode[0]) {
102    default:
103      return true; // Unknown modifier.
104    case 'z':      // Print zero register if zero, regular printing otherwise.
105      if (MO.isImm() && MO.getImm() == 0) {
106        OS << RISCVInstPrinter::getRegisterName(RISCV::X0);
107        return false;
108      }
109      break;
110    case 'i': // Literal 'i' if operand is not a register.
111      if (!MO.isReg())
112        OS << 'i';
113      return false;
114    }
115  }
116
117  switch (MO.getType()) {
118  case MachineOperand::MO_Immediate:
119    OS << MO.getImm();
120    return false;
121  case MachineOperand::MO_Register:
122    OS << RISCVInstPrinter::getRegisterName(MO.getReg());
123    return false;
124  case MachineOperand::MO_GlobalAddress:
125    PrintSymbolOperand(MO, OS);
126    return false;
127  case MachineOperand::MO_BlockAddress: {
128    MCSymbol *Sym = GetBlockAddressSymbol(MO.getBlockAddress());
129    Sym->print(OS, MAI);
130    return false;
131  }
132  default:
133    break;
134  }
135
136  return true;
137}
138
139bool RISCVAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
140                                            unsigned OpNo,
141                                            const char *ExtraCode,
142                                            raw_ostream &OS) {
143  if (!ExtraCode) {
144    const MachineOperand &MO = MI->getOperand(OpNo);
145    // For now, we only support register memory operands in registers and
146    // assume there is no addend
147    if (!MO.isReg())
148      return true;
149
150    OS << "0(" << RISCVInstPrinter::getRegisterName(MO.getReg()) << ")";
151    return false;
152  }
153
154  return AsmPrinter::PrintAsmMemoryOperand(MI, OpNo, ExtraCode, OS);
155}
156
157// Force static initialization.
158extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVAsmPrinter() {
159  RegisterAsmPrinter<RISCVAsmPrinter> X(getTheRISCV32Target());
160  RegisterAsmPrinter<RISCVAsmPrinter> Y(getTheRISCV64Target());
161}
162