RISCVMCTargetDesc.cpp revision 360784 
1//===-- RISCVMCTargetDesc.cpp - RISCV Target Descriptions -----------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8///
9/// This file provides RISCV-specific target descriptions.
10///
11//===----------------------------------------------------------------------===//
12
13#include "RISCVMCTargetDesc.h"
14#include "RISCVELFStreamer.h"
15#include "RISCVInstPrinter.h"
16#include "RISCVMCAsmInfo.h"
17#include "RISCVTargetStreamer.h"
18#include "TargetInfo/RISCVTargetInfo.h"
19#include "Utils/RISCVBaseInfo.h"
20#include "llvm/ADT/STLExtras.h"
21#include "llvm/CodeGen/Register.h"
22#include "llvm/MC/MCAsmInfo.h"
23#include "llvm/MC/MCInstrInfo.h"
24#include "llvm/MC/MCRegisterInfo.h"
25#include "llvm/MC/MCStreamer.h"
26#include "llvm/MC/MCSubtargetInfo.h"
27#include "llvm/Support/ErrorHandling.h"
28#include "llvm/Support/TargetRegistry.h"
29
30#define GET_INSTRINFO_MC_DESC
31#include "RISCVGenInstrInfo.inc"
32
33#define GET_REGINFO_MC_DESC
34#include "RISCVGenRegisterInfo.inc"
35
36#define GET_SUBTARGETINFO_MC_DESC
37#include "RISCVGenSubtargetInfo.inc"
38
39using namespace llvm;
40
41static MCInstrInfo *createRISCVMCInstrInfo() {
42  MCInstrInfo *X = new MCInstrInfo();
43  InitRISCVMCInstrInfo(X);
44  return X;
45}
46
47static MCRegisterInfo *createRISCVMCRegisterInfo(const Triple &TT) {
48  MCRegisterInfo *X = new MCRegisterInfo();
49  InitRISCVMCRegisterInfo(X, RISCV::X1);
50  return X;
51}
52
53static MCAsmInfo *createRISCVMCAsmInfo(const MCRegisterInfo &MRI,
54                                       const Triple &TT,
55                                       const MCTargetOptions &Options) {
56  MCAsmInfo *MAI = new RISCVMCAsmInfo(TT);
57
58  Register SP = MRI.getDwarfRegNum(RISCV::X2, true);
59  MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, SP, 0);
60  MAI->addInitialFrameState(Inst);
61
62  return MAI;
63}
64
65static MCSubtargetInfo *createRISCVMCSubtargetInfo(const Triple &TT,
66                                                   StringRef CPU, StringRef FS) {
67  std::string CPUName = CPU;
68  if (CPUName.empty())
69    CPUName = TT.isArch64Bit() ? "generic-rv64" : "generic-rv32";
70  return createRISCVMCSubtargetInfoImpl(TT, CPUName, FS);
71}
72
73static MCInstPrinter *createRISCVMCInstPrinter(const Triple &T,
74                                               unsigned SyntaxVariant,
75                                               const MCAsmInfo &MAI,
76                                               const MCInstrInfo &MII,
77                                               const MCRegisterInfo &MRI) {
78  return new RISCVInstPrinter(MAI, MII, MRI);
79}
80
81static MCTargetStreamer *
82createRISCVObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) {
83  const Triple &TT = STI.getTargetTriple();
84  if (TT.isOSBinFormatELF())
85    return new RISCVTargetELFStreamer(S, STI);
86  return nullptr;
87}
88
89static MCTargetStreamer *createRISCVAsmTargetStreamer(MCStreamer &S,
90                                                      formatted_raw_ostream &OS,
91                                                      MCInstPrinter *InstPrint,
92                                                      bool isVerboseAsm) {
93  return new RISCVTargetAsmStreamer(S, OS);
94}
95
96extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTargetMC() {
97  for (Target *T : {&getTheRISCV32Target(), &getTheRISCV64Target()}) {
98    TargetRegistry::RegisterMCAsmInfo(*T, createRISCVMCAsmInfo);
99    TargetRegistry::RegisterMCInstrInfo(*T, createRISCVMCInstrInfo);
100    TargetRegistry::RegisterMCRegInfo(*T, createRISCVMCRegisterInfo);
101    TargetRegistry::RegisterMCAsmBackend(*T, createRISCVAsmBackend);
102    TargetRegistry::RegisterMCCodeEmitter(*T, createRISCVMCCodeEmitter);
103    TargetRegistry::RegisterMCInstPrinter(*T, createRISCVMCInstPrinter);
104    TargetRegistry::RegisterMCSubtargetInfo(*T, createRISCVMCSubtargetInfo);
105    TargetRegistry::RegisterObjectTargetStreamer(
106        *T, createRISCVObjectTargetStreamer);
107
108    // Register the asm target streamer.
109    TargetRegistry::RegisterAsmTargetStreamer(*T, createRISCVAsmTargetStreamer);
110  }
111}
112