PPCRegisterInfo.h revision 360784 
1//===-- PPCRegisterInfo.h - PowerPC Register Information Impl ---*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the PowerPC implementation of the TargetRegisterInfo
10// class.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_POWERPC_PPCREGISTERINFO_H
15#define LLVM_LIB_TARGET_POWERPC_PPCREGISTERINFO_H
16
17#include "MCTargetDesc/PPCMCTargetDesc.h"
18#include "llvm/ADT/DenseMap.h"
19
20#define GET_REGINFO_HEADER
21#include "PPCGenRegisterInfo.inc"
22
23namespace llvm {
24class PPCTargetMachine;
25
26inline static unsigned getCRFromCRBit(unsigned SrcReg) {
27  unsigned Reg = 0;
28  if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR0GT ||
29      SrcReg == PPC::CR0EQ || SrcReg == PPC::CR0UN)
30    Reg = PPC::CR0;
31  else if (SrcReg == PPC::CR1LT || SrcReg == PPC::CR1GT ||
32           SrcReg == PPC::CR1EQ || SrcReg == PPC::CR1UN)
33    Reg = PPC::CR1;
34  else if (SrcReg == PPC::CR2LT || SrcReg == PPC::CR2GT ||
35           SrcReg == PPC::CR2EQ || SrcReg == PPC::CR2UN)
36    Reg = PPC::CR2;
37  else if (SrcReg == PPC::CR3LT || SrcReg == PPC::CR3GT ||
38           SrcReg == PPC::CR3EQ || SrcReg == PPC::CR3UN)
39    Reg = PPC::CR3;
40  else if (SrcReg == PPC::CR4LT || SrcReg == PPC::CR4GT ||
41           SrcReg == PPC::CR4EQ || SrcReg == PPC::CR4UN)
42    Reg = PPC::CR4;
43  else if (SrcReg == PPC::CR5LT || SrcReg == PPC::CR5GT ||
44           SrcReg == PPC::CR5EQ || SrcReg == PPC::CR5UN)
45    Reg = PPC::CR5;
46  else if (SrcReg == PPC::CR6LT || SrcReg == PPC::CR6GT ||
47           SrcReg == PPC::CR6EQ || SrcReg == PPC::CR6UN)
48    Reg = PPC::CR6;
49  else if (SrcReg == PPC::CR7LT || SrcReg == PPC::CR7GT ||
50           SrcReg == PPC::CR7EQ || SrcReg == PPC::CR7UN)
51    Reg = PPC::CR7;
52
53  assert(Reg != 0 && "Invalid CR bit register");
54  return Reg;
55}
56
57class PPCRegisterInfo : public PPCGenRegisterInfo {
58  DenseMap<unsigned, unsigned> ImmToIdxMap;
59  const PPCTargetMachine &TM;
60
61public:
62  PPCRegisterInfo(const PPCTargetMachine &TM);
63
64  /// getMappedIdxOpcForImmOpc - Return the mapped index form load/store opcode
65  /// for a given imm form load/store opcode \p ImmFormOpcode.
66  /// FIXME: move this to PPCInstrInfo class.
67  unsigned getMappedIdxOpcForImmOpc(unsigned ImmOpcode) const {
68    if (!ImmToIdxMap.count(ImmOpcode))
69      return PPC::INSTRUCTION_LIST_END;
70    return ImmToIdxMap.find(ImmOpcode)->second;
71  }
72
73  /// getPointerRegClass - Return the register class to use to hold pointers.
74  /// This is used for addressing modes.
75  const TargetRegisterClass *
76  getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override;
77
78  unsigned getRegPressureLimit(const TargetRegisterClass *RC,
79                               MachineFunction &MF) const override;
80
81  const TargetRegisterClass *
82  getLargestLegalSuperClass(const TargetRegisterClass *RC,
83                            const MachineFunction &MF) const override;
84
85  /// Code Generation virtual methods...
86  const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
87  const MCPhysReg *getCalleeSavedRegsViaCopy(const MachineFunction *MF) const;
88  const uint32_t *getCallPreservedMask(const MachineFunction &MF,
89                                       CallingConv::ID CC) const override;
90  const uint32_t *getNoPreservedMask() const override;
91
92  void adjustStackMapLiveOutMask(uint32_t *Mask) const override;
93
94  BitVector getReservedRegs(const MachineFunction &MF) const override;
95  bool isCallerPreservedPhysReg(unsigned PhysReg, const MachineFunction &MF) const override;
96
97  /// We require the register scavenger.
98  bool requiresRegisterScavenging(const MachineFunction &MF) const override {
99    return true;
100  }
101
102  bool requiresFrameIndexScavenging(const MachineFunction &MF) const override;
103
104  bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override {
105    return true;
106  }
107
108  bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override {
109    return true;
110  }
111
112  void lowerDynamicAlloc(MachineBasicBlock::iterator II) const;
113  void lowerDynamicAreaOffset(MachineBasicBlock::iterator II) const;
114  void lowerCRSpilling(MachineBasicBlock::iterator II,
115                       unsigned FrameIndex) const;
116  void lowerCRRestore(MachineBasicBlock::iterator II,
117                      unsigned FrameIndex) const;
118  void lowerCRBitSpilling(MachineBasicBlock::iterator II,
119                          unsigned FrameIndex) const;
120  void lowerCRBitRestore(MachineBasicBlock::iterator II,
121                         unsigned FrameIndex) const;
122  void lowerVRSAVESpilling(MachineBasicBlock::iterator II,
123                           unsigned FrameIndex) const;
124  void lowerVRSAVERestore(MachineBasicBlock::iterator II,
125                          unsigned FrameIndex) const;
126
127  bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg,
128                            int &FrameIdx) const override;
129  void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
130                           unsigned FIOperandNum,
131                           RegScavenger *RS = nullptr) const override;
132
133  // Support for virtual base registers.
134  bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override;
135  void materializeFrameBaseRegister(MachineBasicBlock *MBB,
136                                    unsigned BaseReg, int FrameIdx,
137                                    int64_t Offset) const override;
138  void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
139                         int64_t Offset) const override;
140  bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg,
141                          int64_t Offset) const override;
142
143  // Debug information queries.
144  Register getFrameRegister(const MachineFunction &MF) const override;
145
146  // Base pointer (stack realignment) support.
147  Register getBaseRegister(const MachineFunction &MF) const;
148  bool hasBasePointer(const MachineFunction &MF) const;
149
150  /// stripRegisterPrefix - This method strips the character prefix from a
151  /// register name so that only the number is left.  Used by for linux asm.
152  static const char *stripRegisterPrefix(const char *RegName) {
153    switch (RegName[0]) {
154      case 'r':
155      case 'f':
156      case 'q': // for QPX
157      case 'v':
158        if (RegName[1] == 's')
159          return RegName + 2;
160        return RegName + 1;
161      case 'c': if (RegName[1] == 'r') return RegName + 2;
162    }
163
164    return RegName;
165  }
166};
167
168} // end namespace llvm
169
170#endif
171