PPCInstr64Bit.td revision 360784
1//===-- PPCInstr64Bit.td - The PowerPC 64-bit Support ------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the PowerPC 64-bit instructions. These patterns are used 10// both when in ppc64 mode and when in "use 64-bit extensions in 32-bit" mode. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// 64-bit operands. 16// 17def s16imm64 : Operand<i64> { 18 let PrintMethod = "printS16ImmOperand"; 19 let EncoderMethod = "getImm16Encoding"; 20 let ParserMatchClass = PPCS16ImmAsmOperand; 21 let DecoderMethod = "decodeSImmOperand<16>"; 22} 23def u16imm64 : Operand<i64> { 24 let PrintMethod = "printU16ImmOperand"; 25 let EncoderMethod = "getImm16Encoding"; 26 let ParserMatchClass = PPCU16ImmAsmOperand; 27 let DecoderMethod = "decodeUImmOperand<16>"; 28} 29def s17imm64 : Operand<i64> { 30 // This operand type is used for addis/lis to allow the assembler parser 31 // to accept immediates in the range -65536..65535 for compatibility with 32 // the GNU assembler. The operand is treated as 16-bit otherwise. 33 let PrintMethod = "printS16ImmOperand"; 34 let EncoderMethod = "getImm16Encoding"; 35 let ParserMatchClass = PPCS17ImmAsmOperand; 36 let DecoderMethod = "decodeSImmOperand<16>"; 37} 38def tocentry : Operand<iPTR> { 39 let MIOperandInfo = (ops i64imm:$imm); 40} 41def tlsreg : Operand<i64> { 42 let EncoderMethod = "getTLSRegEncoding"; 43 let ParserMatchClass = PPCTLSRegOperand; 44} 45def tlsgd : Operand<i64> {} 46def tlscall : Operand<i64> { 47 let PrintMethod = "printTLSCall"; 48 let MIOperandInfo = (ops calltarget:$func, tlsgd:$sym); 49 let EncoderMethod = "getTLSCallEncoding"; 50} 51 52//===----------------------------------------------------------------------===// 53// 64-bit transformation functions. 54// 55 56def SHL64 : SDNodeXForm<imm, [{ 57 // Transformation function: 63 - imm 58 return getI32Imm(63 - N->getZExtValue(), SDLoc(N)); 59}]>; 60 61def SRL64 : SDNodeXForm<imm, [{ 62 // Transformation function: 64 - imm 63 return N->getZExtValue() ? getI32Imm(64 - N->getZExtValue(), SDLoc(N)) 64 : getI32Imm(0, SDLoc(N)); 65}]>; 66 67 68//===----------------------------------------------------------------------===// 69// Calls. 70// 71 72let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 73let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in { 74 let isReturn = 1, isPredicable = 1, Uses = [LR8, RM] in 75 def BLR8 : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB, 76 [(retflag)]>, Requires<[In64BitMode]>; 77 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR8] in { 78 let isPredicable = 1 in 79 def BCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB, 80 []>, 81 Requires<[In64BitMode]>; 82 def BCCCTR8 : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond), 83 "b${cond:cc}ctr${cond:pm} ${cond:reg}", IIC_BrB, 84 []>, 85 Requires<[In64BitMode]>; 86 87 def BCCTR8 : XLForm_2_br2<19, 528, 12, 0, (outs), (ins crbitrc:$bi), 88 "bcctr 12, $bi, 0", IIC_BrB, []>, 89 Requires<[In64BitMode]>; 90 def BCCTR8n : XLForm_2_br2<19, 528, 4, 0, (outs), (ins crbitrc:$bi), 91 "bcctr 4, $bi, 0", IIC_BrB, []>, 92 Requires<[In64BitMode]>; 93 } 94} 95 96let Defs = [LR8] in 97 def MovePCtoLR8 : PPCEmitTimePseudo<(outs), (ins), "#MovePCtoLR8", []>, 98 PPC970_Unit_BRU; 99 100let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in { 101 let Defs = [CTR8], Uses = [CTR8] in { 102 def BDZ8 : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst), 103 "bdz $dst">; 104 def BDNZ8 : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst), 105 "bdnz $dst">; 106 } 107 108 let isReturn = 1, Defs = [CTR8], Uses = [CTR8, LR8, RM] in { 109 def BDZLR8 : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins), 110 "bdzlr", IIC_BrB, []>; 111 def BDNZLR8 : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins), 112 "bdnzlr", IIC_BrB, []>; 113 } 114} 115 116 117 118let isCall = 1, PPC970_Unit = 7, Defs = [LR8] in { 119 // Convenient aliases for call instructions 120 let Uses = [RM] in { 121 def BL8 : IForm<18, 0, 1, (outs), (ins calltarget:$func), 122 "bl $func", IIC_BrB, []>; // See Pat patterns below. 123 124 def BL8_TLS : IForm<18, 0, 1, (outs), (ins tlscall:$func), 125 "bl $func", IIC_BrB, []>; 126 127 def BLA8 : IForm<18, 1, 1, (outs), (ins abscalltarget:$func), 128 "bla $func", IIC_BrB, [(PPCcall (i64 imm:$func))]>; 129 } 130 let Uses = [RM], isCodeGenOnly = 1 in { 131 def BL8_NOP : IForm_and_DForm_4_zero<18, 0, 1, 24, 132 (outs), (ins calltarget:$func), 133 "bl $func\n\tnop", IIC_BrB, []>; 134 135 def BL8_NOP_TLS : IForm_and_DForm_4_zero<18, 0, 1, 24, 136 (outs), (ins tlscall:$func), 137 "bl $func\n\tnop", IIC_BrB, []>; 138 139 def BLA8_NOP : IForm_and_DForm_4_zero<18, 1, 1, 24, 140 (outs), (ins abscalltarget:$func), 141 "bla $func\n\tnop", IIC_BrB, 142 [(PPCcall_nop (i64 imm:$func))]>; 143 } 144 let Uses = [CTR8, RM] in { 145 let isPredicable = 1 in 146 def BCTRL8 : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins), 147 "bctrl", IIC_BrB, [(PPCbctrl)]>, 148 Requires<[In64BitMode]>; 149 150 let isCodeGenOnly = 1 in { 151 def BCCCTRL8 : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond), 152 "b${cond:cc}ctrl${cond:pm} ${cond:reg}", IIC_BrB, 153 []>, 154 Requires<[In64BitMode]>; 155 156 def BCCTRL8 : XLForm_2_br2<19, 528, 12, 1, (outs), (ins crbitrc:$bi), 157 "bcctrl 12, $bi, 0", IIC_BrB, []>, 158 Requires<[In64BitMode]>; 159 def BCCTRL8n : XLForm_2_br2<19, 528, 4, 1, (outs), (ins crbitrc:$bi), 160 "bcctrl 4, $bi, 0", IIC_BrB, []>, 161 Requires<[In64BitMode]>; 162 } 163 } 164} 165 166let isCall = 1, PPC970_Unit = 7, isCodeGenOnly = 1, 167 Defs = [LR8, X2], Uses = [CTR8, RM], RST = 2 in { 168 def BCTRL8_LDinto_toc : 169 XLForm_2_ext_and_DSForm_1<19, 528, 20, 0, 1, 58, 0, (outs), 170 (ins memrix:$src), 171 "bctrl\n\tld 2, $src", IIC_BrB, 172 [(PPCbctrl_load_toc iaddrX4:$src)]>, 173 Requires<[In64BitMode]>; 174} 175 176} // Interpretation64Bit 177 178// FIXME: Duplicating this for the asm parser should be unnecessary, but the 179// previous definition must be marked as CodeGen only to prevent decoding 180// conflicts. 181let Interpretation64Bit = 1, isAsmParserOnly = 1 in 182let isCall = 1, PPC970_Unit = 7, Defs = [LR8], Uses = [RM] in 183def BL8_TLS_ : IForm<18, 0, 1, (outs), (ins tlscall:$func), 184 "bl $func", IIC_BrB, []>; 185 186// Calls 187def : Pat<(PPCcall (i64 tglobaladdr:$dst)), 188 (BL8 tglobaladdr:$dst)>; 189def : Pat<(PPCcall_nop (i64 tglobaladdr:$dst)), 190 (BL8_NOP tglobaladdr:$dst)>; 191 192def : Pat<(PPCcall (i64 texternalsym:$dst)), 193 (BL8 texternalsym:$dst)>; 194def : Pat<(PPCcall_nop (i64 texternalsym:$dst)), 195 (BL8_NOP texternalsym:$dst)>; 196 197// Calls for AIX 198def : Pat<(PPCcall (i64 mcsym:$dst)), 199 (BL8 mcsym:$dst)>; 200def : Pat<(PPCcall_nop (i64 mcsym:$dst)), 201 (BL8_NOP mcsym:$dst)>; 202 203// Atomic operations 204// FIXME: some of these might be used with constant operands. This will result 205// in constant materialization instructions that may be redundant. We currently 206// clean this up in PPCMIPeephole with calls to 207// PPCInstrInfo::convertToImmediateForm() but we should probably not emit them 208// in the first place. 209let Defs = [CR0] in { 210 def ATOMIC_LOAD_ADD_I64 : PPCCustomInserterPseudo< 211 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_ADD_I64", 212 [(set i64:$dst, (atomic_load_add_64 xoaddr:$ptr, i64:$incr))]>; 213 def ATOMIC_LOAD_SUB_I64 : PPCCustomInserterPseudo< 214 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_SUB_I64", 215 [(set i64:$dst, (atomic_load_sub_64 xoaddr:$ptr, i64:$incr))]>; 216 def ATOMIC_LOAD_OR_I64 : PPCCustomInserterPseudo< 217 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_OR_I64", 218 [(set i64:$dst, (atomic_load_or_64 xoaddr:$ptr, i64:$incr))]>; 219 def ATOMIC_LOAD_XOR_I64 : PPCCustomInserterPseudo< 220 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_XOR_I64", 221 [(set i64:$dst, (atomic_load_xor_64 xoaddr:$ptr, i64:$incr))]>; 222 def ATOMIC_LOAD_AND_I64 : PPCCustomInserterPseudo< 223 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_AND_i64", 224 [(set i64:$dst, (atomic_load_and_64 xoaddr:$ptr, i64:$incr))]>; 225 def ATOMIC_LOAD_NAND_I64 : PPCCustomInserterPseudo< 226 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_NAND_I64", 227 [(set i64:$dst, (atomic_load_nand_64 xoaddr:$ptr, i64:$incr))]>; 228 def ATOMIC_LOAD_MIN_I64 : PPCCustomInserterPseudo< 229 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_MIN_I64", 230 [(set i64:$dst, (atomic_load_min_64 xoaddr:$ptr, i64:$incr))]>; 231 def ATOMIC_LOAD_MAX_I64 : PPCCustomInserterPseudo< 232 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_MAX_I64", 233 [(set i64:$dst, (atomic_load_max_64 xoaddr:$ptr, i64:$incr))]>; 234 def ATOMIC_LOAD_UMIN_I64 : PPCCustomInserterPseudo< 235 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_UMIN_I64", 236 [(set i64:$dst, (atomic_load_umin_64 xoaddr:$ptr, i64:$incr))]>; 237 def ATOMIC_LOAD_UMAX_I64 : PPCCustomInserterPseudo< 238 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_UMAX_I64", 239 [(set i64:$dst, (atomic_load_umax_64 xoaddr:$ptr, i64:$incr))]>; 240 241 def ATOMIC_CMP_SWAP_I64 : PPCCustomInserterPseudo< 242 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$old, g8rc:$new), "#ATOMIC_CMP_SWAP_I64", 243 [(set i64:$dst, (atomic_cmp_swap_64 xoaddr:$ptr, i64:$old, i64:$new))]>; 244 245 def ATOMIC_SWAP_I64 : PPCCustomInserterPseudo< 246 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$new), "#ATOMIC_SWAP_I64", 247 [(set i64:$dst, (atomic_swap_64 xoaddr:$ptr, i64:$new))]>; 248} 249 250// Instructions to support atomic operations 251let mayLoad = 1, hasSideEffects = 0 in { 252def LDARX : XForm_1_memOp<31, 84, (outs g8rc:$rD), (ins memrr:$ptr), 253 "ldarx $rD, $ptr", IIC_LdStLDARX, []>; 254 255// Instruction to support lock versions of atomics 256// (EH=1 - see Power ISA 2.07 Book II 4.4.2) 257def LDARXL : XForm_1<31, 84, (outs g8rc:$rD), (ins memrr:$ptr), 258 "ldarx $rD, $ptr, 1", IIC_LdStLDARX, []>, isRecordForm; 259 260let hasExtraDefRegAllocReq = 1 in 261def LDAT : X_RD5_RS5_IM5<31, 614, (outs g8rc:$rD), (ins g8rc:$rA, u5imm:$FC), 262 "ldat $rD, $rA, $FC", IIC_LdStLoad>, isPPC64, 263 Requires<[IsISA3_0]>; 264} 265 266let Defs = [CR0], mayStore = 1, mayLoad = 0, hasSideEffects = 0 in 267def STDCX : XForm_1_memOp<31, 214, (outs), (ins g8rc:$rS, memrr:$dst), 268 "stdcx. $rS, $dst", IIC_LdStSTDCX, []>, isRecordForm; 269 270let mayStore = 1, mayLoad = 0, hasSideEffects = 0 in 271def STDAT : X_RD5_RS5_IM5<31, 742, (outs), (ins g8rc:$rS, g8rc:$rA, u5imm:$FC), 272 "stdat $rS, $rA, $FC", IIC_LdStStore>, isPPC64, 273 Requires<[IsISA3_0]>; 274 275let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 276let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 277def TCRETURNdi8 :PPCEmitTimePseudo< (outs), 278 (ins calltarget:$dst, i32imm:$offset), 279 "#TC_RETURNd8 $dst $offset", 280 []>; 281 282let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 283def TCRETURNai8 :PPCEmitTimePseudo<(outs), (ins abscalltarget:$func, i32imm:$offset), 284 "#TC_RETURNa8 $func $offset", 285 [(PPCtc_return (i64 imm:$func), imm:$offset)]>; 286 287let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 288def TCRETURNri8 : PPCEmitTimePseudo<(outs), (ins CTRRC8:$dst, i32imm:$offset), 289 "#TC_RETURNr8 $dst $offset", 290 []>; 291 292let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1, 293 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR8, RM] in 294def TAILBCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB, 295 []>, 296 Requires<[In64BitMode]>; 297 298let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 299 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 300def TAILB8 : IForm<18, 0, 0, (outs), (ins calltarget:$dst), 301 "b $dst", IIC_BrB, 302 []>; 303 304let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 305 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 306def TAILBA8 : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst), 307 "ba $dst", IIC_BrB, 308 []>; 309} // Interpretation64Bit 310 311def : Pat<(PPCtc_return (i64 tglobaladdr:$dst), imm:$imm), 312 (TCRETURNdi8 tglobaladdr:$dst, imm:$imm)>; 313 314def : Pat<(PPCtc_return (i64 texternalsym:$dst), imm:$imm), 315 (TCRETURNdi8 texternalsym:$dst, imm:$imm)>; 316 317def : Pat<(PPCtc_return CTRRC8:$dst, imm:$imm), 318 (TCRETURNri8 CTRRC8:$dst, imm:$imm)>; 319 320 321// 64-bit CR instructions 322let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 323let hasSideEffects = 0 in { 324// mtocrf's input needs to be prepared by shifting by an amount dependent 325// on the cr register selected. Thus, post-ra anti-dep breaking must not 326// later change that register assignment. 327let hasExtraDefRegAllocReq = 1 in { 328def MTOCRF8: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins g8rc:$ST), 329 "mtocrf $FXM, $ST", IIC_BrMCRX>, 330 PPC970_DGroup_First, PPC970_Unit_CRU; 331 332// Similarly to mtocrf, the mask for mtcrf must be prepared in a way that 333// is dependent on the cr fields being set. 334def MTCRF8 : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, g8rc:$rS), 335 "mtcrf $FXM, $rS", IIC_BrMCRX>, 336 PPC970_MicroCode, PPC970_Unit_CRU; 337} // hasExtraDefRegAllocReq = 1 338 339// mfocrf's input needs to be prepared by shifting by an amount dependent 340// on the cr register selected. Thus, post-ra anti-dep breaking must not 341// later change that register assignment. 342let hasExtraSrcRegAllocReq = 1 in { 343def MFOCRF8: XFXForm_5a<31, 19, (outs g8rc:$rT), (ins crbitm:$FXM), 344 "mfocrf $rT, $FXM", IIC_SprMFCRF>, 345 PPC970_DGroup_First, PPC970_Unit_CRU; 346 347// Similarly to mfocrf, the mask for mfcrf must be prepared in a way that 348// is dependent on the cr fields being copied. 349def MFCR8 : XFXForm_3<31, 19, (outs g8rc:$rT), (ins), 350 "mfcr $rT", IIC_SprMFCR>, 351 PPC970_MicroCode, PPC970_Unit_CRU; 352} // hasExtraSrcRegAllocReq = 1 353} // hasSideEffects = 0 354 355// While longjmp is a control-flow barrier (fallthrough isn't allowed), setjmp 356// is not. 357let hasSideEffects = 1 in { 358 let Defs = [CTR8] in 359 def EH_SjLj_SetJmp64 : PPCCustomInserterPseudo<(outs gprc:$dst), (ins memr:$buf), 360 "#EH_SJLJ_SETJMP64", 361 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>, 362 Requires<[In64BitMode]>; 363} 364 365let hasSideEffects = 1, isBarrier = 1 in { 366 let isTerminator = 1 in 367 def EH_SjLj_LongJmp64 : PPCCustomInserterPseudo<(outs), (ins memr:$buf), 368 "#EH_SJLJ_LONGJMP64", 369 [(PPCeh_sjlj_longjmp addr:$buf)]>, 370 Requires<[In64BitMode]>; 371} 372 373def MFSPR8 : XFXForm_1<31, 339, (outs g8rc:$RT), (ins i32imm:$SPR), 374 "mfspr $RT, $SPR", IIC_SprMFSPR>; 375def MTSPR8 : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, g8rc:$RT), 376 "mtspr $SPR, $RT", IIC_SprMTSPR>; 377 378 379//===----------------------------------------------------------------------===// 380// 64-bit SPR manipulation instrs. 381 382let Uses = [CTR8] in { 383def MFCTR8 : XFXForm_1_ext<31, 339, 9, (outs g8rc:$rT), (ins), 384 "mfctr $rT", IIC_SprMFSPR>, 385 PPC970_DGroup_First, PPC970_Unit_FXU; 386} 387let Pattern = [(PPCmtctr i64:$rS)], Defs = [CTR8] in { 388def MTCTR8 : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS), 389 "mtctr $rS", IIC_SprMTSPR>, 390 PPC970_DGroup_First, PPC970_Unit_FXU; 391} 392let hasSideEffects = 1, Defs = [CTR8] in { 393let Pattern = [(int_set_loop_iterations i64:$rS)] in 394def MTCTR8loop : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS), 395 "mtctr $rS", IIC_SprMTSPR>, 396 PPC970_DGroup_First, PPC970_Unit_FXU; 397} 398 399let Pattern = [(set i64:$rT, readcyclecounter)] in 400def MFTB8 : XFXForm_1_ext<31, 339, 268, (outs g8rc:$rT), (ins), 401 "mfspr $rT, 268", IIC_SprMFTB>, 402 PPC970_DGroup_First, PPC970_Unit_FXU; 403// Note that encoding mftb using mfspr is now the preferred form, 404// and has been since at least ISA v2.03. The mftb instruction has 405// now been phased out. Using mfspr, however, is known not to work on 406// the POWER3. 407 408let Defs = [X1], Uses = [X1] in 409def DYNALLOC8 : PPCEmitTimePseudo<(outs g8rc:$result), (ins g8rc:$negsize, memri:$fpsi),"#DYNALLOC8", 410 [(set i64:$result, 411 (PPCdynalloc i64:$negsize, iaddr:$fpsi))]>; 412def DYNAREAOFFSET8 : PPCEmitTimePseudo<(outs i64imm:$result), (ins memri:$fpsi), "#DYNAREAOFFSET8", 413 [(set i64:$result, (PPCdynareaoffset iaddr:$fpsi))]>; 414 415let hasSideEffects = 0 in { 416let Defs = [LR8] in { 417def MTLR8 : XFXForm_7_ext<31, 467, 8, (outs), (ins g8rc:$rS), 418 "mtlr $rS", IIC_SprMTSPR>, 419 PPC970_DGroup_First, PPC970_Unit_FXU; 420} 421let Uses = [LR8] in { 422def MFLR8 : XFXForm_1_ext<31, 339, 8, (outs g8rc:$rT), (ins), 423 "mflr $rT", IIC_SprMFSPR>, 424 PPC970_DGroup_First, PPC970_Unit_FXU; 425} 426} // Interpretation64Bit 427} 428 429//===----------------------------------------------------------------------===// 430// Fixed point instructions. 431// 432 433let PPC970_Unit = 1 in { // FXU Operations. 434let Interpretation64Bit = 1 in { 435let hasSideEffects = 0 in { 436let isCodeGenOnly = 1 in { 437 438let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in { 439def LI8 : DForm_2_r0<14, (outs g8rc:$rD), (ins s16imm64:$imm), 440 "li $rD, $imm", IIC_IntSimple, 441 [(set i64:$rD, imm64SExt16:$imm)]>; 442def LIS8 : DForm_2_r0<15, (outs g8rc:$rD), (ins s17imm64:$imm), 443 "lis $rD, $imm", IIC_IntSimple, 444 [(set i64:$rD, imm16ShiftedSExt:$imm)]>; 445} 446 447// Logical ops. 448let isCommutable = 1 in { 449defm NAND8: XForm_6r<31, 476, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 450 "nand", "$rA, $rS, $rB", IIC_IntSimple, 451 [(set i64:$rA, (not (and i64:$rS, i64:$rB)))]>; 452defm AND8 : XForm_6r<31, 28, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 453 "and", "$rA, $rS, $rB", IIC_IntSimple, 454 [(set i64:$rA, (and i64:$rS, i64:$rB))]>; 455} // isCommutable 456defm ANDC8: XForm_6r<31, 60, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 457 "andc", "$rA, $rS, $rB", IIC_IntSimple, 458 [(set i64:$rA, (and i64:$rS, (not i64:$rB)))]>; 459let isCommutable = 1 in { 460defm OR8 : XForm_6r<31, 444, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 461 "or", "$rA, $rS, $rB", IIC_IntSimple, 462 [(set i64:$rA, (or i64:$rS, i64:$rB))]>; 463defm NOR8 : XForm_6r<31, 124, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 464 "nor", "$rA, $rS, $rB", IIC_IntSimple, 465 [(set i64:$rA, (not (or i64:$rS, i64:$rB)))]>; 466} // isCommutable 467defm ORC8 : XForm_6r<31, 412, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 468 "orc", "$rA, $rS, $rB", IIC_IntSimple, 469 [(set i64:$rA, (or i64:$rS, (not i64:$rB)))]>; 470let isCommutable = 1 in { 471defm EQV8 : XForm_6r<31, 284, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 472 "eqv", "$rA, $rS, $rB", IIC_IntSimple, 473 [(set i64:$rA, (not (xor i64:$rS, i64:$rB)))]>; 474defm XOR8 : XForm_6r<31, 316, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 475 "xor", "$rA, $rS, $rB", IIC_IntSimple, 476 [(set i64:$rA, (xor i64:$rS, i64:$rB))]>; 477} // let isCommutable = 1 478 479// Logical ops with immediate. 480let Defs = [CR0] in { 481def ANDI8_rec : DForm_4<28, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 482 "andi. $dst, $src1, $src2", IIC_IntGeneral, 483 [(set i64:$dst, (and i64:$src1, immZExt16:$src2))]>, 484 isRecordForm; 485def ANDIS8_rec : DForm_4<29, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 486 "andis. $dst, $src1, $src2", IIC_IntGeneral, 487 [(set i64:$dst, (and i64:$src1, imm16ShiftedZExt:$src2))]>, 488 isRecordForm; 489} 490def ORI8 : DForm_4<24, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 491 "ori $dst, $src1, $src2", IIC_IntSimple, 492 [(set i64:$dst, (or i64:$src1, immZExt16:$src2))]>; 493def ORIS8 : DForm_4<25, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 494 "oris $dst, $src1, $src2", IIC_IntSimple, 495 [(set i64:$dst, (or i64:$src1, imm16ShiftedZExt:$src2))]>; 496def XORI8 : DForm_4<26, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 497 "xori $dst, $src1, $src2", IIC_IntSimple, 498 [(set i64:$dst, (xor i64:$src1, immZExt16:$src2))]>; 499def XORIS8 : DForm_4<27, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 500 "xoris $dst, $src1, $src2", IIC_IntSimple, 501 [(set i64:$dst, (xor i64:$src1, imm16ShiftedZExt:$src2))]>; 502 503let isCommutable = 1 in 504defm ADD8 : XOForm_1rx<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 505 "add", "$rT, $rA, $rB", IIC_IntSimple, 506 [(set i64:$rT, (add i64:$rA, i64:$rB))]>; 507// ADD8 has a special form: reg = ADD8(reg, sym@tls) for use by the 508// initial-exec thread-local storage model. We need to forbid r0 here - 509// while it works for add just fine, the linker can relax this to local-exec 510// addi, which won't work for r0. 511def ADD8TLS : XOForm_1<31, 266, 0, (outs g8rc:$rT), (ins g8rc_nox0:$rA, tlsreg:$rB), 512 "add $rT, $rA, $rB", IIC_IntSimple, 513 [(set i64:$rT, (add i64:$rA, tglobaltlsaddr:$rB))]>; 514let mayLoad = 1 in { 515def LBZXTLS : XForm_1<31, 87, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 516 "lbzx $rD, $rA, $rB", IIC_LdStLoad, []>; 517def LHZXTLS : XForm_1<31, 279, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 518 "lhzx $rD, $rA, $rB", IIC_LdStLoad, []>; 519def LWZXTLS : XForm_1<31, 23, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 520 "lwzx $rD, $rA, $rB", IIC_LdStLoad, []>; 521def LDXTLS : XForm_1<31, 21, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 522 "ldx $rD, $rA, $rB", IIC_LdStLD, []>, isPPC64; 523def LBZXTLS_32 : XForm_1<31, 87, (outs gprc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 524 "lbzx $rD, $rA, $rB", IIC_LdStLoad, []>; 525def LHZXTLS_32 : XForm_1<31, 279, (outs gprc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 526 "lhzx $rD, $rA, $rB", IIC_LdStLoad, []>; 527def LWZXTLS_32 : XForm_1<31, 23, (outs gprc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 528 "lwzx $rD, $rA, $rB", IIC_LdStLoad, []>; 529 530} 531 532let mayStore = 1 in { 533def STBXTLS : XForm_8<31, 215, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 534 "stbx $rS, $rA, $rB", IIC_LdStStore, []>, 535 PPC970_DGroup_Cracked; 536def STHXTLS : XForm_8<31, 407, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 537 "sthx $rS, $rA, $rB", IIC_LdStStore, []>, 538 PPC970_DGroup_Cracked; 539def STWXTLS : XForm_8<31, 151, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 540 "stwx $rS, $rA, $rB", IIC_LdStStore, []>, 541 PPC970_DGroup_Cracked; 542def STDXTLS : XForm_8<31, 149, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 543 "stdx $rS, $rA, $rB", IIC_LdStSTD, []>, isPPC64, 544 PPC970_DGroup_Cracked; 545def STBXTLS_32 : XForm_8<31, 215, (outs), (ins gprc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 546 "stbx $rS, $rA, $rB", IIC_LdStStore, []>, 547 PPC970_DGroup_Cracked; 548def STHXTLS_32 : XForm_8<31, 407, (outs), (ins gprc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 549 "sthx $rS, $rA, $rB", IIC_LdStStore, []>, 550 PPC970_DGroup_Cracked; 551def STWXTLS_32 : XForm_8<31, 151, (outs), (ins gprc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 552 "stwx $rS, $rA, $rB", IIC_LdStStore, []>, 553 PPC970_DGroup_Cracked; 554 555} 556 557let isCommutable = 1 in 558defm ADDC8 : XOForm_1rc<31, 10, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 559 "addc", "$rT, $rA, $rB", IIC_IntGeneral, 560 [(set i64:$rT, (addc i64:$rA, i64:$rB))]>, 561 PPC970_DGroup_Cracked; 562 563let Defs = [CARRY] in 564def ADDIC8 : DForm_2<12, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm), 565 "addic $rD, $rA, $imm", IIC_IntGeneral, 566 [(set i64:$rD, (addc i64:$rA, imm64SExt16:$imm))]>; 567def ADDI8 : DForm_2<14, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s16imm64:$imm), 568 "addi $rD, $rA, $imm", IIC_IntSimple, 569 [(set i64:$rD, (add i64:$rA, imm64SExt16:$imm))]>; 570def ADDIS8 : DForm_2<15, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s17imm64:$imm), 571 "addis $rD, $rA, $imm", IIC_IntSimple, 572 [(set i64:$rD, (add i64:$rA, imm16ShiftedSExt:$imm))]>; 573 574let Defs = [CARRY] in { 575def SUBFIC8: DForm_2< 8, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm), 576 "subfic $rD, $rA, $imm", IIC_IntGeneral, 577 [(set i64:$rD, (subc imm64SExt16:$imm, i64:$rA))]>; 578} 579defm SUBFC8 : XOForm_1rc<31, 8, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 580 "subfc", "$rT, $rA, $rB", IIC_IntGeneral, 581 [(set i64:$rT, (subc i64:$rB, i64:$rA))]>, 582 PPC970_DGroup_Cracked; 583defm SUBF8 : XOForm_1rx<31, 40, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 584 "subf", "$rT, $rA, $rB", IIC_IntGeneral, 585 [(set i64:$rT, (sub i64:$rB, i64:$rA))]>; 586defm NEG8 : XOForm_3r<31, 104, 0, (outs g8rc:$rT), (ins g8rc:$rA), 587 "neg", "$rT, $rA", IIC_IntSimple, 588 [(set i64:$rT, (ineg i64:$rA))]>; 589let Uses = [CARRY] in { 590let isCommutable = 1 in 591defm ADDE8 : XOForm_1rc<31, 138, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 592 "adde", "$rT, $rA, $rB", IIC_IntGeneral, 593 [(set i64:$rT, (adde i64:$rA, i64:$rB))]>; 594defm ADDME8 : XOForm_3rc<31, 234, 0, (outs g8rc:$rT), (ins g8rc:$rA), 595 "addme", "$rT, $rA", IIC_IntGeneral, 596 [(set i64:$rT, (adde i64:$rA, -1))]>; 597defm ADDZE8 : XOForm_3rc<31, 202, 0, (outs g8rc:$rT), (ins g8rc:$rA), 598 "addze", "$rT, $rA", IIC_IntGeneral, 599 [(set i64:$rT, (adde i64:$rA, 0))]>; 600defm SUBFE8 : XOForm_1rc<31, 136, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 601 "subfe", "$rT, $rA, $rB", IIC_IntGeneral, 602 [(set i64:$rT, (sube i64:$rB, i64:$rA))]>; 603defm SUBFME8 : XOForm_3rc<31, 232, 0, (outs g8rc:$rT), (ins g8rc:$rA), 604 "subfme", "$rT, $rA", IIC_IntGeneral, 605 [(set i64:$rT, (sube -1, i64:$rA))]>; 606defm SUBFZE8 : XOForm_3rc<31, 200, 0, (outs g8rc:$rT), (ins g8rc:$rA), 607 "subfze", "$rT, $rA", IIC_IntGeneral, 608 [(set i64:$rT, (sube 0, i64:$rA))]>; 609} 610} // isCodeGenOnly 611 612// FIXME: Duplicating this for the asm parser should be unnecessary, but the 613// previous definition must be marked as CodeGen only to prevent decoding 614// conflicts. 615let isAsmParserOnly = 1 in { 616def ADD8TLS_ : XOForm_1<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, tlsreg:$rB), 617 "add $rT, $rA, $rB", IIC_IntSimple, []>; 618 619let mayLoad = 1 in { 620def LBZXTLS_ : XForm_1<31, 87, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 621 "lbzx $rD, $rA, $rB", IIC_LdStLoad, []>; 622def LHZXTLS_ : XForm_1<31, 279, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 623 "lhzx $rD, $rA, $rB", IIC_LdStLoad, []>; 624def LWZXTLS_ : XForm_1<31, 23, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 625 "lwzx $rD, $rA, $rB", IIC_LdStLoad, []>; 626def LDXTLS_ : XForm_1<31, 21, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 627 "ldx $rD, $rA, $rB", IIC_LdStLD, []>, isPPC64; 628} 629 630let mayStore = 1 in { 631def STBXTLS_ : XForm_8<31, 215, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 632 "stbx $rS, $rA, $rB", IIC_LdStStore, []>, 633 PPC970_DGroup_Cracked; 634def STHXTLS_ : XForm_8<31, 407, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 635 "sthx $rS, $rA, $rB", IIC_LdStStore, []>, 636 PPC970_DGroup_Cracked; 637def STWXTLS_ : XForm_8<31, 151, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 638 "stwx $rS, $rA, $rB", IIC_LdStStore, []>, 639 PPC970_DGroup_Cracked; 640def STDXTLS_ : XForm_8<31, 149, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 641 "stdx $rS, $rA, $rB", IIC_LdStSTD, []>, isPPC64, 642 PPC970_DGroup_Cracked; 643} 644} 645 646let isCommutable = 1 in { 647defm MULHD : XOForm_1r<31, 73, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 648 "mulhd", "$rT, $rA, $rB", IIC_IntMulHW, 649 [(set i64:$rT, (mulhs i64:$rA, i64:$rB))]>; 650defm MULHDU : XOForm_1r<31, 9, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 651 "mulhdu", "$rT, $rA, $rB", IIC_IntMulHWU, 652 [(set i64:$rT, (mulhu i64:$rA, i64:$rB))]>; 653} // isCommutable 654} 655} // Interpretation64Bit 656 657let isCompare = 1, hasSideEffects = 0 in { 658 def CMPD : XForm_16_ext<31, 0, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB), 659 "cmpd $crD, $rA, $rB", IIC_IntCompare>, isPPC64; 660 def CMPLD : XForm_16_ext<31, 32, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB), 661 "cmpld $crD, $rA, $rB", IIC_IntCompare>, isPPC64; 662 def CMPDI : DForm_5_ext<11, (outs crrc:$crD), (ins g8rc:$rA, s16imm64:$imm), 663 "cmpdi $crD, $rA, $imm", IIC_IntCompare>, isPPC64; 664 def CMPLDI : DForm_6_ext<10, (outs crrc:$dst), (ins g8rc:$src1, u16imm64:$src2), 665 "cmpldi $dst, $src1, $src2", 666 IIC_IntCompare>, isPPC64; 667 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 668 def CMPRB8 : X_BF3_L1_RS5_RS5<31, 192, (outs crbitrc:$BF), 669 (ins u1imm:$L, g8rc:$rA, g8rc:$rB), 670 "cmprb $BF, $L, $rA, $rB", IIC_IntCompare, []>, 671 Requires<[IsISA3_0]>; 672 def CMPEQB : X_BF3_RS5_RS5<31, 224, (outs crbitrc:$BF), 673 (ins g8rc:$rA, g8rc:$rB), "cmpeqb $BF, $rA, $rB", 674 IIC_IntCompare, []>, Requires<[IsISA3_0]>; 675} 676 677let hasSideEffects = 0 in { 678defm SLD : XForm_6r<31, 27, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB), 679 "sld", "$rA, $rS, $rB", IIC_IntRotateD, 680 [(set i64:$rA, (PPCshl i64:$rS, i32:$rB))]>, isPPC64; 681defm SRD : XForm_6r<31, 539, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB), 682 "srd", "$rA, $rS, $rB", IIC_IntRotateD, 683 [(set i64:$rA, (PPCsrl i64:$rS, i32:$rB))]>, isPPC64; 684defm SRAD : XForm_6rc<31, 794, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB), 685 "srad", "$rA, $rS, $rB", IIC_IntRotateD, 686 [(set i64:$rA, (PPCsra i64:$rS, i32:$rB))]>, isPPC64; 687 688let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 689defm CNTLZW8 : XForm_11r<31, 26, (outs g8rc:$rA), (ins g8rc:$rS), 690 "cntlzw", "$rA, $rS", IIC_IntGeneral, []>; 691defm CNTTZW8 : XForm_11r<31, 538, (outs g8rc:$rA), (ins g8rc:$rS), 692 "cnttzw", "$rA, $rS", IIC_IntGeneral, []>, 693 Requires<[IsISA3_0]>; 694 695defm EXTSB8 : XForm_11r<31, 954, (outs g8rc:$rA), (ins g8rc:$rS), 696 "extsb", "$rA, $rS", IIC_IntSimple, 697 [(set i64:$rA, (sext_inreg i64:$rS, i8))]>; 698defm EXTSH8 : XForm_11r<31, 922, (outs g8rc:$rA), (ins g8rc:$rS), 699 "extsh", "$rA, $rS", IIC_IntSimple, 700 [(set i64:$rA, (sext_inreg i64:$rS, i16))]>; 701 702defm SLW8 : XForm_6r<31, 24, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 703 "slw", "$rA, $rS, $rB", IIC_IntGeneral, []>; 704defm SRW8 : XForm_6r<31, 536, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 705 "srw", "$rA, $rS, $rB", IIC_IntGeneral, []>; 706} // Interpretation64Bit 707 708// For fast-isel: 709let isCodeGenOnly = 1 in { 710def EXTSB8_32_64 : XForm_11<31, 954, (outs g8rc:$rA), (ins gprc:$rS), 711 "extsb $rA, $rS", IIC_IntSimple, []>, isPPC64; 712def EXTSH8_32_64 : XForm_11<31, 922, (outs g8rc:$rA), (ins gprc:$rS), 713 "extsh $rA, $rS", IIC_IntSimple, []>, isPPC64; 714} // isCodeGenOnly for fast-isel 715 716defm EXTSW : XForm_11r<31, 986, (outs g8rc:$rA), (ins g8rc:$rS), 717 "extsw", "$rA, $rS", IIC_IntSimple, 718 [(set i64:$rA, (sext_inreg i64:$rS, i32))]>, isPPC64; 719let Interpretation64Bit = 1, isCodeGenOnly = 1 in 720defm EXTSW_32_64 : XForm_11r<31, 986, (outs g8rc:$rA), (ins gprc:$rS), 721 "extsw", "$rA, $rS", IIC_IntSimple, 722 [(set i64:$rA, (sext i32:$rS))]>, isPPC64; 723let isCodeGenOnly = 1 in 724def EXTSW_32 : XForm_11<31, 986, (outs gprc:$rA), (ins gprc:$rS), 725 "extsw $rA, $rS", IIC_IntSimple, 726 []>, isPPC64; 727 728defm SRADI : XSForm_1rc<31, 413, (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH), 729 "sradi", "$rA, $rS, $SH", IIC_IntRotateDI, 730 [(set i64:$rA, (sra i64:$rS, (i32 imm:$SH)))]>, isPPC64; 731 732let Interpretation64Bit = 1, isCodeGenOnly = 1 in 733defm EXTSWSLI_32_64 : XSForm_1r<31, 445, (outs g8rc:$rA), 734 (ins gprc:$rS, u6imm:$SH), 735 "extswsli", "$rA, $rS, $SH", IIC_IntRotateDI, 736 [(set i64:$rA, 737 (PPCextswsli i32:$rS, (i32 imm:$SH)))]>, 738 isPPC64, Requires<[IsISA3_0]>; 739 740defm EXTSWSLI : XSForm_1rc<31, 445, (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH), 741 "extswsli", "$rA, $rS, $SH", IIC_IntRotateDI, 742 []>, isPPC64, Requires<[IsISA3_0]>; 743 744// For fast-isel: 745let isCodeGenOnly = 1, Defs = [CARRY] in 746def SRADI_32 : XSForm_1<31, 413, (outs gprc:$rA), (ins gprc:$rS, u6imm:$SH), 747 "sradi $rA, $rS, $SH", IIC_IntRotateDI, []>, isPPC64; 748 749defm CNTLZD : XForm_11r<31, 58, (outs g8rc:$rA), (ins g8rc:$rS), 750 "cntlzd", "$rA, $rS", IIC_IntGeneral, 751 [(set i64:$rA, (ctlz i64:$rS))]>; 752defm CNTTZD : XForm_11r<31, 570, (outs g8rc:$rA), (ins g8rc:$rS), 753 "cnttzd", "$rA, $rS", IIC_IntGeneral, 754 [(set i64:$rA, (cttz i64:$rS))]>, Requires<[IsISA3_0]>; 755def POPCNTD : XForm_11<31, 506, (outs g8rc:$rA), (ins g8rc:$rS), 756 "popcntd $rA, $rS", IIC_IntGeneral, 757 [(set i64:$rA, (ctpop i64:$rS))]>; 758def BPERMD : XForm_6<31, 252, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 759 "bpermd $rA, $rS, $rB", IIC_IntGeneral, 760 [(set i64:$rA, (int_ppc_bpermd g8rc:$rS, g8rc:$rB))]>, 761 isPPC64, Requires<[HasBPERMD]>; 762 763let isCodeGenOnly = 1, isCommutable = 1 in 764def CMPB8 : XForm_6<31, 508, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 765 "cmpb $rA, $rS, $rB", IIC_IntGeneral, 766 [(set i64:$rA, (PPCcmpb i64:$rS, i64:$rB))]>; 767 768// popcntw also does a population count on the high 32 bits (storing the 769// results in the high 32-bits of the output). We'll ignore that here (which is 770// safe because we never separately use the high part of the 64-bit registers). 771def POPCNTW : XForm_11<31, 378, (outs gprc:$rA), (ins gprc:$rS), 772 "popcntw $rA, $rS", IIC_IntGeneral, 773 [(set i32:$rA, (ctpop i32:$rS))]>; 774 775def POPCNTB : XForm_11<31, 122, (outs gprc:$rA), (ins gprc:$rS), 776 "popcntb $rA, $rS", IIC_IntGeneral, []>; 777 778defm DIVD : XOForm_1rcr<31, 489, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 779 "divd", "$rT, $rA, $rB", IIC_IntDivD, 780 [(set i64:$rT, (sdiv i64:$rA, i64:$rB))]>, isPPC64; 781defm DIVDU : XOForm_1rcr<31, 457, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 782 "divdu", "$rT, $rA, $rB", IIC_IntDivD, 783 [(set i64:$rT, (udiv i64:$rA, i64:$rB))]>, isPPC64; 784defm DIVDE : XOForm_1rcr<31, 425, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 785 "divde", "$rT, $rA, $rB", IIC_IntDivD, 786 [(set i64:$rT, (int_ppc_divde g8rc:$rA, g8rc:$rB))]>, 787 isPPC64, Requires<[HasExtDiv]>; 788 789let Predicates = [IsISA3_0] in { 790def MADDHD : VAForm_1a<48, (outs g8rc :$RT), (ins g8rc:$RA, g8rc:$RB, g8rc:$RC), 791 "maddhd $RT, $RA, $RB, $RC", IIC_IntMulHD, []>, isPPC64; 792def MADDHDU : VAForm_1a<49, 793 (outs g8rc :$RT), (ins g8rc:$RA, g8rc:$RB, g8rc:$RC), 794 "maddhdu $RT, $RA, $RB, $RC", IIC_IntMulHD, []>, isPPC64; 795def MADDLD : VAForm_1a<51, (outs gprc :$RT), (ins gprc:$RA, gprc:$RB, gprc:$RC), 796 "maddld $RT, $RA, $RB, $RC", IIC_IntMulHD, 797 [(set i32:$RT, (add_without_simm16 (mul_without_simm16 i32:$RA, i32:$RB), i32:$RC))]>, 798 isPPC64; 799def SETB : XForm_44<31, 128, (outs gprc:$RT), (ins crrc:$BFA), 800 "setb $RT, $BFA", IIC_IntGeneral>, isPPC64; 801let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 802 def MADDLD8 : VAForm_1a<51, 803 (outs g8rc :$RT), (ins g8rc:$RA, g8rc:$RB, g8rc:$RC), 804 "maddld $RT, $RA, $RB, $RC", IIC_IntMulHD, 805 [(set i64:$RT, (add_without_simm16 (mul_without_simm16 i64:$RA, i64:$RB), i64:$RC))]>, 806 isPPC64; 807 def SETB8 : XForm_44<31, 128, (outs g8rc:$RT), (ins crrc:$BFA), 808 "setb $RT, $BFA", IIC_IntGeneral>, isPPC64; 809} 810def DARN : XForm_45<31, 755, (outs g8rc:$RT), (ins i32imm:$L), 811 "darn $RT, $L", IIC_LdStLD>, isPPC64; 812def ADDPCIS : DXForm<19, 2, (outs g8rc:$RT), (ins i32imm:$D), 813 "addpcis $RT, $D", IIC_BrB, []>, isPPC64; 814def MODSD : XForm_8<31, 777, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 815 "modsd $rT, $rA, $rB", IIC_IntDivW, 816 [(set i64:$rT, (srem i64:$rA, i64:$rB))]>; 817def MODUD : XForm_8<31, 265, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 818 "modud $rT, $rA, $rB", IIC_IntDivW, 819 [(set i64:$rT, (urem i64:$rA, i64:$rB))]>; 820} 821 822defm DIVDEU : XOForm_1rcr<31, 393, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 823 "divdeu", "$rT, $rA, $rB", IIC_IntDivD, 824 [(set i64:$rT, (int_ppc_divdeu g8rc:$rA, g8rc:$rB))]>, 825 isPPC64, Requires<[HasExtDiv]>; 826let isCommutable = 1 in 827defm MULLD : XOForm_1rx<31, 233, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 828 "mulld", "$rT, $rA, $rB", IIC_IntMulHD, 829 [(set i64:$rT, (mul i64:$rA, i64:$rB))]>, isPPC64; 830let Interpretation64Bit = 1, isCodeGenOnly = 1 in 831def MULLI8 : DForm_2<7, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm), 832 "mulli $rD, $rA, $imm", IIC_IntMulLI, 833 [(set i64:$rD, (mul i64:$rA, imm64SExt16:$imm))]>; 834} 835 836let hasSideEffects = 0 in { 837defm RLDIMI : MDForm_1r<30, 3, (outs g8rc:$rA), 838 (ins g8rc:$rSi, g8rc:$rS, u6imm:$SH, u6imm:$MBE), 839 "rldimi", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 840 []>, isPPC64, RegConstraint<"$rSi = $rA">, 841 NoEncode<"$rSi">; 842 843// Rotate instructions. 844defm RLDCL : MDSForm_1r<30, 8, 845 (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE), 846 "rldcl", "$rA, $rS, $rB, $MBE", IIC_IntRotateD, 847 []>, isPPC64; 848defm RLDCR : MDSForm_1r<30, 9, 849 (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE), 850 "rldcr", "$rA, $rS, $rB, $MBE", IIC_IntRotateD, 851 []>, isPPC64; 852defm RLDICL : MDForm_1r<30, 0, 853 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE), 854 "rldicl", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 855 []>, isPPC64; 856// For fast-isel: 857let isCodeGenOnly = 1 in 858def RLDICL_32_64 : MDForm_1<30, 0, 859 (outs g8rc:$rA), 860 (ins gprc:$rS, u6imm:$SH, u6imm:$MBE), 861 "rldicl $rA, $rS, $SH, $MBE", IIC_IntRotateDI, 862 []>, isPPC64; 863// End fast-isel. 864let Interpretation64Bit = 1, isCodeGenOnly = 1 in 865defm RLDICL_32 : MDForm_1r<30, 0, 866 (outs gprc:$rA), 867 (ins gprc:$rS, u6imm:$SH, u6imm:$MBE), 868 "rldicl", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 869 []>, isPPC64; 870defm RLDICR : MDForm_1r<30, 1, 871 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE), 872 "rldicr", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 873 []>, isPPC64; 874let isCodeGenOnly = 1 in 875def RLDICR_32 : MDForm_1<30, 1, 876 (outs gprc:$rA), (ins gprc:$rS, u6imm:$SH, u6imm:$MBE), 877 "rldicr $rA, $rS, $SH, $MBE", IIC_IntRotateDI, 878 []>, isPPC64; 879defm RLDIC : MDForm_1r<30, 2, 880 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE), 881 "rldic", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 882 []>, isPPC64; 883 884let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 885defm RLWINM8 : MForm_2r<21, (outs g8rc:$rA), 886 (ins g8rc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 887 "rlwinm", "$rA, $rS, $SH, $MB, $ME", IIC_IntGeneral, 888 []>; 889 890defm RLWNM8 : MForm_2r<23, (outs g8rc:$rA), 891 (ins g8rc:$rS, g8rc:$rB, u5imm:$MB, u5imm:$ME), 892 "rlwnm", "$rA, $rS, $rB, $MB, $ME", IIC_IntGeneral, 893 []>; 894 895// RLWIMI can be commuted if the rotate amount is zero. 896let Interpretation64Bit = 1, isCodeGenOnly = 1 in 897defm RLWIMI8 : MForm_2r<20, (outs g8rc:$rA), 898 (ins g8rc:$rSi, g8rc:$rS, u5imm:$SH, u5imm:$MB, 899 u5imm:$ME), "rlwimi", "$rA, $rS, $SH, $MB, $ME", 900 IIC_IntRotate, []>, PPC970_DGroup_Cracked, 901 RegConstraint<"$rSi = $rA">, NoEncode<"$rSi">; 902 903let isSelect = 1 in 904def ISEL8 : AForm_4<31, 15, 905 (outs g8rc:$rT), (ins g8rc_nox0:$rA, g8rc:$rB, crbitrc:$cond), 906 "isel $rT, $rA, $rB, $cond", IIC_IntISEL, 907 []>; 908} // Interpretation64Bit 909} // hasSideEffects = 0 910} // End FXU Operations. 911 912 913//===----------------------------------------------------------------------===// 914// Load/Store instructions. 915// 916 917 918// Sign extending loads. 919let PPC970_Unit = 2 in { 920let Interpretation64Bit = 1, isCodeGenOnly = 1 in 921def LHA8: DForm_1<42, (outs g8rc:$rD), (ins memri:$src), 922 "lha $rD, $src", IIC_LdStLHA, 923 [(set i64:$rD, (sextloadi16 iaddr:$src))]>, 924 PPC970_DGroup_Cracked; 925def LWA : DSForm_1<58, 2, (outs g8rc:$rD), (ins memrix:$src), 926 "lwa $rD, $src", IIC_LdStLWA, 927 [(set i64:$rD, 928 (aligned4sextloadi32 iaddrX4:$src))]>, isPPC64, 929 PPC970_DGroup_Cracked; 930let Interpretation64Bit = 1, isCodeGenOnly = 1 in 931def LHAX8: XForm_1_memOp<31, 343, (outs g8rc:$rD), (ins memrr:$src), 932 "lhax $rD, $src", IIC_LdStLHA, 933 [(set i64:$rD, (sextloadi16 xaddr:$src))]>, 934 PPC970_DGroup_Cracked; 935def LWAX : XForm_1_memOp<31, 341, (outs g8rc:$rD), (ins memrr:$src), 936 "lwax $rD, $src", IIC_LdStLHA, 937 [(set i64:$rD, (sextloadi32 xaddrX4:$src))]>, isPPC64, 938 PPC970_DGroup_Cracked; 939// For fast-isel: 940let isCodeGenOnly = 1, mayLoad = 1, hasSideEffects = 0 in { 941def LWA_32 : DSForm_1<58, 2, (outs gprc:$rD), (ins memrix:$src), 942 "lwa $rD, $src", IIC_LdStLWA, []>, isPPC64, 943 PPC970_DGroup_Cracked; 944def LWAX_32 : XForm_1_memOp<31, 341, (outs gprc:$rD), (ins memrr:$src), 945 "lwax $rD, $src", IIC_LdStLHA, []>, isPPC64, 946 PPC970_DGroup_Cracked; 947} // end fast-isel isCodeGenOnly 948 949// Update forms. 950let mayLoad = 1, hasSideEffects = 0 in { 951let Interpretation64Bit = 1, isCodeGenOnly = 1 in 952def LHAU8 : DForm_1<43, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 953 (ins memri:$addr), 954 "lhau $rD, $addr", IIC_LdStLHAU, 955 []>, RegConstraint<"$addr.reg = $ea_result">, 956 NoEncode<"$ea_result">; 957// NO LWAU! 958 959let Interpretation64Bit = 1, isCodeGenOnly = 1 in 960def LHAUX8 : XForm_1_memOp<31, 375, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 961 (ins memrr:$addr), 962 "lhaux $rD, $addr", IIC_LdStLHAUX, 963 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 964 NoEncode<"$ea_result">; 965def LWAUX : XForm_1_memOp<31, 373, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 966 (ins memrr:$addr), 967 "lwaux $rD, $addr", IIC_LdStLHAUX, 968 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 969 NoEncode<"$ea_result">, isPPC64; 970} 971} 972 973let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 974// Zero extending loads. 975let PPC970_Unit = 2 in { 976def LBZ8 : DForm_1<34, (outs g8rc:$rD), (ins memri:$src), 977 "lbz $rD, $src", IIC_LdStLoad, 978 [(set i64:$rD, (zextloadi8 iaddr:$src))]>; 979def LHZ8 : DForm_1<40, (outs g8rc:$rD), (ins memri:$src), 980 "lhz $rD, $src", IIC_LdStLoad, 981 [(set i64:$rD, (zextloadi16 iaddr:$src))]>; 982def LWZ8 : DForm_1<32, (outs g8rc:$rD), (ins memri:$src), 983 "lwz $rD, $src", IIC_LdStLoad, 984 [(set i64:$rD, (zextloadi32 iaddr:$src))]>, isPPC64; 985 986def LBZX8 : XForm_1_memOp<31, 87, (outs g8rc:$rD), (ins memrr:$src), 987 "lbzx $rD, $src", IIC_LdStLoad, 988 [(set i64:$rD, (zextloadi8 xaddr:$src))]>; 989def LHZX8 : XForm_1_memOp<31, 279, (outs g8rc:$rD), (ins memrr:$src), 990 "lhzx $rD, $src", IIC_LdStLoad, 991 [(set i64:$rD, (zextloadi16 xaddr:$src))]>; 992def LWZX8 : XForm_1_memOp<31, 23, (outs g8rc:$rD), (ins memrr:$src), 993 "lwzx $rD, $src", IIC_LdStLoad, 994 [(set i64:$rD, (zextloadi32 xaddr:$src))]>; 995 996 997// Update forms. 998let mayLoad = 1, hasSideEffects = 0 in { 999def LBZU8 : DForm_1<35, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1000 (ins memri:$addr), 1001 "lbzu $rD, $addr", IIC_LdStLoadUpd, 1002 []>, RegConstraint<"$addr.reg = $ea_result">, 1003 NoEncode<"$ea_result">; 1004def LHZU8 : DForm_1<41, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1005 (ins memri:$addr), 1006 "lhzu $rD, $addr", IIC_LdStLoadUpd, 1007 []>, RegConstraint<"$addr.reg = $ea_result">, 1008 NoEncode<"$ea_result">; 1009def LWZU8 : DForm_1<33, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1010 (ins memri:$addr), 1011 "lwzu $rD, $addr", IIC_LdStLoadUpd, 1012 []>, RegConstraint<"$addr.reg = $ea_result">, 1013 NoEncode<"$ea_result">; 1014 1015def LBZUX8 : XForm_1_memOp<31, 119, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1016 (ins memrr:$addr), 1017 "lbzux $rD, $addr", IIC_LdStLoadUpdX, 1018 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1019 NoEncode<"$ea_result">; 1020def LHZUX8 : XForm_1_memOp<31, 311, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1021 (ins memrr:$addr), 1022 "lhzux $rD, $addr", IIC_LdStLoadUpdX, 1023 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1024 NoEncode<"$ea_result">; 1025def LWZUX8 : XForm_1_memOp<31, 55, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1026 (ins memrr:$addr), 1027 "lwzux $rD, $addr", IIC_LdStLoadUpdX, 1028 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1029 NoEncode<"$ea_result">; 1030} 1031} 1032} // Interpretation64Bit 1033 1034 1035// Full 8-byte loads. 1036let PPC970_Unit = 2 in { 1037def LD : DSForm_1<58, 0, (outs g8rc:$rD), (ins memrix:$src), 1038 "ld $rD, $src", IIC_LdStLD, 1039 [(set i64:$rD, (aligned4load iaddrX4:$src))]>, isPPC64; 1040// The following four definitions are selected for small code model only. 1041// Otherwise, we need to create two instructions to form a 32-bit offset, 1042// so we have a custom matcher for TOC_ENTRY in PPCDAGToDAGIsel::Select(). 1043def LDtoc: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 1044 "#LDtoc", 1045 [(set i64:$rD, 1046 (PPCtoc_entry tglobaladdr:$disp, i64:$reg))]>, isPPC64; 1047def LDtocJTI: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 1048 "#LDtocJTI", 1049 [(set i64:$rD, 1050 (PPCtoc_entry tjumptable:$disp, i64:$reg))]>, isPPC64; 1051def LDtocCPT: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 1052 "#LDtocCPT", 1053 [(set i64:$rD, 1054 (PPCtoc_entry tconstpool:$disp, i64:$reg))]>, isPPC64; 1055def LDtocBA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 1056 "#LDtocCPT", 1057 [(set i64:$rD, 1058 (PPCtoc_entry tblockaddress:$disp, i64:$reg))]>, isPPC64; 1059 1060def LDX : XForm_1_memOp<31, 21, (outs g8rc:$rD), (ins memrr:$src), 1061 "ldx $rD, $src", IIC_LdStLD, 1062 [(set i64:$rD, (load xaddrX4:$src))]>, isPPC64; 1063def LDBRX : XForm_1_memOp<31, 532, (outs g8rc:$rD), (ins memrr:$src), 1064 "ldbrx $rD, $src", IIC_LdStLoad, 1065 [(set i64:$rD, (PPClbrx xoaddr:$src, i64))]>, isPPC64; 1066 1067let mayLoad = 1, hasSideEffects = 0, isCodeGenOnly = 1 in { 1068def LHBRX8 : XForm_1_memOp<31, 790, (outs g8rc:$rD), (ins memrr:$src), 1069 "lhbrx $rD, $src", IIC_LdStLoad, []>; 1070def LWBRX8 : XForm_1_memOp<31, 534, (outs g8rc:$rD), (ins memrr:$src), 1071 "lwbrx $rD, $src", IIC_LdStLoad, []>; 1072} 1073 1074let mayLoad = 1, hasSideEffects = 0 in { 1075def LDU : DSForm_1<58, 1, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1076 (ins memrix:$addr), 1077 "ldu $rD, $addr", IIC_LdStLDU, 1078 []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64, 1079 NoEncode<"$ea_result">; 1080 1081def LDUX : XForm_1_memOp<31, 53, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1082 (ins memrr:$addr), 1083 "ldux $rD, $addr", IIC_LdStLDUX, 1084 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1085 NoEncode<"$ea_result">, isPPC64; 1086 1087def LDMX : XForm_1<31, 309, (outs g8rc:$rD), (ins memrr:$src), 1088 "ldmx $rD, $src", IIC_LdStLD, []>, isPPC64, 1089 Requires<[IsISA3_0]>; 1090} 1091} 1092 1093// Support for medium and large code model. 1094let hasSideEffects = 0 in { 1095let isReMaterializable = 1 in { 1096def ADDIStocHA8: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp), 1097 "#ADDIStocHA8", []>, isPPC64; 1098def ADDItocL: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp), 1099 "#ADDItocL", []>, isPPC64; 1100} 1101let mayLoad = 1 in 1102def LDtocL: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc_nox0:$reg), 1103 "#LDtocL", []>, isPPC64; 1104} 1105 1106// Support for thread-local storage. 1107def ADDISgotTprelHA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1108 "#ADDISgotTprelHA", 1109 [(set i64:$rD, 1110 (PPCaddisGotTprelHA i64:$reg, 1111 tglobaltlsaddr:$disp))]>, 1112 isPPC64; 1113def LDgotTprelL: PPCEmitTimePseudo<(outs g8rc_nox0:$rD), (ins s16imm64:$disp, g8rc_nox0:$reg), 1114 "#LDgotTprelL", 1115 [(set i64:$rD, 1116 (PPCldGotTprelL tglobaltlsaddr:$disp, i64:$reg))]>, 1117 isPPC64; 1118 1119let Defs = [CR7], Itinerary = IIC_LdStSync in 1120def CFENCE8 : PPCPostRAExpPseudo<(outs), (ins g8rc:$cr), "#CFENCE8", []>; 1121 1122def : Pat<(PPCaddTls i64:$in, tglobaltlsaddr:$g), 1123 (ADD8TLS $in, tglobaltlsaddr:$g)>; 1124def ADDIStlsgdHA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1125 "#ADDIStlsgdHA", 1126 [(set i64:$rD, 1127 (PPCaddisTlsgdHA i64:$reg, tglobaltlsaddr:$disp))]>, 1128 isPPC64; 1129def ADDItlsgdL : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1130 "#ADDItlsgdL", 1131 [(set i64:$rD, 1132 (PPCaddiTlsgdL i64:$reg, tglobaltlsaddr:$disp))]>, 1133 isPPC64; 1134// LR8 is a true define, while the rest of the Defs are clobbers. X3 is 1135// explicitly defined when this op is created, so not mentioned here. 1136// This is lowered to BL8_NOP_TLS by the assembly printer, so the size must be 1137// correct because the branch select pass is relying on it. 1138let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, Size = 8, 1139 Defs = [X0,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] in 1140def GETtlsADDR : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym), 1141 "#GETtlsADDR", 1142 [(set i64:$rD, 1143 (PPCgetTlsAddr i64:$reg, tglobaltlsaddr:$sym))]>, 1144 isPPC64; 1145// Combined op for ADDItlsgdL and GETtlsADDR, late expanded. X3 and LR8 1146// are true defines while the rest of the Defs are clobbers. 1147let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 1148 Defs = [X0,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] 1149 in 1150def ADDItlsgdLADDR : PPCEmitTimePseudo<(outs g8rc:$rD), 1151 (ins g8rc_nox0:$reg, s16imm64:$disp, tlsgd:$sym), 1152 "#ADDItlsgdLADDR", 1153 [(set i64:$rD, 1154 (PPCaddiTlsgdLAddr i64:$reg, 1155 tglobaltlsaddr:$disp, 1156 tglobaltlsaddr:$sym))]>, 1157 isPPC64; 1158def ADDIStlsldHA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1159 "#ADDIStlsldHA", 1160 [(set i64:$rD, 1161 (PPCaddisTlsldHA i64:$reg, tglobaltlsaddr:$disp))]>, 1162 isPPC64; 1163def ADDItlsldL : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1164 "#ADDItlsldL", 1165 [(set i64:$rD, 1166 (PPCaddiTlsldL i64:$reg, tglobaltlsaddr:$disp))]>, 1167 isPPC64; 1168// LR8 is a true define, while the rest of the Defs are clobbers. X3 is 1169// explicitly defined when this op is created, so not mentioned here. 1170let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 1171 Defs = [X0,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] in 1172def GETtlsldADDR : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym), 1173 "#GETtlsldADDR", 1174 [(set i64:$rD, 1175 (PPCgetTlsldAddr i64:$reg, tglobaltlsaddr:$sym))]>, 1176 isPPC64; 1177// Combined op for ADDItlsldL and GETtlsADDR, late expanded. X3 and LR8 1178// are true defines, while the rest of the Defs are clobbers. 1179let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 1180 Defs = [X0,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] 1181 in 1182def ADDItlsldLADDR : PPCEmitTimePseudo<(outs g8rc:$rD), 1183 (ins g8rc_nox0:$reg, s16imm64:$disp, tlsgd:$sym), 1184 "#ADDItlsldLADDR", 1185 [(set i64:$rD, 1186 (PPCaddiTlsldLAddr i64:$reg, 1187 tglobaltlsaddr:$disp, 1188 tglobaltlsaddr:$sym))]>, 1189 isPPC64; 1190def ADDISdtprelHA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1191 "#ADDISdtprelHA", 1192 [(set i64:$rD, 1193 (PPCaddisDtprelHA i64:$reg, 1194 tglobaltlsaddr:$disp))]>, 1195 isPPC64; 1196def ADDIdtprelL : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1197 "#ADDIdtprelL", 1198 [(set i64:$rD, 1199 (PPCaddiDtprelL i64:$reg, tglobaltlsaddr:$disp))]>, 1200 isPPC64; 1201 1202let PPC970_Unit = 2 in { 1203let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1204// Truncating stores. 1205def STB8 : DForm_1<38, (outs), (ins g8rc:$rS, memri:$src), 1206 "stb $rS, $src", IIC_LdStStore, 1207 [(truncstorei8 i64:$rS, iaddr:$src)]>; 1208def STH8 : DForm_1<44, (outs), (ins g8rc:$rS, memri:$src), 1209 "sth $rS, $src", IIC_LdStStore, 1210 [(truncstorei16 i64:$rS, iaddr:$src)]>; 1211def STW8 : DForm_1<36, (outs), (ins g8rc:$rS, memri:$src), 1212 "stw $rS, $src", IIC_LdStStore, 1213 [(truncstorei32 i64:$rS, iaddr:$src)]>; 1214def STBX8 : XForm_8_memOp<31, 215, (outs), (ins g8rc:$rS, memrr:$dst), 1215 "stbx $rS, $dst", IIC_LdStStore, 1216 [(truncstorei8 i64:$rS, xaddr:$dst)]>, 1217 PPC970_DGroup_Cracked; 1218def STHX8 : XForm_8_memOp<31, 407, (outs), (ins g8rc:$rS, memrr:$dst), 1219 "sthx $rS, $dst", IIC_LdStStore, 1220 [(truncstorei16 i64:$rS, xaddr:$dst)]>, 1221 PPC970_DGroup_Cracked; 1222def STWX8 : XForm_8_memOp<31, 151, (outs), (ins g8rc:$rS, memrr:$dst), 1223 "stwx $rS, $dst", IIC_LdStStore, 1224 [(truncstorei32 i64:$rS, xaddr:$dst)]>, 1225 PPC970_DGroup_Cracked; 1226} // Interpretation64Bit 1227 1228// Normal 8-byte stores. 1229def STD : DSForm_1<62, 0, (outs), (ins g8rc:$rS, memrix:$dst), 1230 "std $rS, $dst", IIC_LdStSTD, 1231 [(aligned4store i64:$rS, iaddrX4:$dst)]>, isPPC64; 1232def STDX : XForm_8_memOp<31, 149, (outs), (ins g8rc:$rS, memrr:$dst), 1233 "stdx $rS, $dst", IIC_LdStSTD, 1234 [(store i64:$rS, xaddrX4:$dst)]>, isPPC64, 1235 PPC970_DGroup_Cracked; 1236def STDBRX: XForm_8_memOp<31, 660, (outs), (ins g8rc:$rS, memrr:$dst), 1237 "stdbrx $rS, $dst", IIC_LdStStore, 1238 [(PPCstbrx i64:$rS, xoaddr:$dst, i64)]>, isPPC64, 1239 PPC970_DGroup_Cracked; 1240} 1241 1242// Stores with Update (pre-inc). 1243let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in { 1244let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1245def STBU8 : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst), 1246 "stbu $rS, $dst", IIC_LdStSTU, []>, 1247 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1248def STHU8 : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst), 1249 "sthu $rS, $dst", IIC_LdStSTU, []>, 1250 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1251def STWU8 : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst), 1252 "stwu $rS, $dst", IIC_LdStSTU, []>, 1253 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1254 1255def STBUX8: XForm_8_memOp<31, 247, (outs ptr_rc_nor0:$ea_res), 1256 (ins g8rc:$rS, memrr:$dst), 1257 "stbux $rS, $dst", IIC_LdStSTUX, []>, 1258 RegConstraint<"$dst.ptrreg = $ea_res">, 1259 NoEncode<"$ea_res">, 1260 PPC970_DGroup_Cracked; 1261def STHUX8: XForm_8_memOp<31, 439, (outs ptr_rc_nor0:$ea_res), 1262 (ins g8rc:$rS, memrr:$dst), 1263 "sthux $rS, $dst", IIC_LdStSTUX, []>, 1264 RegConstraint<"$dst.ptrreg = $ea_res">, 1265 NoEncode<"$ea_res">, 1266 PPC970_DGroup_Cracked; 1267def STWUX8: XForm_8_memOp<31, 183, (outs ptr_rc_nor0:$ea_res), 1268 (ins g8rc:$rS, memrr:$dst), 1269 "stwux $rS, $dst", IIC_LdStSTUX, []>, 1270 RegConstraint<"$dst.ptrreg = $ea_res">, 1271 NoEncode<"$ea_res">, 1272 PPC970_DGroup_Cracked; 1273} // Interpretation64Bit 1274 1275def STDU : DSForm_1<62, 1, (outs ptr_rc_nor0:$ea_res), 1276 (ins g8rc:$rS, memrix:$dst), 1277 "stdu $rS, $dst", IIC_LdStSTU, []>, 1278 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">, 1279 isPPC64; 1280 1281def STDUX : XForm_8_memOp<31, 181, (outs ptr_rc_nor0:$ea_res), 1282 (ins g8rc:$rS, memrr:$dst), 1283 "stdux $rS, $dst", IIC_LdStSTUX, []>, 1284 RegConstraint<"$dst.ptrreg = $ea_res">, 1285 NoEncode<"$ea_res">, 1286 PPC970_DGroup_Cracked, isPPC64; 1287} 1288 1289// Patterns to match the pre-inc stores. We can't put the patterns on 1290// the instruction definitions directly as ISel wants the address base 1291// and offset to be separate operands, not a single complex operand. 1292def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1293 (STBU8 $rS, iaddroff:$ptroff, $ptrreg)>; 1294def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1295 (STHU8 $rS, iaddroff:$ptroff, $ptrreg)>; 1296def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1297 (STWU8 $rS, iaddroff:$ptroff, $ptrreg)>; 1298def : Pat<(aligned4pre_store i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1299 (STDU $rS, iaddroff:$ptroff, $ptrreg)>; 1300 1301def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1302 (STBUX8 $rS, $ptrreg, $ptroff)>; 1303def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1304 (STHUX8 $rS, $ptrreg, $ptroff)>; 1305def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1306 (STWUX8 $rS, $ptrreg, $ptroff)>; 1307def : Pat<(pre_store i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1308 (STDUX $rS, $ptrreg, $ptroff)>; 1309 1310 1311//===----------------------------------------------------------------------===// 1312// Floating point instructions. 1313// 1314 1315 1316let PPC970_Unit = 3, hasSideEffects = 0, 1317 Uses = [RM] in { // FPU Operations. 1318defm FCFID : XForm_26r<63, 846, (outs f8rc:$frD), (ins f8rc:$frB), 1319 "fcfid", "$frD, $frB", IIC_FPGeneral, 1320 [(set f64:$frD, (PPCfcfid f64:$frB))]>, isPPC64; 1321defm FCTID : XForm_26r<63, 814, (outs f8rc:$frD), (ins f8rc:$frB), 1322 "fctid", "$frD, $frB", IIC_FPGeneral, 1323 []>, isPPC64; 1324defm FCTIDU : XForm_26r<63, 942, (outs f8rc:$frD), (ins f8rc:$frB), 1325 "fctidu", "$frD, $frB", IIC_FPGeneral, 1326 []>, isPPC64; 1327defm FCTIDZ : XForm_26r<63, 815, (outs f8rc:$frD), (ins f8rc:$frB), 1328 "fctidz", "$frD, $frB", IIC_FPGeneral, 1329 [(set f64:$frD, (PPCfctidz f64:$frB))]>, isPPC64; 1330 1331defm FCFIDU : XForm_26r<63, 974, (outs f8rc:$frD), (ins f8rc:$frB), 1332 "fcfidu", "$frD, $frB", IIC_FPGeneral, 1333 [(set f64:$frD, (PPCfcfidu f64:$frB))]>, isPPC64; 1334defm FCFIDS : XForm_26r<59, 846, (outs f4rc:$frD), (ins f8rc:$frB), 1335 "fcfids", "$frD, $frB", IIC_FPGeneral, 1336 [(set f32:$frD, (PPCfcfids f64:$frB))]>, isPPC64; 1337defm FCFIDUS : XForm_26r<59, 974, (outs f4rc:$frD), (ins f8rc:$frB), 1338 "fcfidus", "$frD, $frB", IIC_FPGeneral, 1339 [(set f32:$frD, (PPCfcfidus f64:$frB))]>, isPPC64; 1340defm FCTIDUZ : XForm_26r<63, 943, (outs f8rc:$frD), (ins f8rc:$frB), 1341 "fctiduz", "$frD, $frB", IIC_FPGeneral, 1342 [(set f64:$frD, (PPCfctiduz f64:$frB))]>, isPPC64; 1343defm FCTIWUZ : XForm_26r<63, 143, (outs f8rc:$frD), (ins f8rc:$frB), 1344 "fctiwuz", "$frD, $frB", IIC_FPGeneral, 1345 [(set f64:$frD, (PPCfctiwuz f64:$frB))]>, isPPC64; 1346} 1347 1348 1349//===----------------------------------------------------------------------===// 1350// Instruction Patterns 1351// 1352 1353// Extensions and truncates to/from 32-bit regs. 1354def : Pat<(i64 (zext i32:$in)), 1355 (RLDICL (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32), 1356 0, 32)>; 1357def : Pat<(i64 (anyext i32:$in)), 1358 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32)>; 1359def : Pat<(i32 (trunc i64:$in)), 1360 (EXTRACT_SUBREG $in, sub_32)>; 1361 1362// Implement the 'not' operation with the NOR instruction. 1363// (we could use the default xori pattern, but nor has lower latency on some 1364// cores (such as the A2)). 1365def i64not : OutPatFrag<(ops node:$in), 1366 (NOR8 $in, $in)>; 1367def : Pat<(not i64:$in), 1368 (i64not $in)>; 1369 1370// Extending loads with i64 targets. 1371def : Pat<(zextloadi1 iaddr:$src), 1372 (LBZ8 iaddr:$src)>; 1373def : Pat<(zextloadi1 xaddr:$src), 1374 (LBZX8 xaddr:$src)>; 1375def : Pat<(extloadi1 iaddr:$src), 1376 (LBZ8 iaddr:$src)>; 1377def : Pat<(extloadi1 xaddr:$src), 1378 (LBZX8 xaddr:$src)>; 1379def : Pat<(extloadi8 iaddr:$src), 1380 (LBZ8 iaddr:$src)>; 1381def : Pat<(extloadi8 xaddr:$src), 1382 (LBZX8 xaddr:$src)>; 1383def : Pat<(extloadi16 iaddr:$src), 1384 (LHZ8 iaddr:$src)>; 1385def : Pat<(extloadi16 xaddr:$src), 1386 (LHZX8 xaddr:$src)>; 1387def : Pat<(extloadi32 iaddr:$src), 1388 (LWZ8 iaddr:$src)>; 1389def : Pat<(extloadi32 xaddr:$src), 1390 (LWZX8 xaddr:$src)>; 1391 1392// Standard shifts. These are represented separately from the real shifts above 1393// so that we can distinguish between shifts that allow 6-bit and 7-bit shift 1394// amounts. 1395def : Pat<(sra i64:$rS, i32:$rB), 1396 (SRAD $rS, $rB)>; 1397def : Pat<(srl i64:$rS, i32:$rB), 1398 (SRD $rS, $rB)>; 1399def : Pat<(shl i64:$rS, i32:$rB), 1400 (SLD $rS, $rB)>; 1401 1402// SUBFIC 1403def : Pat<(sub imm64SExt16:$imm, i64:$in), 1404 (SUBFIC8 $in, imm:$imm)>; 1405 1406// SHL/SRL 1407def : Pat<(shl i64:$in, (i32 imm:$imm)), 1408 (RLDICR $in, imm:$imm, (SHL64 imm:$imm))>; 1409def : Pat<(srl i64:$in, (i32 imm:$imm)), 1410 (RLDICL $in, (SRL64 imm:$imm), imm:$imm)>; 1411 1412// ROTL 1413def : Pat<(rotl i64:$in, i32:$sh), 1414 (RLDCL $in, $sh, 0)>; 1415def : Pat<(rotl i64:$in, (i32 imm:$imm)), 1416 (RLDICL $in, imm:$imm, 0)>; 1417 1418// Hi and Lo for Darwin Global Addresses. 1419def : Pat<(PPChi tglobaladdr:$in, 0), (LIS8 tglobaladdr:$in)>; 1420def : Pat<(PPClo tglobaladdr:$in, 0), (LI8 tglobaladdr:$in)>; 1421def : Pat<(PPChi tconstpool:$in , 0), (LIS8 tconstpool:$in)>; 1422def : Pat<(PPClo tconstpool:$in , 0), (LI8 tconstpool:$in)>; 1423def : Pat<(PPChi tjumptable:$in , 0), (LIS8 tjumptable:$in)>; 1424def : Pat<(PPClo tjumptable:$in , 0), (LI8 tjumptable:$in)>; 1425def : Pat<(PPChi tblockaddress:$in, 0), (LIS8 tblockaddress:$in)>; 1426def : Pat<(PPClo tblockaddress:$in, 0), (LI8 tblockaddress:$in)>; 1427def : Pat<(PPChi tglobaltlsaddr:$g, i64:$in), 1428 (ADDIS8 $in, tglobaltlsaddr:$g)>; 1429def : Pat<(PPClo tglobaltlsaddr:$g, i64:$in), 1430 (ADDI8 $in, tglobaltlsaddr:$g)>; 1431def : Pat<(add i64:$in, (PPChi tglobaladdr:$g, 0)), 1432 (ADDIS8 $in, tglobaladdr:$g)>; 1433def : Pat<(add i64:$in, (PPChi tconstpool:$g, 0)), 1434 (ADDIS8 $in, tconstpool:$g)>; 1435def : Pat<(add i64:$in, (PPChi tjumptable:$g, 0)), 1436 (ADDIS8 $in, tjumptable:$g)>; 1437def : Pat<(add i64:$in, (PPChi tblockaddress:$g, 0)), 1438 (ADDIS8 $in, tblockaddress:$g)>; 1439 1440// Patterns to match r+r indexed loads and stores for 1441// addresses without at least 4-byte alignment. 1442def : Pat<(i64 (unaligned4sextloadi32 xoaddr:$src)), 1443 (LWAX xoaddr:$src)>; 1444def : Pat<(i64 (unaligned4load xoaddr:$src)), 1445 (LDX xoaddr:$src)>; 1446def : Pat<(unaligned4store i64:$rS, xoaddr:$dst), 1447 (STDX $rS, xoaddr:$dst)>; 1448 1449// 64-bits atomic loads and stores 1450def : Pat<(atomic_load_64 iaddrX4:$src), (LD memrix:$src)>; 1451def : Pat<(atomic_load_64 xaddrX4:$src), (LDX memrr:$src)>; 1452 1453def : Pat<(atomic_store_64 iaddrX4:$ptr, i64:$val), (STD g8rc:$val, memrix:$ptr)>; 1454def : Pat<(atomic_store_64 xaddrX4:$ptr, i64:$val), (STDX g8rc:$val, memrr:$ptr)>; 1455 1456let Predicates = [IsISA3_0] in { 1457 1458class X_L1_RA5_RB5<bits<6> opcode, bits<10> xo, string opc, RegisterOperand ty, 1459 InstrItinClass itin, list<dag> pattern> 1460 : X_L1_RS5_RS5<opcode, xo, (outs), (ins ty:$rA, ty:$rB, u1imm:$L), 1461 !strconcat(opc, " $rA, $rB, $L"), itin, pattern>; 1462 1463let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1464def CP_COPY8 : X_L1_RA5_RB5<31, 774, "copy" , g8rc, IIC_LdStCOPY, []>; 1465def CP_PASTE8 : X_L1_RA5_RB5<31, 902, "paste" , g8rc, IIC_LdStPASTE, []>; 1466def CP_PASTE8_rec : X_L1_RA5_RB5<31, 902, "paste.", g8rc, IIC_LdStPASTE, []>,isRecordForm; 1467} 1468 1469// SLB Invalidate Entry Global 1470def SLBIEG : XForm_26<31, 466, (outs), (ins gprc:$RS, gprc:$RB), 1471 "slbieg $RS, $RB", IIC_SprSLBIEG, []>; 1472// SLB Synchronize 1473def SLBSYNC : XForm_0<31, 338, (outs), (ins), "slbsync", IIC_SprSLBSYNC, []>; 1474 1475} // IsISA3_0 1476