PPC.td revision 360784
1//===-- PPC.td - Describe the PowerPC Target Machine -------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This is the top level entry point for the PowerPC target. 10// 11//===----------------------------------------------------------------------===// 12 13// Get the target-independent interfaces which we are implementing. 14// 15include "llvm/Target/Target.td" 16 17//===----------------------------------------------------------------------===// 18// PowerPC Subtarget features. 19// 20 21//===----------------------------------------------------------------------===// 22// CPU Directives // 23//===----------------------------------------------------------------------===// 24 25def Directive440 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_440", "">; 26def Directive601 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_601", "">; 27def Directive602 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_602", "">; 28def Directive603 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_603", "">; 29def Directive604 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_603", "">; 30def Directive620 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_603", "">; 31def Directive7400: SubtargetFeature<"", "CPUDirective", "PPC::DIR_7400", "">; 32def Directive750 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_750", "">; 33def Directive970 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_970", "">; 34def Directive32 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_32", "">; 35def Directive64 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_64", "">; 36def DirectiveA2 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_A2", "">; 37def DirectiveE500 : SubtargetFeature<"", "CPUDirective", 38 "PPC::DIR_E500", "">; 39def DirectiveE500mc : SubtargetFeature<"", "CPUDirective", 40 "PPC::DIR_E500mc", "">; 41def DirectiveE5500 : SubtargetFeature<"", "CPUDirective", 42 "PPC::DIR_E5500", "">; 43def DirectivePwr3: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR3", "">; 44def DirectivePwr4: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR4", "">; 45def DirectivePwr5: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR5", "">; 46def DirectivePwr5x 47 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR5X", "">; 48def DirectivePwr6: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR6", "">; 49def DirectivePwr6x 50 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR6X", "">; 51def DirectivePwr7: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR7", "">; 52def DirectivePwr8: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR8", "">; 53def DirectivePwr9: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR9", "">; 54def DirectivePwrFuture 55 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR_FUTURE", "">; 56 57def Feature64Bit : SubtargetFeature<"64bit","Has64BitSupport", "true", 58 "Enable 64-bit instructions">; 59def FeatureHardFloat : SubtargetFeature<"hard-float", "HasHardFloat", "true", 60 "Enable floating-point instructions">; 61def Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true", 62 "Enable 64-bit registers usage for ppc32 [beta]">; 63def FeatureCRBits : SubtargetFeature<"crbits", "UseCRBits", "true", 64 "Use condition-register bits individually">; 65def FeatureFPU : SubtargetFeature<"fpu","HasFPU","true", 66 "Enable classic FPU instructions", 67 [FeatureHardFloat]>; 68def FeatureAltivec : SubtargetFeature<"altivec","HasAltivec", "true", 69 "Enable Altivec instructions", 70 [FeatureFPU]>; 71def FeatureSPE : SubtargetFeature<"spe","HasSPE", "true", 72 "Enable SPE instructions", 73 [FeatureHardFloat]>; 74def FeatureMFOCRF : SubtargetFeature<"mfocrf","HasMFOCRF", "true", 75 "Enable the MFOCRF instruction">; 76def FeatureFSqrt : SubtargetFeature<"fsqrt","HasFSQRT", "true", 77 "Enable the fsqrt instruction", 78 [FeatureFPU]>; 79def FeatureFCPSGN : SubtargetFeature<"fcpsgn", "HasFCPSGN", "true", 80 "Enable the fcpsgn instruction", 81 [FeatureFPU]>; 82def FeatureFRE : SubtargetFeature<"fre", "HasFRE", "true", 83 "Enable the fre instruction", 84 [FeatureFPU]>; 85def FeatureFRES : SubtargetFeature<"fres", "HasFRES", "true", 86 "Enable the fres instruction", 87 [FeatureFPU]>; 88def FeatureFRSQRTE : SubtargetFeature<"frsqrte", "HasFRSQRTE", "true", 89 "Enable the frsqrte instruction", 90 [FeatureFPU]>; 91def FeatureFRSQRTES : SubtargetFeature<"frsqrtes", "HasFRSQRTES", "true", 92 "Enable the frsqrtes instruction", 93 [FeatureFPU]>; 94def FeatureRecipPrec : SubtargetFeature<"recipprec", "HasRecipPrec", "true", 95 "Assume higher precision reciprocal estimates">; 96def FeatureSTFIWX : SubtargetFeature<"stfiwx","HasSTFIWX", "true", 97 "Enable the stfiwx instruction", 98 [FeatureFPU]>; 99def FeatureLFIWAX : SubtargetFeature<"lfiwax","HasLFIWAX", "true", 100 "Enable the lfiwax instruction", 101 [FeatureFPU]>; 102def FeatureFPRND : SubtargetFeature<"fprnd", "HasFPRND", "true", 103 "Enable the fri[mnpz] instructions", 104 [FeatureFPU]>; 105def FeatureFPCVT : SubtargetFeature<"fpcvt", "HasFPCVT", "true", 106 "Enable fc[ft]* (unsigned and single-precision) and lfiwzx instructions", 107 [FeatureFPU]>; 108def FeatureISEL : SubtargetFeature<"isel","HasISEL", "true", 109 "Enable the isel instruction">; 110def FeatureBPERMD : SubtargetFeature<"bpermd", "HasBPERMD", "true", 111 "Enable the bpermd instruction">; 112def FeatureExtDiv : SubtargetFeature<"extdiv", "HasExtDiv", "true", 113 "Enable extended divide instructions">; 114def FeatureLDBRX : SubtargetFeature<"ldbrx","HasLDBRX", "true", 115 "Enable the ldbrx instruction">; 116def FeatureCMPB : SubtargetFeature<"cmpb", "HasCMPB", "true", 117 "Enable the cmpb instruction">; 118def FeatureICBT : SubtargetFeature<"icbt","HasICBT", "true", 119 "Enable icbt instruction">; 120def FeatureBookE : SubtargetFeature<"booke", "IsBookE", "true", 121 "Enable Book E instructions", 122 [FeatureICBT]>; 123def FeatureMSYNC : SubtargetFeature<"msync", "HasOnlyMSYNC", "true", 124 "Has only the msync instruction instead of sync", 125 [FeatureBookE]>; 126def FeatureE500 : SubtargetFeature<"e500", "IsE500", "true", 127 "Enable E500/E500mc instructions">; 128def FeatureSecurePlt : SubtargetFeature<"secure-plt","SecurePlt", "true", 129 "Enable secure plt mode">; 130def FeaturePPC4xx : SubtargetFeature<"ppc4xx", "IsPPC4xx", "true", 131 "Enable PPC 4xx instructions">; 132def FeaturePPC6xx : SubtargetFeature<"ppc6xx", "IsPPC6xx", "true", 133 "Enable PPC 6xx instructions">; 134def FeatureQPX : SubtargetFeature<"qpx","HasQPX", "true", 135 "Enable QPX instructions", 136 [FeatureFPU]>; 137def FeatureVSX : SubtargetFeature<"vsx","HasVSX", "true", 138 "Enable VSX instructions", 139 [FeatureAltivec]>; 140def FeatureTwoConstNR : 141 SubtargetFeature<"two-const-nr", "NeedsTwoConstNR", "true", 142 "Requires two constant Newton-Raphson computation">; 143def FeatureP8Altivec : SubtargetFeature<"power8-altivec", "HasP8Altivec", "true", 144 "Enable POWER8 Altivec instructions", 145 [FeatureAltivec]>; 146def FeatureP8Crypto : SubtargetFeature<"crypto", "HasP8Crypto", "true", 147 "Enable POWER8 Crypto instructions", 148 [FeatureP8Altivec]>; 149def FeatureP8Vector : SubtargetFeature<"power8-vector", "HasP8Vector", "true", 150 "Enable POWER8 vector instructions", 151 [FeatureVSX, FeatureP8Altivec]>; 152def FeatureDirectMove : 153 SubtargetFeature<"direct-move", "HasDirectMove", "true", 154 "Enable Power8 direct move instructions", 155 [FeatureVSX]>; 156def FeaturePartwordAtomic : SubtargetFeature<"partword-atomics", 157 "HasPartwordAtomics", "true", 158 "Enable l[bh]arx and st[bh]cx.">; 159def FeatureInvariantFunctionDescriptors : 160 SubtargetFeature<"invariant-function-descriptors", 161 "HasInvariantFunctionDescriptors", "true", 162 "Assume function descriptors are invariant">; 163def FeatureLongCall : SubtargetFeature<"longcall", "UseLongCalls", "true", 164 "Always use indirect calls">; 165def FeatureHTM : SubtargetFeature<"htm", "HasHTM", "true", 166 "Enable Hardware Transactional Memory instructions">; 167def FeatureMFTB : SubtargetFeature<"", "FeatureMFTB", "true", 168 "Implement mftb using the mfspr instruction">; 169def FeaturePPCPreRASched: 170 SubtargetFeature<"ppc-prera-sched", "UsePPCPreRASchedStrategy", "true", 171 "Use PowerPC pre-RA scheduling strategy">; 172def FeaturePPCPostRASched: 173 SubtargetFeature<"ppc-postra-sched", "UsePPCPostRASchedStrategy", "true", 174 "Use PowerPC post-RA scheduling strategy">; 175def FeatureFloat128 : 176 SubtargetFeature<"float128", "HasFloat128", "true", 177 "Enable the __float128 data type for IEEE-754R Binary128.", 178 [FeatureVSX]>; 179def FeaturePOPCNTD : SubtargetFeature<"popcntd","HasPOPCNTD", 180 "POPCNTD_Fast", 181 "Enable the popcnt[dw] instructions">; 182// Note that for the a2/a2q processor models we should not use popcnt[dw] by 183// default. These processors do support the instructions, but they're 184// microcoded, and the software emulation is about twice as fast. 185def FeatureSlowPOPCNTD : SubtargetFeature<"slow-popcntd","HasPOPCNTD", 186 "POPCNTD_Slow", 187 "Has slow popcnt[dw] instructions">; 188 189def DeprecatedDST : SubtargetFeature<"", "DeprecatedDST", "true", 190 "Treat vector data stream cache control instructions as deprecated">; 191 192def FeatureISA3_0 : SubtargetFeature<"isa-v30-instructions", "IsISA3_0", 193 "true", 194 "Enable instructions added in ISA 3.0.">; 195def FeatureP9Altivec : SubtargetFeature<"power9-altivec", "HasP9Altivec", "true", 196 "Enable POWER9 Altivec instructions", 197 [FeatureISA3_0, FeatureP8Altivec]>; 198def FeatureP9Vector : SubtargetFeature<"power9-vector", "HasP9Vector", "true", 199 "Enable POWER9 vector instructions", 200 [FeatureISA3_0, FeatureP8Vector, 201 FeatureP9Altivec]>; 202// A separate feature for this even though it is equivalent to P9Vector 203// because this is a feature of the implementation rather than the architecture 204// and may go away with future CPU's. 205def FeatureVectorsUseTwoUnits : SubtargetFeature<"vectors-use-two-units", 206 "VectorsUseTwoUnits", 207 "true", 208 "Vectors use two units">; 209 210// Since new processors generally contain a superset of features of those that 211// came before them, the idea is to make implementations of new processors 212// less error prone and easier to read. 213// Namely: 214// list<SubtargetFeature> P8InheritableFeatures = ... 215// list<SubtargetFeature> FutureProcessorAddtionalFeatures = 216// [ features that Power8 does not support but inheritable ] 217// list<SubtargetFeature> FutureProcessorSpecificFeatures = 218// [ features that Power8 does not support and not inheritable ] 219// list<SubtargetFeature> FutureProcessorInheritableFeatures = 220// !listconcat(P8InheritableFeatures, FutureProcessorAddtionalFeatures) 221// list<SubtargetFeature> FutureProcessorFeatures = 222// !listconcat(FutureProcessorInheritableFeatures, 223// FutureProcessorSpecificFeatures) 224 225// Makes it explicit and obvious what is new in FutureProcesor vs. Power8 as 226// well as providing a single point of definition if the feature set will be 227// used elsewhere. 228def ProcessorFeatures { 229 // Power7 230 list<SubtargetFeature> P7InheritableFeatures = [DirectivePwr7, 231 FeatureAltivec, 232 FeatureVSX, 233 FeatureMFOCRF, 234 FeatureFCPSGN, 235 FeatureFSqrt, 236 FeatureFRE, 237 FeatureFRES, 238 FeatureFRSQRTE, 239 FeatureFRSQRTES, 240 FeatureRecipPrec, 241 FeatureSTFIWX, 242 FeatureLFIWAX, 243 FeatureFPRND, 244 FeatureFPCVT, 245 FeatureISEL, 246 FeaturePOPCNTD, 247 FeatureCMPB, 248 FeatureLDBRX, 249 Feature64Bit, 250 /* Feature64BitRegs, */ 251 FeatureBPERMD, 252 FeatureExtDiv, 253 FeatureMFTB, 254 DeprecatedDST, 255 FeatureTwoConstNR]; 256 list<SubtargetFeature> P7SpecificFeatures = []; 257 list<SubtargetFeature> P7Features = 258 !listconcat(P7InheritableFeatures, P7SpecificFeatures); 259 260 // Power8 261 list<SubtargetFeature> P8AdditionalFeatures = [DirectivePwr8, 262 FeatureP8Altivec, 263 FeatureP8Vector, 264 FeatureP8Crypto, 265 FeatureHTM, 266 FeatureDirectMove, 267 FeatureICBT, 268 FeaturePartwordAtomic]; 269 list<SubtargetFeature> P8SpecificFeatures = []; 270 list<SubtargetFeature> P8InheritableFeatures = 271 !listconcat(P7InheritableFeatures, P8AdditionalFeatures); 272 list<SubtargetFeature> P8Features = 273 !listconcat(P8InheritableFeatures, P8SpecificFeatures); 274 275 // Power9 276 list<SubtargetFeature> P9AdditionalFeatures = [DirectivePwr9, 277 FeatureP9Altivec, 278 FeatureP9Vector, 279 FeatureISA3_0]; 280 // Some features are unique to Power9 and there is no reason to assume 281 // they will be part of any future CPUs. One example is the narrower 282 // dispatch for vector operations than scalar ones. For the time being, 283 // this list also includes scheduling-related features since we do not have 284 // enough info to create custom scheduling strategies for future CPUs. 285 list<SubtargetFeature> P9SpecificFeatures = [FeatureVectorsUseTwoUnits, 286 FeaturePPCPreRASched, 287 FeaturePPCPostRASched]; 288 list<SubtargetFeature> P9InheritableFeatures = 289 !listconcat(P8InheritableFeatures, P9AdditionalFeatures); 290 list<SubtargetFeature> P9Features = 291 !listconcat(P9InheritableFeatures, P9SpecificFeatures); 292 293 // Future 294 // For future CPU we assume that all of the existing features from Power 9 295 // still exist with the exception of those we know are Power 9 specific. 296 list<SubtargetFeature> FutureAdditionalFeatures = []; 297 list<SubtargetFeature> FutureSpecificFeatures = []; 298 list<SubtargetFeature> FutureInheritableFeatures = 299 !listconcat(P9InheritableFeatures, FutureAdditionalFeatures); 300 list<SubtargetFeature> FutureFeatures = 301 !listconcat(FutureInheritableFeatures, FutureSpecificFeatures); 302} 303 304// Note: Future features to add when support is extended to more 305// recent ISA levels: 306// 307// DFP p6, p6x, p7 decimal floating-point instructions 308// POPCNTB p5 through p7 popcntb and related instructions 309 310//===----------------------------------------------------------------------===// 311// Classes used for relation maps. 312//===----------------------------------------------------------------------===// 313// RecFormRel - Filter class used to relate non-record-form instructions with 314// their record-form variants. 315class RecFormRel; 316 317// AltVSXFMARel - Filter class used to relate the primary addend-killing VSX 318// FMA instruction forms with their corresponding factor-killing forms. 319class AltVSXFMARel { 320 bit IsVSXFMAAlt = 0; 321} 322 323//===----------------------------------------------------------------------===// 324// Relation Map Definitions. 325//===----------------------------------------------------------------------===// 326 327def getRecordFormOpcode : InstrMapping { 328 let FilterClass = "RecFormRel"; 329 // Instructions with the same BaseName and Interpretation64Bit values 330 // form a row. 331 let RowFields = ["BaseName", "Interpretation64Bit"]; 332 // Instructions with the same RC value form a column. 333 let ColFields = ["RC"]; 334 // The key column are the non-record-form instructions. 335 let KeyCol = ["0"]; 336 // Value columns RC=1 337 let ValueCols = [["1"]]; 338} 339 340def getNonRecordFormOpcode : InstrMapping { 341 let FilterClass = "RecFormRel"; 342 // Instructions with the same BaseName and Interpretation64Bit values 343 // form a row. 344 let RowFields = ["BaseName", "Interpretation64Bit"]; 345 // Instructions with the same RC value form a column. 346 let ColFields = ["RC"]; 347 // The key column are the record-form instructions. 348 let KeyCol = ["1"]; 349 // Value columns are RC=0 350 let ValueCols = [["0"]]; 351} 352 353def getAltVSXFMAOpcode : InstrMapping { 354 let FilterClass = "AltVSXFMARel"; 355 // Instructions with the same BaseName value form a row. 356 let RowFields = ["BaseName"]; 357 // Instructions with the same IsVSXFMAAlt value form a column. 358 let ColFields = ["IsVSXFMAAlt"]; 359 // The key column are the (default) addend-killing instructions. 360 let KeyCol = ["0"]; 361 // Value columns IsVSXFMAAlt=1 362 let ValueCols = [["1"]]; 363} 364 365//===----------------------------------------------------------------------===// 366// Register File Description 367//===----------------------------------------------------------------------===// 368 369include "PPCRegisterInfo.td" 370include "PPCSchedule.td" 371 372//===----------------------------------------------------------------------===// 373// PowerPC processors supported. 374// 375 376def : Processor<"generic", G3Itineraries, [Directive32, FeatureHardFloat, 377 FeatureMFTB]>; 378def : ProcessorModel<"440", PPC440Model, [Directive440, FeatureISEL, 379 FeatureFRES, FeatureFRSQRTE, 380 FeatureICBT, FeatureBookE, 381 FeatureMSYNC, FeatureMFTB]>; 382def : ProcessorModel<"450", PPC440Model, [Directive440, FeatureISEL, 383 FeatureFRES, FeatureFRSQRTE, 384 FeatureICBT, FeatureBookE, 385 FeatureMSYNC, FeatureMFTB]>; 386def : Processor<"601", G3Itineraries, [Directive601, FeatureFPU]>; 387def : Processor<"602", G3Itineraries, [Directive602, FeatureFPU, 388 FeatureMFTB]>; 389def : Processor<"603", G3Itineraries, [Directive603, 390 FeatureFRES, FeatureFRSQRTE, 391 FeatureMFTB]>; 392def : Processor<"603e", G3Itineraries, [Directive603, 393 FeatureFRES, FeatureFRSQRTE, 394 FeatureMFTB]>; 395def : Processor<"603ev", G3Itineraries, [Directive603, 396 FeatureFRES, FeatureFRSQRTE, 397 FeatureMFTB]>; 398def : Processor<"604", G3Itineraries, [Directive604, 399 FeatureFRES, FeatureFRSQRTE, 400 FeatureMFTB]>; 401def : Processor<"604e", G3Itineraries, [Directive604, 402 FeatureFRES, FeatureFRSQRTE, 403 FeatureMFTB]>; 404def : Processor<"620", G3Itineraries, [Directive620, 405 FeatureFRES, FeatureFRSQRTE, 406 FeatureMFTB]>; 407def : Processor<"750", G4Itineraries, [Directive750, 408 FeatureFRES, FeatureFRSQRTE, 409 FeatureMFTB]>; 410def : Processor<"g3", G3Itineraries, [Directive750, 411 FeatureFRES, FeatureFRSQRTE, 412 FeatureMFTB]>; 413def : Processor<"7400", G4Itineraries, [Directive7400, FeatureAltivec, 414 FeatureFRES, FeatureFRSQRTE, 415 FeatureMFTB]>; 416def : Processor<"g4", G4Itineraries, [Directive7400, FeatureAltivec, 417 FeatureFRES, FeatureFRSQRTE, 418 FeatureMFTB]>; 419def : Processor<"7450", G4PlusItineraries, [Directive7400, FeatureAltivec, 420 FeatureFRES, FeatureFRSQRTE, 421 FeatureMFTB]>; 422def : Processor<"g4+", G4PlusItineraries, [Directive7400, FeatureAltivec, 423 FeatureFRES, FeatureFRSQRTE, 424 FeatureMFTB]>; 425 426def : ProcessorModel<"970", G5Model, 427 [Directive970, FeatureAltivec, 428 FeatureMFOCRF, FeatureFSqrt, 429 FeatureFRES, FeatureFRSQRTE, FeatureSTFIWX, 430 Feature64Bit /*, Feature64BitRegs */, 431 FeatureMFTB]>; 432def : ProcessorModel<"g5", G5Model, 433 [Directive970, FeatureAltivec, 434 FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX, 435 FeatureFRES, FeatureFRSQRTE, 436 Feature64Bit /*, Feature64BitRegs */, 437 FeatureMFTB, DeprecatedDST]>; 438def : ProcessorModel<"e500", PPCE500Model, 439 [DirectiveE500, 440 FeatureICBT, FeatureBookE, 441 FeatureISEL, FeatureMFTB, FeatureMSYNC, FeatureSPE]>; 442def : ProcessorModel<"e500mc", PPCE500mcModel, 443 [DirectiveE500mc, 444 FeatureSTFIWX, FeatureICBT, FeatureBookE, 445 FeatureISEL, FeatureMFTB]>; 446def : ProcessorModel<"e5500", PPCE5500Model, 447 [DirectiveE5500, FeatureMFOCRF, Feature64Bit, 448 FeatureSTFIWX, FeatureICBT, FeatureBookE, 449 FeatureISEL, FeatureMFTB]>; 450def : ProcessorModel<"a2", PPCA2Model, 451 [DirectiveA2, FeatureICBT, FeatureBookE, FeatureMFOCRF, 452 FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES, 453 FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec, 454 FeatureSTFIWX, FeatureLFIWAX, 455 FeatureFPRND, FeatureFPCVT, FeatureISEL, 456 FeatureSlowPOPCNTD, FeatureCMPB, FeatureLDBRX, 457 Feature64Bit /*, Feature64BitRegs */, FeatureMFTB]>; 458def : ProcessorModel<"a2q", PPCA2Model, 459 [DirectiveA2, FeatureICBT, FeatureBookE, FeatureMFOCRF, 460 FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES, 461 FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec, 462 FeatureSTFIWX, FeatureLFIWAX, 463 FeatureFPRND, FeatureFPCVT, FeatureISEL, 464 FeatureSlowPOPCNTD, FeatureCMPB, FeatureLDBRX, 465 Feature64Bit /*, Feature64BitRegs */, FeatureQPX, 466 FeatureMFTB]>; 467def : ProcessorModel<"pwr3", G5Model, 468 [DirectivePwr3, FeatureAltivec, 469 FeatureFRES, FeatureFRSQRTE, FeatureMFOCRF, 470 FeatureSTFIWX, Feature64Bit]>; 471def : ProcessorModel<"pwr4", G5Model, 472 [DirectivePwr4, FeatureAltivec, FeatureMFOCRF, 473 FeatureFSqrt, FeatureFRES, FeatureFRSQRTE, 474 FeatureSTFIWX, Feature64Bit, FeatureMFTB]>; 475def : ProcessorModel<"pwr5", G5Model, 476 [DirectivePwr5, FeatureAltivec, FeatureMFOCRF, 477 FeatureFSqrt, FeatureFRE, FeatureFRES, 478 FeatureFRSQRTE, FeatureFRSQRTES, 479 FeatureSTFIWX, Feature64Bit, 480 FeatureMFTB, DeprecatedDST]>; 481def : ProcessorModel<"pwr5x", G5Model, 482 [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF, 483 FeatureFSqrt, FeatureFRE, FeatureFRES, 484 FeatureFRSQRTE, FeatureFRSQRTES, 485 FeatureSTFIWX, FeatureFPRND, Feature64Bit, 486 FeatureMFTB, DeprecatedDST]>; 487def : ProcessorModel<"pwr6", G5Model, 488 [DirectivePwr6, FeatureAltivec, 489 FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE, 490 FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES, 491 FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX, FeatureCMPB, 492 FeatureFPRND, Feature64Bit /*, Feature64BitRegs */, 493 FeatureMFTB, DeprecatedDST]>; 494def : ProcessorModel<"pwr6x", G5Model, 495 [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF, 496 FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES, 497 FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec, 498 FeatureSTFIWX, FeatureLFIWAX, FeatureCMPB, 499 FeatureFPRND, Feature64Bit, 500 FeatureMFTB, DeprecatedDST]>; 501def : ProcessorModel<"pwr7", P7Model, ProcessorFeatures.P7Features>; 502def : ProcessorModel<"pwr8", P8Model, ProcessorFeatures.P8Features>; 503def : ProcessorModel<"pwr9", P9Model, ProcessorFeatures.P9Features>; 504// No scheduler model for future CPU. 505def : ProcessorModel<"future", NoSchedModel, 506 ProcessorFeatures.FutureFeatures>; 507def : Processor<"ppc", G3Itineraries, [Directive32, FeatureHardFloat, 508 FeatureMFTB]>; 509def : Processor<"ppc32", G3Itineraries, [Directive32, FeatureHardFloat, 510 FeatureMFTB]>; 511def : ProcessorModel<"ppc64", G5Model, 512 [Directive64, FeatureAltivec, 513 FeatureMFOCRF, FeatureFSqrt, FeatureFRES, 514 FeatureFRSQRTE, FeatureSTFIWX, 515 Feature64Bit /*, Feature64BitRegs */, 516 FeatureMFTB]>; 517def : ProcessorModel<"ppc64le", P8Model, ProcessorFeatures.P8Features>; 518 519//===----------------------------------------------------------------------===// 520// Calling Conventions 521//===----------------------------------------------------------------------===// 522 523include "PPCCallingConv.td" 524 525def PPCInstrInfo : InstrInfo { 526 let isLittleEndianEncoding = 1; 527 528 // FIXME: Unset this when no longer needed! 529 let decodePositionallyEncodedOperands = 1; 530 531 let noNamedPositionallyEncodedOperands = 1; 532} 533 534def PPCAsmParser : AsmParser { 535 let ShouldEmitMatchRegisterName = 0; 536} 537 538def PPCAsmParserVariant : AsmParserVariant { 539 int Variant = 0; 540 541 // We do not use hard coded registers in asm strings. However, some 542 // InstAlias definitions use immediate literals. Set RegisterPrefix 543 // so that those are not misinterpreted as registers. 544 string RegisterPrefix = "%"; 545 string BreakCharacters = "."; 546} 547 548def PPC : Target { 549 // Information about the instructions. 550 let InstructionSet = PPCInstrInfo; 551 552 let AssemblyParsers = [PPCAsmParser]; 553 let AssemblyParserVariants = [PPCAsmParserVariant]; 554 let AllowRegisterRenaming = 1; 555} 556 557//===----------------------------------------------------------------------===// 558// Pfm Counters 559//===----------------------------------------------------------------------===// 560 561include "PPCPfmCounters.td" 562