MipsSubtarget.h revision 360784 
1//===-- MipsSubtarget.h - Define Subtarget for the Mips ---------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file declares the Mips specific subclass of TargetSubtargetInfo.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_MIPS_MIPSSUBTARGET_H
14#define LLVM_LIB_TARGET_MIPS_MIPSSUBTARGET_H
15
16#include "MCTargetDesc/MipsABIInfo.h"
17#include "MipsFrameLowering.h"
18#include "MipsISelLowering.h"
19#include "MipsInstrInfo.h"
20#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
21#include "llvm/CodeGen/TargetSubtargetInfo.h"
22#include "llvm/CodeGen/GlobalISel/CallLowering.h"
23#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
24#include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
25#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
26#include "llvm/IR/DataLayout.h"
27#include "llvm/MC/MCInstrItineraries.h"
28#include "llvm/Support/ErrorHandling.h"
29#include <string>
30
31#define GET_SUBTARGETINFO_HEADER
32#include "MipsGenSubtargetInfo.inc"
33
34namespace llvm {
35class StringRef;
36
37class MipsTargetMachine;
38
39class MipsSubtarget : public MipsGenSubtargetInfo {
40  virtual void anchor();
41
42  enum MipsArchEnum {
43    MipsDefault,
44    Mips1, Mips2, Mips32, Mips32r2, Mips32r3, Mips32r5, Mips32r6, Mips32Max,
45    Mips3, Mips4, Mips5, Mips64, Mips64r2, Mips64r3, Mips64r5, Mips64r6
46  };
47
48  enum class CPU { P5600 };
49
50  // Used to avoid printing dsp warnings multiple times.
51  static bool DspWarningPrinted;
52
53  // Used to avoid printing msa warnings multiple times.
54  static bool MSAWarningPrinted;
55
56  // Used to avoid printing crc warnings multiple times.
57  static bool CRCWarningPrinted;
58
59  // Used to avoid printing ginv warnings multiple times.
60  static bool GINVWarningPrinted;
61
62  // Used to avoid printing virt warnings multiple times.
63  static bool VirtWarningPrinted;
64
65  // Mips architecture version
66  MipsArchEnum MipsArchVersion;
67
68  // Processor implementation (unused but required to exist by
69  // tablegen-erated code).
70  CPU ProcImpl;
71
72  // IsLittle - The target is Little Endian
73  bool IsLittle;
74
75  // IsSoftFloat - The target does not support any floating point instructions.
76  bool IsSoftFloat;
77
78  // IsSingleFloat - The target only supports single precision float
79  // point operations. This enable the target to use all 32 32-bit
80  // floating point registers instead of only using even ones.
81  bool IsSingleFloat;
82
83  // IsFPXX - MIPS O32 modeless ABI.
84  bool IsFPXX;
85
86  // NoABICalls - Disable SVR4-style position-independent code.
87  bool NoABICalls;
88
89  // Abs2008 - Use IEEE 754-2008 abs.fmt instruction.
90  bool Abs2008;
91
92  // IsFP64bit - The target processor has 64-bit floating point registers.
93  bool IsFP64bit;
94
95  /// Are odd single-precision registers permitted?
96  /// This corresponds to -modd-spreg and -mno-odd-spreg
97  bool UseOddSPReg;
98
99  // IsNan2008 - IEEE 754-2008 NaN encoding.
100  bool IsNaN2008bit;
101
102  // IsGP64bit - General-purpose registers are 64 bits wide
103  bool IsGP64bit;
104
105  // IsPTR64bit - Pointers are 64 bit wide
106  bool IsPTR64bit;
107
108  // HasVFPU - Processor has a vector floating point unit.
109  bool HasVFPU;
110
111  // CPU supports cnMIPS (Cavium Networks Octeon CPU).
112  bool HasCnMips;
113
114  // CPU supports cnMIPSP (Cavium Networks Octeon+ CPU).
115  bool HasCnMipsP;
116
117  // isLinux - Target system is Linux. Is false we consider ELFOS for now.
118  bool IsLinux;
119
120  // UseSmallSection - Small section is used.
121  bool UseSmallSection;
122
123  /// Features related to the presence of specific instructions.
124
125  // HasMips3_32 - The subset of MIPS-III instructions added to MIPS32
126  bool HasMips3_32;
127
128  // HasMips3_32r2 - The subset of MIPS-III instructions added to MIPS32r2
129  bool HasMips3_32r2;
130
131  // HasMips4_32 - Has the subset of MIPS-IV present in MIPS32
132  bool HasMips4_32;
133
134  // HasMips4_32r2 - Has the subset of MIPS-IV present in MIPS32r2
135  bool HasMips4_32r2;
136
137  // HasMips5_32r2 - Has the subset of MIPS-V present in MIPS32r2
138  bool HasMips5_32r2;
139
140  // InMips16 -- can process Mips16 instructions
141  bool InMips16Mode;
142
143  // Mips16 hard float
144  bool InMips16HardFloat;
145
146  // InMicroMips -- can process MicroMips instructions
147  bool InMicroMipsMode;
148
149  // HasDSP, HasDSPR2, HasDSPR3 -- supports DSP ASE.
150  bool HasDSP, HasDSPR2, HasDSPR3;
151
152  // Allow mixed Mips16 and Mips32 in one source file
153  bool AllowMixed16_32;
154
155  // Optimize for space by compiling all functions as Mips 16 unless
156  // it needs floating point. Functions needing floating point are
157  // compiled as Mips32
158  bool Os16;
159
160  // HasMSA -- supports MSA ASE.
161  bool HasMSA;
162
163  // UseTCCInDIV -- Enables the use of trapping in the assembler.
164  bool UseTCCInDIV;
165
166  // Sym32 -- On Mips64 symbols are 32 bits.
167  bool HasSym32;
168
169  // HasEVA -- supports EVA ASE.
170  bool HasEVA;
171
172  // nomadd4 - disables generation of 4-operand madd.s, madd.d and
173  // related instructions.
174  bool DisableMadd4;
175
176  // HasMT -- support MT ASE.
177  bool HasMT;
178
179  // HasCRC -- supports R6 CRC ASE
180  bool HasCRC;
181
182  // HasVirt -- supports Virtualization ASE
183  bool HasVirt;
184
185  // HasGINV -- supports R6 Global INValidate ASE
186  bool HasGINV;
187
188  // Use hazard variants of the jump register instructions for indirect
189  // function calls and jump tables.
190  bool UseIndirectJumpsHazard;
191
192  // Disable use of the `jal` instruction.
193  bool UseLongCalls = false;
194
195  // Assume 32-bit GOT.
196  bool UseXGOT = false;
197
198  /// The minimum alignment known to hold of the stack frame on
199  /// entry to the function and which must be maintained by every function.
200  Align stackAlignment;
201
202  /// The overridden stack alignment.
203  MaybeAlign StackAlignOverride;
204
205  InstrItineraryData InstrItins;
206
207  // We can override the determination of whether we are in mips16 mode
208  // as from the command line
209  enum {NoOverride, Mips16Override, NoMips16Override} OverrideMode;
210
211  const MipsTargetMachine &TM;
212
213  Triple TargetTriple;
214
215  const SelectionDAGTargetInfo TSInfo;
216  std::unique_ptr<const MipsInstrInfo> InstrInfo;
217  std::unique_ptr<const MipsFrameLowering> FrameLowering;
218  std::unique_ptr<const MipsTargetLowering> TLInfo;
219
220public:
221  bool isPositionIndependent() const;
222  /// This overrides the PostRAScheduler bit in the SchedModel for each CPU.
223  bool enablePostRAScheduler() const override;
224  void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override;
225  CodeGenOpt::Level getOptLevelToEnablePostRAScheduler() const override;
226
227  bool isABI_N64() const;
228  bool isABI_N32() const;
229  bool isABI_O32() const;
230  const MipsABIInfo &getABI() const;
231  bool isABI_FPXX() const { return isABI_O32() && IsFPXX; }
232
233  /// This constructor initializes the data members to match that
234  /// of the specified triple.
235  MipsSubtarget(const Triple &TT, StringRef CPU, StringRef FS, bool little,
236                const MipsTargetMachine &TM, MaybeAlign StackAlignOverride);
237
238  /// ParseSubtargetFeatures - Parses features string setting specified
239  /// subtarget options.  Definition of function is auto generated by tblgen.
240  void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
241
242  bool hasMips1() const { return MipsArchVersion >= Mips1; }
243  bool hasMips2() const { return MipsArchVersion >= Mips2; }
244  bool hasMips3() const { return MipsArchVersion >= Mips3; }
245  bool hasMips4() const { return MipsArchVersion >= Mips4; }
246  bool hasMips5() const { return MipsArchVersion >= Mips5; }
247  bool hasMips4_32() const { return HasMips4_32; }
248  bool hasMips4_32r2() const { return HasMips4_32r2; }
249  bool hasMips32() const {
250    return (MipsArchVersion >= Mips32 && MipsArchVersion < Mips32Max) ||
251           hasMips64();
252  }
253  bool hasMips32r2() const {
254    return (MipsArchVersion >= Mips32r2 && MipsArchVersion < Mips32Max) ||
255           hasMips64r2();
256  }
257  bool hasMips32r3() const {
258    return (MipsArchVersion >= Mips32r3 && MipsArchVersion < Mips32Max) ||
259           hasMips64r2();
260  }
261  bool hasMips32r5() const {
262    return (MipsArchVersion >= Mips32r5 && MipsArchVersion < Mips32Max) ||
263           hasMips64r5();
264  }
265  bool hasMips32r6() const {
266    return (MipsArchVersion >= Mips32r6 && MipsArchVersion < Mips32Max) ||
267           hasMips64r6();
268  }
269  bool hasMips64() const { return MipsArchVersion >= Mips64; }
270  bool hasMips64r2() const { return MipsArchVersion >= Mips64r2; }
271  bool hasMips64r3() const { return MipsArchVersion >= Mips64r3; }
272  bool hasMips64r5() const { return MipsArchVersion >= Mips64r5; }
273  bool hasMips64r6() const { return MipsArchVersion >= Mips64r6; }
274
275  bool hasCnMips() const { return HasCnMips; }
276  bool hasCnMipsP() const { return HasCnMipsP; }
277
278  bool isLittle() const { return IsLittle; }
279  bool isABICalls() const { return !NoABICalls; }
280  bool isFPXX() const { return IsFPXX; }
281  bool isFP64bit() const { return IsFP64bit; }
282  bool useOddSPReg() const { return UseOddSPReg; }
283  bool noOddSPReg() const { return !UseOddSPReg; }
284  bool isNaN2008() const { return IsNaN2008bit; }
285  bool inAbs2008Mode() const { return Abs2008; }
286  bool isGP64bit() const { return IsGP64bit; }
287  bool isGP32bit() const { return !IsGP64bit; }
288  unsigned getGPRSizeInBytes() const { return isGP64bit() ? 8 : 4; }
289  bool isPTR64bit() const { return IsPTR64bit; }
290  bool isPTR32bit() const { return !IsPTR64bit; }
291  bool hasSym32() const {
292    return (HasSym32 && isABI_N64()) || isABI_N32() || isABI_O32();
293  }
294  bool isSingleFloat() const { return IsSingleFloat; }
295  bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
296  bool hasVFPU() const { return HasVFPU; }
297  bool inMips16Mode() const { return InMips16Mode; }
298  bool inMips16ModeDefault() const {
299    return InMips16Mode;
300  }
301  // Hard float for mips16 means essentially to compile as soft float
302  // but to use a runtime library for soft float that is written with
303  // native mips32 floating point instructions (those runtime routines
304  // run in mips32 hard float mode).
305  bool inMips16HardFloat() const {
306    return inMips16Mode() && InMips16HardFloat;
307  }
308  bool inMicroMipsMode() const { return InMicroMipsMode && !InMips16Mode; }
309  bool inMicroMips32r6Mode() const {
310    return inMicroMipsMode() && hasMips32r6();
311  }
312  bool hasDSP() const { return HasDSP; }
313  bool hasDSPR2() const { return HasDSPR2; }
314  bool hasDSPR3() const { return HasDSPR3; }
315  bool hasMSA() const { return HasMSA; }
316  bool disableMadd4() const { return DisableMadd4; }
317  bool hasEVA() const { return HasEVA; }
318  bool hasMT() const { return HasMT; }
319  bool hasCRC() const { return HasCRC; }
320  bool hasVirt() const { return HasVirt; }
321  bool hasGINV() const { return HasGINV; }
322  bool useIndirectJumpsHazard() const {
323    return UseIndirectJumpsHazard && hasMips32r2();
324  }
325  bool useSmallSection() const { return UseSmallSection; }
326
327  bool hasStandardEncoding() const { return !InMips16Mode && !InMicroMipsMode; }
328
329  bool useSoftFloat() const { return IsSoftFloat; }
330
331  bool useLongCalls() const { return UseLongCalls; }
332
333  bool useXGOT() const { return UseXGOT; }
334
335  bool enableLongBranchPass() const {
336    return hasStandardEncoding() || inMicroMipsMode() || allowMixed16_32();
337  }
338
339  /// Features related to the presence of specific instructions.
340  bool hasExtractInsert() const { return !inMips16Mode() && hasMips32r2(); }
341  bool hasMTHC1() const { return hasMips32r2(); }
342
343  bool allowMixed16_32() const { return inMips16ModeDefault() |
344                                        AllowMixed16_32; }
345
346  bool os16() const { return Os16; }
347
348  bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
349
350  bool isXRaySupported() const override { return true; }
351
352  // for now constant islands are on for the whole compilation unit but we only
353  // really use them if in addition we are in mips16 mode
354  static bool useConstantIslands();
355
356  Align getStackAlignment() const { return stackAlignment; }
357
358  // Grab relocation model
359  Reloc::Model getRelocationModel() const;
360
361  MipsSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS,
362                                                 const TargetMachine &TM);
363
364  /// Does the system support unaligned memory access.
365  ///
366  /// MIPS32r6/MIPS64r6 require full unaligned access support but does not
367  /// specify which component of the system provides it. Hardware, software, and
368  /// hybrid implementations are all valid.
369  bool systemSupportsUnalignedAccess() const { return hasMips32r6(); }
370
371  // Set helper classes
372  void setHelperClassesMips16();
373  void setHelperClassesMipsSE();
374
375  const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
376    return &TSInfo;
377  }
378  const MipsInstrInfo *getInstrInfo() const override { return InstrInfo.get(); }
379  const TargetFrameLowering *getFrameLowering() const override {
380    return FrameLowering.get();
381  }
382  const MipsRegisterInfo *getRegisterInfo() const override {
383    return &InstrInfo->getRegisterInfo();
384  }
385  const MipsTargetLowering *getTargetLowering() const override {
386    return TLInfo.get();
387  }
388  const InstrItineraryData *getInstrItineraryData() const override {
389    return &InstrItins;
390  }
391
392protected:
393  // GlobalISel related APIs.
394  std::unique_ptr<CallLowering> CallLoweringInfo;
395  std::unique_ptr<LegalizerInfo> Legalizer;
396  std::unique_ptr<RegisterBankInfo> RegBankInfo;
397  std::unique_ptr<InstructionSelector> InstSelector;
398
399public:
400  const CallLowering *getCallLowering() const override;
401  const LegalizerInfo *getLegalizerInfo() const override;
402  const RegisterBankInfo *getRegBankInfo() const override;
403  InstructionSelector *getInstructionSelector() const override;
404};
405} // End llvm namespace
406
407#endif
408