MipsMSAInstrInfo.td revision 360784
1//===- MipsMSAInstrInfo.td - MSA ASE instructions -*- tablegen ------------*-=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes Mips MSA ASE instructions. 10// 11//===----------------------------------------------------------------------===// 12 13def SDT_MipsVecCond : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVec<1>]>; 14def SDT_VSetCC : SDTypeProfile<1, 3, [SDTCisInt<0>, 15 SDTCisInt<1>, 16 SDTCisSameAs<1, 2>, 17 SDTCisVT<3, OtherVT>]>; 18def SDT_VFSetCC : SDTypeProfile<1, 3, [SDTCisInt<0>, 19 SDTCisFP<1>, 20 SDTCisSameAs<1, 2>, 21 SDTCisVT<3, OtherVT>]>; 22def SDT_VSHF : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisVec<0>, 23 SDTCisInt<1>, SDTCisVec<1>, 24 SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>]>; 25def SDT_SHF : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisVec<0>, 26 SDTCisVT<1, i32>, SDTCisSameAs<0, 2>]>; 27def SDT_ILV : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisVec<0>, 28 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>]>; 29def SDT_INSVE : SDTypeProfile<1, 4, [SDTCisVec<0>, SDTCisSameAs<0, 1>, 30 SDTCisVT<2, i32>, SDTCisSameAs<0, 3>, 31 SDTCisVT<4, i32>]>; 32 33def MipsVAllNonZero : SDNode<"MipsISD::VALL_NONZERO", SDT_MipsVecCond>; 34def MipsVAnyNonZero : SDNode<"MipsISD::VANY_NONZERO", SDT_MipsVecCond>; 35def MipsVAllZero : SDNode<"MipsISD::VALL_ZERO", SDT_MipsVecCond>; 36def MipsVAnyZero : SDNode<"MipsISD::VANY_ZERO", SDT_MipsVecCond>; 37def MipsVNOR : SDNode<"MipsISD::VNOR", SDTIntBinOp, 38 [SDNPCommutative, SDNPAssociative]>; 39def MipsVSHF : SDNode<"MipsISD::VSHF", SDT_VSHF>; 40def MipsSHF : SDNode<"MipsISD::SHF", SDT_SHF>; 41def MipsILVEV : SDNode<"MipsISD::ILVEV", SDT_ILV>; 42def MipsILVOD : SDNode<"MipsISD::ILVOD", SDT_ILV>; 43def MipsILVL : SDNode<"MipsISD::ILVL", SDT_ILV>; 44def MipsILVR : SDNode<"MipsISD::ILVR", SDT_ILV>; 45def MipsPCKEV : SDNode<"MipsISD::PCKEV", SDT_ILV>; 46def MipsPCKOD : SDNode<"MipsISD::PCKOD", SDT_ILV>; 47def MipsINSVE : SDNode<"MipsISD::INSVE", SDT_INSVE>; 48def MipsFMS : SDNode<"MipsISD::FMS", SDTFPTernaryOp>; 49 50def vsetcc : SDNode<"ISD::SETCC", SDT_VSetCC>; 51def vfsetcc : SDNode<"ISD::SETCC", SDT_VFSetCC>; 52 53def MipsVExtractSExt : SDNode<"MipsISD::VEXTRACT_SEXT_ELT", 54 SDTypeProfile<1, 3, [SDTCisPtrTy<2>]>, []>; 55def MipsVExtractZExt : SDNode<"MipsISD::VEXTRACT_ZEXT_ELT", 56 SDTypeProfile<1, 3, [SDTCisPtrTy<2>]>, []>; 57 58def immZExt1Ptr : ImmLeaf<iPTR, [{return isUInt<1>(Imm);}]>; 59def immZExt2Ptr : ImmLeaf<iPTR, [{return isUInt<2>(Imm);}]>; 60def immZExt3Ptr : ImmLeaf<iPTR, [{return isUInt<3>(Imm);}]>; 61def immZExt4Ptr : ImmLeaf<iPTR, [{return isUInt<4>(Imm);}]>; 62 63def timmZExt1Ptr : TImmLeaf<iPTR, [{return isUInt<1>(Imm);}]>; 64def timmZExt2Ptr : TImmLeaf<iPTR, [{return isUInt<2>(Imm);}]>; 65def timmZExt3Ptr : TImmLeaf<iPTR, [{return isUInt<3>(Imm);}]>; 66def timmZExt4Ptr : TImmLeaf<iPTR, [{return isUInt<4>(Imm);}]>; 67 68// Operands 69 70def immZExt2Lsa : ImmLeaf<i32, [{return isUInt<2>(Imm - 1);}]>; 71 72// Pattern fragments 73def vextract_sext_i8 : PatFrag<(ops node:$vec, node:$idx), 74 (MipsVExtractSExt node:$vec, node:$idx, i8)>; 75def vextract_sext_i16 : PatFrag<(ops node:$vec, node:$idx), 76 (MipsVExtractSExt node:$vec, node:$idx, i16)>; 77def vextract_sext_i32 : PatFrag<(ops node:$vec, node:$idx), 78 (MipsVExtractSExt node:$vec, node:$idx, i32)>; 79def vextract_sext_i64 : PatFrag<(ops node:$vec, node:$idx), 80 (MipsVExtractSExt node:$vec, node:$idx, i64)>; 81 82def vextract_zext_i8 : PatFrag<(ops node:$vec, node:$idx), 83 (MipsVExtractZExt node:$vec, node:$idx, i8)>; 84def vextract_zext_i16 : PatFrag<(ops node:$vec, node:$idx), 85 (MipsVExtractZExt node:$vec, node:$idx, i16)>; 86def vextract_zext_i32 : PatFrag<(ops node:$vec, node:$idx), 87 (MipsVExtractZExt node:$vec, node:$idx, i32)>; 88def vextract_zext_i64 : PatFrag<(ops node:$vec, node:$idx), 89 (MipsVExtractZExt node:$vec, node:$idx, i64)>; 90 91def vinsert_v16i8 : PatFrag<(ops node:$vec, node:$val, node:$idx), 92 (v16i8 (vector_insert node:$vec, node:$val, node:$idx))>; 93def vinsert_v8i16 : PatFrag<(ops node:$vec, node:$val, node:$idx), 94 (v8i16 (vector_insert node:$vec, node:$val, node:$idx))>; 95def vinsert_v4i32 : PatFrag<(ops node:$vec, node:$val, node:$idx), 96 (v4i32 (vector_insert node:$vec, node:$val, node:$idx))>; 97def vinsert_v2i64 : PatFrag<(ops node:$vec, node:$val, node:$idx), 98 (v2i64 (vector_insert node:$vec, node:$val, node:$idx))>; 99 100def insve_v16i8 : PatFrag<(ops node:$v1, node:$i1, node:$v2, node:$i2), 101 (v16i8 (MipsINSVE node:$v1, node:$i1, node:$v2, node:$i2))>; 102def insve_v8i16 : PatFrag<(ops node:$v1, node:$i1, node:$v2, node:$i2), 103 (v8i16 (MipsINSVE node:$v1, node:$i1, node:$v2, node:$i2))>; 104def insve_v4i32 : PatFrag<(ops node:$v1, node:$i1, node:$v2, node:$i2), 105 (v4i32 (MipsINSVE node:$v1, node:$i1, node:$v2, node:$i2))>; 106def insve_v2i64 : PatFrag<(ops node:$v1, node:$i1, node:$v2, node:$i2), 107 (v2i64 (MipsINSVE node:$v1, node:$i1, node:$v2, node:$i2))>; 108 109class vfsetcc_type<ValueType ResTy, ValueType OpTy, CondCode CC> : 110 PatFrag<(ops node:$lhs, node:$rhs), 111 (ResTy (vfsetcc (OpTy node:$lhs), (OpTy node:$rhs), CC))>; 112 113// ISD::SETFALSE cannot occur 114def vfseteq_v4f32 : vfsetcc_type<v4i32, v4f32, SETEQ>; 115def vfseteq_v2f64 : vfsetcc_type<v2i64, v2f64, SETEQ>; 116def vfsetge_v4f32 : vfsetcc_type<v4i32, v4f32, SETGE>; 117def vfsetge_v2f64 : vfsetcc_type<v2i64, v2f64, SETGE>; 118def vfsetgt_v4f32 : vfsetcc_type<v4i32, v4f32, SETGT>; 119def vfsetgt_v2f64 : vfsetcc_type<v2i64, v2f64, SETGT>; 120def vfsetle_v4f32 : vfsetcc_type<v4i32, v4f32, SETLE>; 121def vfsetle_v2f64 : vfsetcc_type<v2i64, v2f64, SETLE>; 122def vfsetlt_v4f32 : vfsetcc_type<v4i32, v4f32, SETLT>; 123def vfsetlt_v2f64 : vfsetcc_type<v2i64, v2f64, SETLT>; 124def vfsetne_v4f32 : vfsetcc_type<v4i32, v4f32, SETNE>; 125def vfsetne_v2f64 : vfsetcc_type<v2i64, v2f64, SETNE>; 126def vfsetoeq_v4f32 : vfsetcc_type<v4i32, v4f32, SETOEQ>; 127def vfsetoeq_v2f64 : vfsetcc_type<v2i64, v2f64, SETOEQ>; 128def vfsetoge_v4f32 : vfsetcc_type<v4i32, v4f32, SETOGE>; 129def vfsetoge_v2f64 : vfsetcc_type<v2i64, v2f64, SETOGE>; 130def vfsetogt_v4f32 : vfsetcc_type<v4i32, v4f32, SETOGT>; 131def vfsetogt_v2f64 : vfsetcc_type<v2i64, v2f64, SETOGT>; 132def vfsetole_v4f32 : vfsetcc_type<v4i32, v4f32, SETOLE>; 133def vfsetole_v2f64 : vfsetcc_type<v2i64, v2f64, SETOLE>; 134def vfsetolt_v4f32 : vfsetcc_type<v4i32, v4f32, SETOLT>; 135def vfsetolt_v2f64 : vfsetcc_type<v2i64, v2f64, SETOLT>; 136def vfsetone_v4f32 : vfsetcc_type<v4i32, v4f32, SETONE>; 137def vfsetone_v2f64 : vfsetcc_type<v2i64, v2f64, SETONE>; 138def vfsetord_v4f32 : vfsetcc_type<v4i32, v4f32, SETO>; 139def vfsetord_v2f64 : vfsetcc_type<v2i64, v2f64, SETO>; 140def vfsetun_v4f32 : vfsetcc_type<v4i32, v4f32, SETUO>; 141def vfsetun_v2f64 : vfsetcc_type<v2i64, v2f64, SETUO>; 142def vfsetueq_v4f32 : vfsetcc_type<v4i32, v4f32, SETUEQ>; 143def vfsetueq_v2f64 : vfsetcc_type<v2i64, v2f64, SETUEQ>; 144def vfsetuge_v4f32 : vfsetcc_type<v4i32, v4f32, SETUGE>; 145def vfsetuge_v2f64 : vfsetcc_type<v2i64, v2f64, SETUGE>; 146def vfsetugt_v4f32 : vfsetcc_type<v4i32, v4f32, SETUGT>; 147def vfsetugt_v2f64 : vfsetcc_type<v2i64, v2f64, SETUGT>; 148def vfsetule_v4f32 : vfsetcc_type<v4i32, v4f32, SETULE>; 149def vfsetule_v2f64 : vfsetcc_type<v2i64, v2f64, SETULE>; 150def vfsetult_v4f32 : vfsetcc_type<v4i32, v4f32, SETULT>; 151def vfsetult_v2f64 : vfsetcc_type<v2i64, v2f64, SETULT>; 152def vfsetune_v4f32 : vfsetcc_type<v4i32, v4f32, SETUNE>; 153def vfsetune_v2f64 : vfsetcc_type<v2i64, v2f64, SETUNE>; 154// ISD::SETTRUE cannot occur 155// ISD::SETFALSE2 cannot occur 156// ISD::SETTRUE2 cannot occur 157 158class vsetcc_type<ValueType ResTy, CondCode CC> : 159 PatFrag<(ops node:$lhs, node:$rhs), 160 (ResTy (vsetcc node:$lhs, node:$rhs, CC))>; 161 162def vseteq_v16i8 : vsetcc_type<v16i8, SETEQ>; 163def vseteq_v8i16 : vsetcc_type<v8i16, SETEQ>; 164def vseteq_v4i32 : vsetcc_type<v4i32, SETEQ>; 165def vseteq_v2i64 : vsetcc_type<v2i64, SETEQ>; 166def vsetle_v16i8 : vsetcc_type<v16i8, SETLE>; 167def vsetle_v8i16 : vsetcc_type<v8i16, SETLE>; 168def vsetle_v4i32 : vsetcc_type<v4i32, SETLE>; 169def vsetle_v2i64 : vsetcc_type<v2i64, SETLE>; 170def vsetlt_v16i8 : vsetcc_type<v16i8, SETLT>; 171def vsetlt_v8i16 : vsetcc_type<v8i16, SETLT>; 172def vsetlt_v4i32 : vsetcc_type<v4i32, SETLT>; 173def vsetlt_v2i64 : vsetcc_type<v2i64, SETLT>; 174def vsetule_v16i8 : vsetcc_type<v16i8, SETULE>; 175def vsetule_v8i16 : vsetcc_type<v8i16, SETULE>; 176def vsetule_v4i32 : vsetcc_type<v4i32, SETULE>; 177def vsetule_v2i64 : vsetcc_type<v2i64, SETULE>; 178def vsetult_v16i8 : vsetcc_type<v16i8, SETULT>; 179def vsetult_v8i16 : vsetcc_type<v8i16, SETULT>; 180def vsetult_v4i32 : vsetcc_type<v4i32, SETULT>; 181def vsetult_v2i64 : vsetcc_type<v2i64, SETULT>; 182 183def vsplati8 : PatFrag<(ops node:$e0), 184 (v16i8 (build_vector node:$e0, node:$e0, 185 node:$e0, node:$e0, 186 node:$e0, node:$e0, 187 node:$e0, node:$e0, 188 node:$e0, node:$e0, 189 node:$e0, node:$e0, 190 node:$e0, node:$e0, 191 node:$e0, node:$e0))>; 192def vsplati16 : PatFrag<(ops node:$e0), 193 (v8i16 (build_vector node:$e0, node:$e0, 194 node:$e0, node:$e0, 195 node:$e0, node:$e0, 196 node:$e0, node:$e0))>; 197def vsplati32 : PatFrag<(ops node:$e0), 198 (v4i32 (build_vector node:$e0, node:$e0, 199 node:$e0, node:$e0))>; 200 201def vsplati64_imm_eq_1 : PatLeaf<(bitconvert (v4i32 (build_vector))), [{ 202 APInt Imm; 203 SDNode *BV = N->getOperand(0).getNode(); 204 EVT EltTy = N->getValueType(0).getVectorElementType(); 205 206 return selectVSplat(BV, Imm, EltTy.getSizeInBits()) && 207 Imm.getBitWidth() == EltTy.getSizeInBits() && Imm == 1; 208}]>; 209 210def vsplati64 : PatFrag<(ops node:$e0), 211 (v2i64 (build_vector node:$e0, node:$e0))>; 212 213def vsplati64_splat_d : PatFrag<(ops node:$e0), 214 (v2i64 (bitconvert 215 (v4i32 (and 216 (v4i32 (build_vector node:$e0, 217 node:$e0, 218 node:$e0, 219 node:$e0)), 220 vsplati64_imm_eq_1))))>; 221 222def vsplatf32 : PatFrag<(ops node:$e0), 223 (v4f32 (build_vector node:$e0, node:$e0, 224 node:$e0, node:$e0))>; 225def vsplatf64 : PatFrag<(ops node:$e0), 226 (v2f64 (build_vector node:$e0, node:$e0))>; 227 228def vsplati8_elt : PatFrag<(ops node:$v, node:$i), 229 (MipsVSHF (vsplati8 node:$i), node:$v, node:$v)>; 230def vsplati16_elt : PatFrag<(ops node:$v, node:$i), 231 (MipsVSHF (vsplati16 node:$i), node:$v, node:$v)>; 232def vsplati32_elt : PatFrag<(ops node:$v, node:$i), 233 (MipsVSHF (vsplati32 node:$i), node:$v, node:$v)>; 234def vsplati64_elt : PatFrag<(ops node:$v, node:$i), 235 (MipsVSHF (vsplati64_splat_d node:$i), 236 node:$v, node:$v)>; 237 238class SplatPatLeaf<Operand opclass, dag frag, code pred = [{}], 239 SDNodeXForm xform = NOOP_SDNodeXForm> 240 : PatLeaf<frag, pred, xform> { 241 Operand OpClass = opclass; 242} 243 244class SplatComplexPattern<Operand opclass, ValueType ty, int numops, string fn, 245 list<SDNode> roots = [], 246 list<SDNodeProperty> props = []> : 247 ComplexPattern<ty, numops, fn, roots, props> { 248 Operand OpClass = opclass; 249} 250 251def vsplati8_uimm3 : SplatComplexPattern<vsplat_uimm3, v16i8, 1, 252 "selectVSplatUimm3", 253 [build_vector, bitconvert]>; 254 255def vsplati8_uimm4 : SplatComplexPattern<vsplat_uimm4, v16i8, 1, 256 "selectVSplatUimm4", 257 [build_vector, bitconvert]>; 258 259def vsplati8_uimm5 : SplatComplexPattern<vsplat_uimm5, v16i8, 1, 260 "selectVSplatUimm5", 261 [build_vector, bitconvert]>; 262 263def vsplati8_uimm8 : SplatComplexPattern<vsplat_uimm8, v16i8, 1, 264 "selectVSplatUimm8", 265 [build_vector, bitconvert]>; 266 267def vsplati8_simm5 : SplatComplexPattern<vsplat_simm5, v16i8, 1, 268 "selectVSplatSimm5", 269 [build_vector, bitconvert]>; 270 271def vsplati16_uimm3 : SplatComplexPattern<vsplat_uimm3, v8i16, 1, 272 "selectVSplatUimm3", 273 [build_vector, bitconvert]>; 274 275def vsplati16_uimm4 : SplatComplexPattern<vsplat_uimm4, v8i16, 1, 276 "selectVSplatUimm4", 277 [build_vector, bitconvert]>; 278 279def vsplati16_uimm5 : SplatComplexPattern<vsplat_uimm5, v8i16, 1, 280 "selectVSplatUimm5", 281 [build_vector, bitconvert]>; 282 283def vsplati16_simm5 : SplatComplexPattern<vsplat_simm5, v8i16, 1, 284 "selectVSplatSimm5", 285 [build_vector, bitconvert]>; 286 287def vsplati32_uimm2 : SplatComplexPattern<vsplat_uimm2, v4i32, 1, 288 "selectVSplatUimm2", 289 [build_vector, bitconvert]>; 290 291def vsplati32_uimm5 : SplatComplexPattern<vsplat_uimm5, v4i32, 1, 292 "selectVSplatUimm5", 293 [build_vector, bitconvert]>; 294 295def vsplati32_simm5 : SplatComplexPattern<vsplat_simm5, v4i32, 1, 296 "selectVSplatSimm5", 297 [build_vector, bitconvert]>; 298 299def vsplati64_uimm1 : SplatComplexPattern<vsplat_uimm1, v2i64, 1, 300 "selectVSplatUimm1", 301 [build_vector, bitconvert]>; 302 303def vsplati64_uimm5 : SplatComplexPattern<vsplat_uimm5, v2i64, 1, 304 "selectVSplatUimm5", 305 [build_vector, bitconvert]>; 306 307def vsplati64_uimm6 : SplatComplexPattern<vsplat_uimm6, v2i64, 1, 308 "selectVSplatUimm6", 309 [build_vector, bitconvert]>; 310 311def vsplati64_simm5 : SplatComplexPattern<vsplat_simm5, v2i64, 1, 312 "selectVSplatSimm5", 313 [build_vector, bitconvert]>; 314 315// Any build_vector that is a constant splat with a value that is an exact 316// power of 2 317def vsplat_uimm_pow2 : ComplexPattern<vAny, 1, "selectVSplatUimmPow2", 318 [build_vector, bitconvert]>; 319 320// Any build_vector that is a constant splat with a value that is the bitwise 321// inverse of an exact power of 2 322def vsplat_uimm_inv_pow2 : ComplexPattern<vAny, 1, "selectVSplatUimmInvPow2", 323 [build_vector, bitconvert]>; 324 325// Any build_vector that is a constant splat with only a consecutive sequence 326// of left-most bits set. 327def vsplat_maskl_bits_uimm3 328 : SplatComplexPattern<vsplat_uimm3, vAny, 1, "selectVSplatMaskL", 329 [build_vector, bitconvert]>; 330def vsplat_maskl_bits_uimm4 331 : SplatComplexPattern<vsplat_uimm4, vAny, 1, "selectVSplatMaskL", 332 [build_vector, bitconvert]>; 333def vsplat_maskl_bits_uimm5 334 : SplatComplexPattern<vsplat_uimm5, vAny, 1, "selectVSplatMaskL", 335 [build_vector, bitconvert]>; 336def vsplat_maskl_bits_uimm6 337 : SplatComplexPattern<vsplat_uimm6, vAny, 1, "selectVSplatMaskL", 338 [build_vector, bitconvert]>; 339 340// Any build_vector that is a constant splat with only a consecutive sequence 341// of right-most bits set. 342def vsplat_maskr_bits_uimm3 343 : SplatComplexPattern<vsplat_uimm3, vAny, 1, "selectVSplatMaskR", 344 [build_vector, bitconvert]>; 345def vsplat_maskr_bits_uimm4 346 : SplatComplexPattern<vsplat_uimm4, vAny, 1, "selectVSplatMaskR", 347 [build_vector, bitconvert]>; 348def vsplat_maskr_bits_uimm5 349 : SplatComplexPattern<vsplat_uimm5, vAny, 1, "selectVSplatMaskR", 350 [build_vector, bitconvert]>; 351def vsplat_maskr_bits_uimm6 352 : SplatComplexPattern<vsplat_uimm6, vAny, 1, "selectVSplatMaskR", 353 [build_vector, bitconvert]>; 354 355// Any build_vector that is a constant splat with a value that equals 1 356// FIXME: These should be a ComplexPattern but we can't use them because the 357// ISel generator requires the uses to have a name, but providing a name 358// causes other errors ("used in pattern but not operand list") 359def vsplat_imm_eq_1 : PatLeaf<(build_vector), [{ 360 APInt Imm; 361 EVT EltTy = N->getValueType(0).getVectorElementType(); 362 363 return selectVSplat(N, Imm, EltTy.getSizeInBits()) && 364 Imm.getBitWidth() == EltTy.getSizeInBits() && Imm == 1; 365}]>; 366 367def vbclr_b : PatFrag<(ops node:$ws, node:$wt), 368 (and node:$ws, (xor (shl vsplat_imm_eq_1, node:$wt), 369 immAllOnesV))>; 370def vbclr_h : PatFrag<(ops node:$ws, node:$wt), 371 (and node:$ws, (xor (shl vsplat_imm_eq_1, node:$wt), 372 immAllOnesV))>; 373def vbclr_w : PatFrag<(ops node:$ws, node:$wt), 374 (and node:$ws, (xor (shl vsplat_imm_eq_1, node:$wt), 375 immAllOnesV))>; 376def vbclr_d : PatFrag<(ops node:$ws, node:$wt), 377 (and node:$ws, (xor (shl (v2i64 vsplati64_imm_eq_1), 378 node:$wt), 379 (bitconvert (v4i32 immAllOnesV))))>; 380 381def vbneg_b : PatFrag<(ops node:$ws, node:$wt), 382 (xor node:$ws, (shl vsplat_imm_eq_1, node:$wt))>; 383def vbneg_h : PatFrag<(ops node:$ws, node:$wt), 384 (xor node:$ws, (shl vsplat_imm_eq_1, node:$wt))>; 385def vbneg_w : PatFrag<(ops node:$ws, node:$wt), 386 (xor node:$ws, (shl vsplat_imm_eq_1, node:$wt))>; 387def vbneg_d : PatFrag<(ops node:$ws, node:$wt), 388 (xor node:$ws, (shl (v2i64 vsplati64_imm_eq_1), 389 node:$wt))>; 390 391def vbset_b : PatFrag<(ops node:$ws, node:$wt), 392 (or node:$ws, (shl vsplat_imm_eq_1, node:$wt))>; 393def vbset_h : PatFrag<(ops node:$ws, node:$wt), 394 (or node:$ws, (shl vsplat_imm_eq_1, node:$wt))>; 395def vbset_w : PatFrag<(ops node:$ws, node:$wt), 396 (or node:$ws, (shl vsplat_imm_eq_1, node:$wt))>; 397def vbset_d : PatFrag<(ops node:$ws, node:$wt), 398 (or node:$ws, (shl (v2i64 vsplati64_imm_eq_1), 399 node:$wt))>; 400 401def muladd : PatFrag<(ops node:$wd, node:$ws, node:$wt), 402 (add node:$wd, (mul node:$ws, node:$wt))>; 403 404def mulsub : PatFrag<(ops node:$wd, node:$ws, node:$wt), 405 (sub node:$wd, (mul node:$ws, node:$wt))>; 406 407def mul_fexp2 : PatFrag<(ops node:$ws, node:$wt), 408 (fmul node:$ws, (fexp2 node:$wt))>; 409 410// Instruction encoding. 411class ADD_A_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010000>; 412class ADD_A_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010000>; 413class ADD_A_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010000>; 414class ADD_A_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010000>; 415 416class ADDS_A_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010000>; 417class ADDS_A_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010000>; 418class ADDS_A_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010000>; 419class ADDS_A_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010000>; 420 421class ADDS_S_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010000>; 422class ADDS_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010000>; 423class ADDS_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010000>; 424class ADDS_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010000>; 425 426class ADDS_U_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b010000>; 427class ADDS_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010000>; 428class ADDS_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010000>; 429class ADDS_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010000>; 430 431class ADDV_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b001110>; 432class ADDV_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b001110>; 433class ADDV_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b001110>; 434class ADDV_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b001110>; 435 436class ADDVI_B_ENC : MSA_I5_FMT<0b000, 0b00, 0b000110>; 437class ADDVI_H_ENC : MSA_I5_FMT<0b000, 0b01, 0b000110>; 438class ADDVI_W_ENC : MSA_I5_FMT<0b000, 0b10, 0b000110>; 439class ADDVI_D_ENC : MSA_I5_FMT<0b000, 0b11, 0b000110>; 440 441class AND_V_ENC : MSA_VEC_FMT<0b00000, 0b011110>; 442 443class ANDI_B_ENC : MSA_I8_FMT<0b00, 0b000000>; 444 445class ASUB_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010001>; 446class ASUB_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010001>; 447class ASUB_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010001>; 448class ASUB_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010001>; 449 450class ASUB_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010001>; 451class ASUB_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010001>; 452class ASUB_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010001>; 453class ASUB_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010001>; 454 455class AVE_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010000>; 456class AVE_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010000>; 457class AVE_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010000>; 458class AVE_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010000>; 459 460class AVE_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010000>; 461class AVE_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010000>; 462class AVE_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010000>; 463class AVE_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010000>; 464 465class AVER_S_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b010000>; 466class AVER_S_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010000>; 467class AVER_S_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010000>; 468class AVER_S_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010000>; 469 470class AVER_U_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b010000>; 471class AVER_U_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010000>; 472class AVER_U_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010000>; 473class AVER_U_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010000>; 474 475class BCLR_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b001101>; 476class BCLR_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b001101>; 477class BCLR_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b001101>; 478class BCLR_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b001101>; 479 480class BCLRI_B_ENC : MSA_BIT_B_FMT<0b011, 0b001001>; 481class BCLRI_H_ENC : MSA_BIT_H_FMT<0b011, 0b001001>; 482class BCLRI_W_ENC : MSA_BIT_W_FMT<0b011, 0b001001>; 483class BCLRI_D_ENC : MSA_BIT_D_FMT<0b011, 0b001001>; 484 485class BINSL_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b001101>; 486class BINSL_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b001101>; 487class BINSL_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b001101>; 488class BINSL_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b001101>; 489 490class BINSLI_B_ENC : MSA_BIT_B_FMT<0b110, 0b001001>; 491class BINSLI_H_ENC : MSA_BIT_H_FMT<0b110, 0b001001>; 492class BINSLI_W_ENC : MSA_BIT_W_FMT<0b110, 0b001001>; 493class BINSLI_D_ENC : MSA_BIT_D_FMT<0b110, 0b001001>; 494 495class BINSR_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b001101>; 496class BINSR_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b001101>; 497class BINSR_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b001101>; 498class BINSR_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b001101>; 499 500class BINSRI_B_ENC : MSA_BIT_B_FMT<0b111, 0b001001>; 501class BINSRI_H_ENC : MSA_BIT_H_FMT<0b111, 0b001001>; 502class BINSRI_W_ENC : MSA_BIT_W_FMT<0b111, 0b001001>; 503class BINSRI_D_ENC : MSA_BIT_D_FMT<0b111, 0b001001>; 504 505class BMNZ_V_ENC : MSA_VEC_FMT<0b00100, 0b011110>; 506 507class BMNZI_B_ENC : MSA_I8_FMT<0b00, 0b000001>; 508 509class BMZ_V_ENC : MSA_VEC_FMT<0b00101, 0b011110>; 510 511class BMZI_B_ENC : MSA_I8_FMT<0b01, 0b000001>; 512 513class BNEG_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b001101>; 514class BNEG_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b001101>; 515class BNEG_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b001101>; 516class BNEG_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b001101>; 517 518class BNEGI_B_ENC : MSA_BIT_B_FMT<0b101, 0b001001>; 519class BNEGI_H_ENC : MSA_BIT_H_FMT<0b101, 0b001001>; 520class BNEGI_W_ENC : MSA_BIT_W_FMT<0b101, 0b001001>; 521class BNEGI_D_ENC : MSA_BIT_D_FMT<0b101, 0b001001>; 522 523class BNZ_B_ENC : MSA_CBRANCH_FMT<0b111, 0b00>; 524class BNZ_H_ENC : MSA_CBRANCH_FMT<0b111, 0b01>; 525class BNZ_W_ENC : MSA_CBRANCH_FMT<0b111, 0b10>; 526class BNZ_D_ENC : MSA_CBRANCH_FMT<0b111, 0b11>; 527 528class BNZ_V_ENC : MSA_CBRANCH_V_FMT<0b01111>; 529 530class BSEL_V_ENC : MSA_VEC_FMT<0b00110, 0b011110>; 531 532class BSELI_B_ENC : MSA_I8_FMT<0b10, 0b000001>; 533 534class BSET_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b001101>; 535class BSET_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b001101>; 536class BSET_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b001101>; 537class BSET_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b001101>; 538 539class BSETI_B_ENC : MSA_BIT_B_FMT<0b100, 0b001001>; 540class BSETI_H_ENC : MSA_BIT_H_FMT<0b100, 0b001001>; 541class BSETI_W_ENC : MSA_BIT_W_FMT<0b100, 0b001001>; 542class BSETI_D_ENC : MSA_BIT_D_FMT<0b100, 0b001001>; 543 544class BZ_B_ENC : MSA_CBRANCH_FMT<0b110, 0b00>; 545class BZ_H_ENC : MSA_CBRANCH_FMT<0b110, 0b01>; 546class BZ_W_ENC : MSA_CBRANCH_FMT<0b110, 0b10>; 547class BZ_D_ENC : MSA_CBRANCH_FMT<0b110, 0b11>; 548 549class BZ_V_ENC : MSA_CBRANCH_V_FMT<0b01011>; 550 551class CEQ_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b001111>; 552class CEQ_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b001111>; 553class CEQ_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b001111>; 554class CEQ_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b001111>; 555 556class CEQI_B_ENC : MSA_I5_FMT<0b000, 0b00, 0b000111>; 557class CEQI_H_ENC : MSA_I5_FMT<0b000, 0b01, 0b000111>; 558class CEQI_W_ENC : MSA_I5_FMT<0b000, 0b10, 0b000111>; 559class CEQI_D_ENC : MSA_I5_FMT<0b000, 0b11, 0b000111>; 560 561class CFCMSA_ENC : MSA_ELM_CFCMSA_FMT<0b0001111110, 0b011001>; 562 563class CLE_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b001111>; 564class CLE_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b001111>; 565class CLE_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b001111>; 566class CLE_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b001111>; 567 568class CLE_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b001111>; 569class CLE_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b001111>; 570class CLE_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b001111>; 571class CLE_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b001111>; 572 573class CLEI_S_B_ENC : MSA_I5_FMT<0b100, 0b00, 0b000111>; 574class CLEI_S_H_ENC : MSA_I5_FMT<0b100, 0b01, 0b000111>; 575class CLEI_S_W_ENC : MSA_I5_FMT<0b100, 0b10, 0b000111>; 576class CLEI_S_D_ENC : MSA_I5_FMT<0b100, 0b11, 0b000111>; 577 578class CLEI_U_B_ENC : MSA_I5_FMT<0b101, 0b00, 0b000111>; 579class CLEI_U_H_ENC : MSA_I5_FMT<0b101, 0b01, 0b000111>; 580class CLEI_U_W_ENC : MSA_I5_FMT<0b101, 0b10, 0b000111>; 581class CLEI_U_D_ENC : MSA_I5_FMT<0b101, 0b11, 0b000111>; 582 583class CLT_S_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b001111>; 584class CLT_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b001111>; 585class CLT_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b001111>; 586class CLT_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b001111>; 587 588class CLT_U_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b001111>; 589class CLT_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b001111>; 590class CLT_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b001111>; 591class CLT_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b001111>; 592 593class CLTI_S_B_ENC : MSA_I5_FMT<0b010, 0b00, 0b000111>; 594class CLTI_S_H_ENC : MSA_I5_FMT<0b010, 0b01, 0b000111>; 595class CLTI_S_W_ENC : MSA_I5_FMT<0b010, 0b10, 0b000111>; 596class CLTI_S_D_ENC : MSA_I5_FMT<0b010, 0b11, 0b000111>; 597 598class CLTI_U_B_ENC : MSA_I5_FMT<0b011, 0b00, 0b000111>; 599class CLTI_U_H_ENC : MSA_I5_FMT<0b011, 0b01, 0b000111>; 600class CLTI_U_W_ENC : MSA_I5_FMT<0b011, 0b10, 0b000111>; 601class CLTI_U_D_ENC : MSA_I5_FMT<0b011, 0b11, 0b000111>; 602 603class COPY_S_B_ENC : MSA_ELM_COPY_B_FMT<0b0010, 0b011001>; 604class COPY_S_H_ENC : MSA_ELM_COPY_H_FMT<0b0010, 0b011001>; 605class COPY_S_W_ENC : MSA_ELM_COPY_W_FMT<0b0010, 0b011001>; 606class COPY_S_D_ENC : MSA_ELM_COPY_D_FMT<0b0010, 0b011001>; 607 608class COPY_U_B_ENC : MSA_ELM_COPY_B_FMT<0b0011, 0b011001>; 609class COPY_U_H_ENC : MSA_ELM_COPY_H_FMT<0b0011, 0b011001>; 610class COPY_U_W_ENC : MSA_ELM_COPY_W_FMT<0b0011, 0b011001>; 611 612class CTCMSA_ENC : MSA_ELM_CTCMSA_FMT<0b0000111110, 0b011001>; 613 614class DIV_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010010>; 615class DIV_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010010>; 616class DIV_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010010>; 617class DIV_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010010>; 618 619class DIV_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010010>; 620class DIV_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010010>; 621class DIV_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010010>; 622class DIV_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010010>; 623 624class DOTP_S_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010011>; 625class DOTP_S_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010011>; 626class DOTP_S_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010011>; 627 628class DOTP_U_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010011>; 629class DOTP_U_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010011>; 630class DOTP_U_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010011>; 631 632class DPADD_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010011>; 633class DPADD_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010011>; 634class DPADD_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010011>; 635 636class DPADD_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010011>; 637class DPADD_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010011>; 638class DPADD_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010011>; 639 640class DPSUB_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010011>; 641class DPSUB_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010011>; 642class DPSUB_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010011>; 643 644class DPSUB_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010011>; 645class DPSUB_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010011>; 646class DPSUB_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010011>; 647 648class FADD_W_ENC : MSA_3RF_FMT<0b0000, 0b0, 0b011011>; 649class FADD_D_ENC : MSA_3RF_FMT<0b0000, 0b1, 0b011011>; 650 651class FCAF_W_ENC : MSA_3RF_FMT<0b0000, 0b0, 0b011010>; 652class FCAF_D_ENC : MSA_3RF_FMT<0b0000, 0b1, 0b011010>; 653 654class FCEQ_W_ENC : MSA_3RF_FMT<0b0010, 0b0, 0b011010>; 655class FCEQ_D_ENC : MSA_3RF_FMT<0b0010, 0b1, 0b011010>; 656 657class FCLASS_W_ENC : MSA_2RF_FMT<0b110010000, 0b0, 0b011110>; 658class FCLASS_D_ENC : MSA_2RF_FMT<0b110010000, 0b1, 0b011110>; 659 660class FCLE_W_ENC : MSA_3RF_FMT<0b0110, 0b0, 0b011010>; 661class FCLE_D_ENC : MSA_3RF_FMT<0b0110, 0b1, 0b011010>; 662 663class FCLT_W_ENC : MSA_3RF_FMT<0b0100, 0b0, 0b011010>; 664class FCLT_D_ENC : MSA_3RF_FMT<0b0100, 0b1, 0b011010>; 665 666class FCNE_W_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011100>; 667class FCNE_D_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011100>; 668 669class FCOR_W_ENC : MSA_3RF_FMT<0b0001, 0b0, 0b011100>; 670class FCOR_D_ENC : MSA_3RF_FMT<0b0001, 0b1, 0b011100>; 671 672class FCUEQ_W_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011010>; 673class FCUEQ_D_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011010>; 674 675class FCULE_W_ENC : MSA_3RF_FMT<0b0111, 0b0, 0b011010>; 676class FCULE_D_ENC : MSA_3RF_FMT<0b0111, 0b1, 0b011010>; 677 678class FCULT_W_ENC : MSA_3RF_FMT<0b0101, 0b0, 0b011010>; 679class FCULT_D_ENC : MSA_3RF_FMT<0b0101, 0b1, 0b011010>; 680 681class FCUN_W_ENC : MSA_3RF_FMT<0b0001, 0b0, 0b011010>; 682class FCUN_D_ENC : MSA_3RF_FMT<0b0001, 0b1, 0b011010>; 683 684class FCUNE_W_ENC : MSA_3RF_FMT<0b0010, 0b0, 0b011100>; 685class FCUNE_D_ENC : MSA_3RF_FMT<0b0010, 0b1, 0b011100>; 686 687class FDIV_W_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011011>; 688class FDIV_D_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011011>; 689 690class FEXDO_H_ENC : MSA_3RF_FMT<0b1000, 0b0, 0b011011>; 691class FEXDO_W_ENC : MSA_3RF_FMT<0b1000, 0b1, 0b011011>; 692 693class FEXP2_W_ENC : MSA_3RF_FMT<0b0111, 0b0, 0b011011>; 694class FEXP2_D_ENC : MSA_3RF_FMT<0b0111, 0b1, 0b011011>; 695 696class FEXUPL_W_ENC : MSA_2RF_FMT<0b110011000, 0b0, 0b011110>; 697class FEXUPL_D_ENC : MSA_2RF_FMT<0b110011000, 0b1, 0b011110>; 698 699class FEXUPR_W_ENC : MSA_2RF_FMT<0b110011001, 0b0, 0b011110>; 700class FEXUPR_D_ENC : MSA_2RF_FMT<0b110011001, 0b1, 0b011110>; 701 702class FFINT_S_W_ENC : MSA_2RF_FMT<0b110011110, 0b0, 0b011110>; 703class FFINT_S_D_ENC : MSA_2RF_FMT<0b110011110, 0b1, 0b011110>; 704 705class FFINT_U_W_ENC : MSA_2RF_FMT<0b110011111, 0b0, 0b011110>; 706class FFINT_U_D_ENC : MSA_2RF_FMT<0b110011111, 0b1, 0b011110>; 707 708class FFQL_W_ENC : MSA_2RF_FMT<0b110011010, 0b0, 0b011110>; 709class FFQL_D_ENC : MSA_2RF_FMT<0b110011010, 0b1, 0b011110>; 710 711class FFQR_W_ENC : MSA_2RF_FMT<0b110011011, 0b0, 0b011110>; 712class FFQR_D_ENC : MSA_2RF_FMT<0b110011011, 0b1, 0b011110>; 713 714class FILL_B_ENC : MSA_2R_FILL_FMT<0b11000000, 0b00, 0b011110>; 715class FILL_H_ENC : MSA_2R_FILL_FMT<0b11000000, 0b01, 0b011110>; 716class FILL_W_ENC : MSA_2R_FILL_FMT<0b11000000, 0b10, 0b011110>; 717class FILL_D_ENC : MSA_2R_FILL_D_FMT<0b11000000, 0b11, 0b011110>; 718 719class FLOG2_W_ENC : MSA_2RF_FMT<0b110010111, 0b0, 0b011110>; 720class FLOG2_D_ENC : MSA_2RF_FMT<0b110010111, 0b1, 0b011110>; 721 722class FMADD_W_ENC : MSA_3RF_FMT<0b0100, 0b0, 0b011011>; 723class FMADD_D_ENC : MSA_3RF_FMT<0b0100, 0b1, 0b011011>; 724 725class FMAX_W_ENC : MSA_3RF_FMT<0b1110, 0b0, 0b011011>; 726class FMAX_D_ENC : MSA_3RF_FMT<0b1110, 0b1, 0b011011>; 727 728class FMAX_A_W_ENC : MSA_3RF_FMT<0b1111, 0b0, 0b011011>; 729class FMAX_A_D_ENC : MSA_3RF_FMT<0b1111, 0b1, 0b011011>; 730 731class FMIN_W_ENC : MSA_3RF_FMT<0b1100, 0b0, 0b011011>; 732class FMIN_D_ENC : MSA_3RF_FMT<0b1100, 0b1, 0b011011>; 733 734class FMIN_A_W_ENC : MSA_3RF_FMT<0b1101, 0b0, 0b011011>; 735class FMIN_A_D_ENC : MSA_3RF_FMT<0b1101, 0b1, 0b011011>; 736 737class FMSUB_W_ENC : MSA_3RF_FMT<0b0101, 0b0, 0b011011>; 738class FMSUB_D_ENC : MSA_3RF_FMT<0b0101, 0b1, 0b011011>; 739 740class FMUL_W_ENC : MSA_3RF_FMT<0b0010, 0b0, 0b011011>; 741class FMUL_D_ENC : MSA_3RF_FMT<0b0010, 0b1, 0b011011>; 742 743class FRINT_W_ENC : MSA_2RF_FMT<0b110010110, 0b0, 0b011110>; 744class FRINT_D_ENC : MSA_2RF_FMT<0b110010110, 0b1, 0b011110>; 745 746class FRCP_W_ENC : MSA_2RF_FMT<0b110010101, 0b0, 0b011110>; 747class FRCP_D_ENC : MSA_2RF_FMT<0b110010101, 0b1, 0b011110>; 748 749class FRSQRT_W_ENC : MSA_2RF_FMT<0b110010100, 0b0, 0b011110>; 750class FRSQRT_D_ENC : MSA_2RF_FMT<0b110010100, 0b1, 0b011110>; 751 752class FSAF_W_ENC : MSA_3RF_FMT<0b1000, 0b0, 0b011010>; 753class FSAF_D_ENC : MSA_3RF_FMT<0b1000, 0b1, 0b011010>; 754 755class FSEQ_W_ENC : MSA_3RF_FMT<0b1010, 0b0, 0b011010>; 756class FSEQ_D_ENC : MSA_3RF_FMT<0b1010, 0b1, 0b011010>; 757 758class FSLE_W_ENC : MSA_3RF_FMT<0b1110, 0b0, 0b011010>; 759class FSLE_D_ENC : MSA_3RF_FMT<0b1110, 0b1, 0b011010>; 760 761class FSLT_W_ENC : MSA_3RF_FMT<0b1100, 0b0, 0b011010>; 762class FSLT_D_ENC : MSA_3RF_FMT<0b1100, 0b1, 0b011010>; 763 764class FSNE_W_ENC : MSA_3RF_FMT<0b1011, 0b0, 0b011100>; 765class FSNE_D_ENC : MSA_3RF_FMT<0b1011, 0b1, 0b011100>; 766 767class FSOR_W_ENC : MSA_3RF_FMT<0b1001, 0b0, 0b011100>; 768class FSOR_D_ENC : MSA_3RF_FMT<0b1001, 0b1, 0b011100>; 769 770class FSQRT_W_ENC : MSA_2RF_FMT<0b110010011, 0b0, 0b011110>; 771class FSQRT_D_ENC : MSA_2RF_FMT<0b110010011, 0b1, 0b011110>; 772 773class FSUB_W_ENC : MSA_3RF_FMT<0b0001, 0b0, 0b011011>; 774class FSUB_D_ENC : MSA_3RF_FMT<0b0001, 0b1, 0b011011>; 775 776class FSUEQ_W_ENC : MSA_3RF_FMT<0b1011, 0b0, 0b011010>; 777class FSUEQ_D_ENC : MSA_3RF_FMT<0b1011, 0b1, 0b011010>; 778 779class FSULE_W_ENC : MSA_3RF_FMT<0b1111, 0b0, 0b011010>; 780class FSULE_D_ENC : MSA_3RF_FMT<0b1111, 0b1, 0b011010>; 781 782class FSULT_W_ENC : MSA_3RF_FMT<0b1101, 0b0, 0b011010>; 783class FSULT_D_ENC : MSA_3RF_FMT<0b1101, 0b1, 0b011010>; 784 785class FSUN_W_ENC : MSA_3RF_FMT<0b1001, 0b0, 0b011010>; 786class FSUN_D_ENC : MSA_3RF_FMT<0b1001, 0b1, 0b011010>; 787 788class FSUNE_W_ENC : MSA_3RF_FMT<0b1010, 0b0, 0b011100>; 789class FSUNE_D_ENC : MSA_3RF_FMT<0b1010, 0b1, 0b011100>; 790 791class FTINT_S_W_ENC : MSA_2RF_FMT<0b110011100, 0b0, 0b011110>; 792class FTINT_S_D_ENC : MSA_2RF_FMT<0b110011100, 0b1, 0b011110>; 793 794class FTINT_U_W_ENC : MSA_2RF_FMT<0b110011101, 0b0, 0b011110>; 795class FTINT_U_D_ENC : MSA_2RF_FMT<0b110011101, 0b1, 0b011110>; 796 797class FTQ_H_ENC : MSA_3RF_FMT<0b1010, 0b0, 0b011011>; 798class FTQ_W_ENC : MSA_3RF_FMT<0b1010, 0b1, 0b011011>; 799 800class FTRUNC_S_W_ENC : MSA_2RF_FMT<0b110010001, 0b0, 0b011110>; 801class FTRUNC_S_D_ENC : MSA_2RF_FMT<0b110010001, 0b1, 0b011110>; 802 803class FTRUNC_U_W_ENC : MSA_2RF_FMT<0b110010010, 0b0, 0b011110>; 804class FTRUNC_U_D_ENC : MSA_2RF_FMT<0b110010010, 0b1, 0b011110>; 805 806class HADD_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010101>; 807class HADD_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010101>; 808class HADD_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010101>; 809 810class HADD_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010101>; 811class HADD_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010101>; 812class HADD_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010101>; 813 814class HSUB_S_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010101>; 815class HSUB_S_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010101>; 816class HSUB_S_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010101>; 817 818class HSUB_U_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010101>; 819class HSUB_U_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010101>; 820class HSUB_U_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010101>; 821 822class ILVEV_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b010100>; 823class ILVEV_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010100>; 824class ILVEV_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010100>; 825class ILVEV_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010100>; 826 827class ILVL_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010100>; 828class ILVL_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010100>; 829class ILVL_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010100>; 830class ILVL_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010100>; 831 832class ILVOD_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b010100>; 833class ILVOD_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010100>; 834class ILVOD_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010100>; 835class ILVOD_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010100>; 836 837class ILVR_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010100>; 838class ILVR_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010100>; 839class ILVR_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010100>; 840class ILVR_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010100>; 841 842class INSERT_B_ENC : MSA_ELM_INSERT_B_FMT<0b0100, 0b011001>; 843class INSERT_H_ENC : MSA_ELM_INSERT_H_FMT<0b0100, 0b011001>; 844class INSERT_W_ENC : MSA_ELM_INSERT_W_FMT<0b0100, 0b011001>; 845class INSERT_D_ENC : MSA_ELM_INSERT_D_FMT<0b0100, 0b011001>; 846 847class INSVE_B_ENC : MSA_ELM_B_FMT<0b0101, 0b011001>; 848class INSVE_H_ENC : MSA_ELM_H_FMT<0b0101, 0b011001>; 849class INSVE_W_ENC : MSA_ELM_W_FMT<0b0101, 0b011001>; 850class INSVE_D_ENC : MSA_ELM_D_FMT<0b0101, 0b011001>; 851 852class LD_B_ENC : MSA_MI10_FMT<0b00, 0b1000>; 853class LD_H_ENC : MSA_MI10_FMT<0b01, 0b1000>; 854class LD_W_ENC : MSA_MI10_FMT<0b10, 0b1000>; 855class LD_D_ENC : MSA_MI10_FMT<0b11, 0b1000>; 856 857class LDI_B_ENC : MSA_I10_FMT<0b110, 0b00, 0b000111>; 858class LDI_H_ENC : MSA_I10_FMT<0b110, 0b01, 0b000111>; 859class LDI_W_ENC : MSA_I10_FMT<0b110, 0b10, 0b000111>; 860class LDI_D_ENC : MSA_I10_FMT<0b110, 0b11, 0b000111>; 861 862class LSA_ENC : SPECIAL_LSA_FMT<0b000101>; 863class DLSA_ENC : SPECIAL_DLSA_FMT<0b010101>; 864 865class MADD_Q_H_ENC : MSA_3RF_FMT<0b0101, 0b0, 0b011100>; 866class MADD_Q_W_ENC : MSA_3RF_FMT<0b0101, 0b1, 0b011100>; 867 868class MADDR_Q_H_ENC : MSA_3RF_FMT<0b1101, 0b0, 0b011100>; 869class MADDR_Q_W_ENC : MSA_3RF_FMT<0b1101, 0b1, 0b011100>; 870 871class MADDV_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010010>; 872class MADDV_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010010>; 873class MADDV_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010010>; 874class MADDV_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010010>; 875 876class MAX_A_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b001110>; 877class MAX_A_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b001110>; 878class MAX_A_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b001110>; 879class MAX_A_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b001110>; 880 881class MAX_S_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b001110>; 882class MAX_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b001110>; 883class MAX_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b001110>; 884class MAX_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b001110>; 885 886class MAX_U_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b001110>; 887class MAX_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b001110>; 888class MAX_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b001110>; 889class MAX_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b001110>; 890 891class MAXI_S_B_ENC : MSA_I5_FMT<0b010, 0b00, 0b000110>; 892class MAXI_S_H_ENC : MSA_I5_FMT<0b010, 0b01, 0b000110>; 893class MAXI_S_W_ENC : MSA_I5_FMT<0b010, 0b10, 0b000110>; 894class MAXI_S_D_ENC : MSA_I5_FMT<0b010, 0b11, 0b000110>; 895 896class MAXI_U_B_ENC : MSA_I5_FMT<0b011, 0b00, 0b000110>; 897class MAXI_U_H_ENC : MSA_I5_FMT<0b011, 0b01, 0b000110>; 898class MAXI_U_W_ENC : MSA_I5_FMT<0b011, 0b10, 0b000110>; 899class MAXI_U_D_ENC : MSA_I5_FMT<0b011, 0b11, 0b000110>; 900 901class MIN_A_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b001110>; 902class MIN_A_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b001110>; 903class MIN_A_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b001110>; 904class MIN_A_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b001110>; 905 906class MIN_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b001110>; 907class MIN_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b001110>; 908class MIN_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b001110>; 909class MIN_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b001110>; 910 911class MIN_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b001110>; 912class MIN_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b001110>; 913class MIN_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b001110>; 914class MIN_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b001110>; 915 916class MINI_S_B_ENC : MSA_I5_FMT<0b100, 0b00, 0b000110>; 917class MINI_S_H_ENC : MSA_I5_FMT<0b100, 0b01, 0b000110>; 918class MINI_S_W_ENC : MSA_I5_FMT<0b100, 0b10, 0b000110>; 919class MINI_S_D_ENC : MSA_I5_FMT<0b100, 0b11, 0b000110>; 920 921class MINI_U_B_ENC : MSA_I5_FMT<0b101, 0b00, 0b000110>; 922class MINI_U_H_ENC : MSA_I5_FMT<0b101, 0b01, 0b000110>; 923class MINI_U_W_ENC : MSA_I5_FMT<0b101, 0b10, 0b000110>; 924class MINI_U_D_ENC : MSA_I5_FMT<0b101, 0b11, 0b000110>; 925 926class MOD_S_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b010010>; 927class MOD_S_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010010>; 928class MOD_S_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010010>; 929class MOD_S_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010010>; 930 931class MOD_U_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b010010>; 932class MOD_U_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010010>; 933class MOD_U_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010010>; 934class MOD_U_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010010>; 935 936class MOVE_V_ENC : MSA_ELM_FMT<0b0010111110, 0b011001>; 937 938class MSUB_Q_H_ENC : MSA_3RF_FMT<0b0110, 0b0, 0b011100>; 939class MSUB_Q_W_ENC : MSA_3RF_FMT<0b0110, 0b1, 0b011100>; 940 941class MSUBR_Q_H_ENC : MSA_3RF_FMT<0b1110, 0b0, 0b011100>; 942class MSUBR_Q_W_ENC : MSA_3RF_FMT<0b1110, 0b1, 0b011100>; 943 944class MSUBV_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010010>; 945class MSUBV_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010010>; 946class MSUBV_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010010>; 947class MSUBV_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010010>; 948 949class MUL_Q_H_ENC : MSA_3RF_FMT<0b0100, 0b0, 0b011100>; 950class MUL_Q_W_ENC : MSA_3RF_FMT<0b0100, 0b1, 0b011100>; 951 952class MULR_Q_H_ENC : MSA_3RF_FMT<0b1100, 0b0, 0b011100>; 953class MULR_Q_W_ENC : MSA_3RF_FMT<0b1100, 0b1, 0b011100>; 954 955class MULV_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010010>; 956class MULV_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010010>; 957class MULV_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010010>; 958class MULV_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010010>; 959 960class NLOC_B_ENC : MSA_2R_FMT<0b11000010, 0b00, 0b011110>; 961class NLOC_H_ENC : MSA_2R_FMT<0b11000010, 0b01, 0b011110>; 962class NLOC_W_ENC : MSA_2R_FMT<0b11000010, 0b10, 0b011110>; 963class NLOC_D_ENC : MSA_2R_FMT<0b11000010, 0b11, 0b011110>; 964 965class NLZC_B_ENC : MSA_2R_FMT<0b11000011, 0b00, 0b011110>; 966class NLZC_H_ENC : MSA_2R_FMT<0b11000011, 0b01, 0b011110>; 967class NLZC_W_ENC : MSA_2R_FMT<0b11000011, 0b10, 0b011110>; 968class NLZC_D_ENC : MSA_2R_FMT<0b11000011, 0b11, 0b011110>; 969 970class NOR_V_ENC : MSA_VEC_FMT<0b00010, 0b011110>; 971 972class NORI_B_ENC : MSA_I8_FMT<0b10, 0b000000>; 973 974class OR_V_ENC : MSA_VEC_FMT<0b00001, 0b011110>; 975 976class ORI_B_ENC : MSA_I8_FMT<0b01, 0b000000>; 977 978class PCKEV_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010100>; 979class PCKEV_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010100>; 980class PCKEV_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010100>; 981class PCKEV_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010100>; 982 983class PCKOD_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b010100>; 984class PCKOD_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010100>; 985class PCKOD_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010100>; 986class PCKOD_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010100>; 987 988class PCNT_B_ENC : MSA_2R_FMT<0b11000001, 0b00, 0b011110>; 989class PCNT_H_ENC : MSA_2R_FMT<0b11000001, 0b01, 0b011110>; 990class PCNT_W_ENC : MSA_2R_FMT<0b11000001, 0b10, 0b011110>; 991class PCNT_D_ENC : MSA_2R_FMT<0b11000001, 0b11, 0b011110>; 992 993class SAT_S_B_ENC : MSA_BIT_B_FMT<0b000, 0b001010>; 994class SAT_S_H_ENC : MSA_BIT_H_FMT<0b000, 0b001010>; 995class SAT_S_W_ENC : MSA_BIT_W_FMT<0b000, 0b001010>; 996class SAT_S_D_ENC : MSA_BIT_D_FMT<0b000, 0b001010>; 997 998class SAT_U_B_ENC : MSA_BIT_B_FMT<0b001, 0b001010>; 999class SAT_U_H_ENC : MSA_BIT_H_FMT<0b001, 0b001010>; 1000class SAT_U_W_ENC : MSA_BIT_W_FMT<0b001, 0b001010>; 1001class SAT_U_D_ENC : MSA_BIT_D_FMT<0b001, 0b001010>; 1002 1003class SHF_B_ENC : MSA_I8_FMT<0b00, 0b000010>; 1004class SHF_H_ENC : MSA_I8_FMT<0b01, 0b000010>; 1005class SHF_W_ENC : MSA_I8_FMT<0b10, 0b000010>; 1006 1007class SLD_B_ENC : MSA_3R_INDEX_FMT<0b000, 0b00, 0b010100>; 1008class SLD_H_ENC : MSA_3R_INDEX_FMT<0b000, 0b01, 0b010100>; 1009class SLD_W_ENC : MSA_3R_INDEX_FMT<0b000, 0b10, 0b010100>; 1010class SLD_D_ENC : MSA_3R_INDEX_FMT<0b000, 0b11, 0b010100>; 1011 1012class SLDI_B_ENC : MSA_ELM_B_FMT<0b0000, 0b011001>; 1013class SLDI_H_ENC : MSA_ELM_H_FMT<0b0000, 0b011001>; 1014class SLDI_W_ENC : MSA_ELM_W_FMT<0b0000, 0b011001>; 1015class SLDI_D_ENC : MSA_ELM_D_FMT<0b0000, 0b011001>; 1016 1017class SLL_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b001101>; 1018class SLL_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b001101>; 1019class SLL_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b001101>; 1020class SLL_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b001101>; 1021 1022class SLLI_B_ENC : MSA_BIT_B_FMT<0b000, 0b001001>; 1023class SLLI_H_ENC : MSA_BIT_H_FMT<0b000, 0b001001>; 1024class SLLI_W_ENC : MSA_BIT_W_FMT<0b000, 0b001001>; 1025class SLLI_D_ENC : MSA_BIT_D_FMT<0b000, 0b001001>; 1026 1027class SPLAT_B_ENC : MSA_3R_INDEX_FMT<0b001, 0b00, 0b010100>; 1028class SPLAT_H_ENC : MSA_3R_INDEX_FMT<0b001, 0b01, 0b010100>; 1029class SPLAT_W_ENC : MSA_3R_INDEX_FMT<0b001, 0b10, 0b010100>; 1030class SPLAT_D_ENC : MSA_3R_INDEX_FMT<0b001, 0b11, 0b010100>; 1031 1032class SPLATI_B_ENC : MSA_ELM_B_FMT<0b0001, 0b011001>; 1033class SPLATI_H_ENC : MSA_ELM_H_FMT<0b0001, 0b011001>; 1034class SPLATI_W_ENC : MSA_ELM_W_FMT<0b0001, 0b011001>; 1035class SPLATI_D_ENC : MSA_ELM_D_FMT<0b0001, 0b011001>; 1036 1037class SRA_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b001101>; 1038class SRA_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b001101>; 1039class SRA_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b001101>; 1040class SRA_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b001101>; 1041 1042class SRAI_B_ENC : MSA_BIT_B_FMT<0b001, 0b001001>; 1043class SRAI_H_ENC : MSA_BIT_H_FMT<0b001, 0b001001>; 1044class SRAI_W_ENC : MSA_BIT_W_FMT<0b001, 0b001001>; 1045class SRAI_D_ENC : MSA_BIT_D_FMT<0b001, 0b001001>; 1046 1047class SRAR_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010101>; 1048class SRAR_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010101>; 1049class SRAR_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010101>; 1050class SRAR_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010101>; 1051 1052class SRARI_B_ENC : MSA_BIT_B_FMT<0b010, 0b001010>; 1053class SRARI_H_ENC : MSA_BIT_H_FMT<0b010, 0b001010>; 1054class SRARI_W_ENC : MSA_BIT_W_FMT<0b010, 0b001010>; 1055class SRARI_D_ENC : MSA_BIT_D_FMT<0b010, 0b001010>; 1056 1057class SRL_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b001101>; 1058class SRL_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b001101>; 1059class SRL_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b001101>; 1060class SRL_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b001101>; 1061 1062class SRLI_B_ENC : MSA_BIT_B_FMT<0b010, 0b001001>; 1063class SRLI_H_ENC : MSA_BIT_H_FMT<0b010, 0b001001>; 1064class SRLI_W_ENC : MSA_BIT_W_FMT<0b010, 0b001001>; 1065class SRLI_D_ENC : MSA_BIT_D_FMT<0b010, 0b001001>; 1066 1067class SRLR_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010101>; 1068class SRLR_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010101>; 1069class SRLR_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010101>; 1070class SRLR_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010101>; 1071 1072class SRLRI_B_ENC : MSA_BIT_B_FMT<0b011, 0b001010>; 1073class SRLRI_H_ENC : MSA_BIT_H_FMT<0b011, 0b001010>; 1074class SRLRI_W_ENC : MSA_BIT_W_FMT<0b011, 0b001010>; 1075class SRLRI_D_ENC : MSA_BIT_D_FMT<0b011, 0b001010>; 1076 1077class ST_B_ENC : MSA_MI10_FMT<0b00, 0b1001>; 1078class ST_H_ENC : MSA_MI10_FMT<0b01, 0b1001>; 1079class ST_W_ENC : MSA_MI10_FMT<0b10, 0b1001>; 1080class ST_D_ENC : MSA_MI10_FMT<0b11, 0b1001>; 1081 1082class SUBS_S_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010001>; 1083class SUBS_S_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010001>; 1084class SUBS_S_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010001>; 1085class SUBS_S_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010001>; 1086 1087class SUBS_U_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010001>; 1088class SUBS_U_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010001>; 1089class SUBS_U_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010001>; 1090class SUBS_U_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010001>; 1091 1092class SUBSUS_U_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010001>; 1093class SUBSUS_U_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010001>; 1094class SUBSUS_U_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010001>; 1095class SUBSUS_U_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010001>; 1096 1097class SUBSUU_S_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b010001>; 1098class SUBSUU_S_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010001>; 1099class SUBSUU_S_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010001>; 1100class SUBSUU_S_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010001>; 1101 1102class SUBV_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b001110>; 1103class SUBV_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b001110>; 1104class SUBV_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b001110>; 1105class SUBV_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b001110>; 1106 1107class SUBVI_B_ENC : MSA_I5_FMT<0b001, 0b00, 0b000110>; 1108class SUBVI_H_ENC : MSA_I5_FMT<0b001, 0b01, 0b000110>; 1109class SUBVI_W_ENC : MSA_I5_FMT<0b001, 0b10, 0b000110>; 1110class SUBVI_D_ENC : MSA_I5_FMT<0b001, 0b11, 0b000110>; 1111 1112class VSHF_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010101>; 1113class VSHF_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010101>; 1114class VSHF_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010101>; 1115class VSHF_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010101>; 1116 1117class XOR_V_ENC : MSA_VEC_FMT<0b00011, 0b011110>; 1118 1119class XORI_B_ENC : MSA_I8_FMT<0b11, 0b000000>; 1120 1121// Instruction desc. 1122class MSA_BIT_B_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1123 ComplexPattern Imm, RegisterOperand ROWD, 1124 RegisterOperand ROWS = ROWD, 1125 InstrItinClass itin = NoItinerary> { 1126 dag OutOperandList = (outs ROWD:$wd); 1127 dag InOperandList = (ins ROWS:$ws, vsplat_uimm3:$m); 1128 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m"); 1129 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))]; 1130 InstrItinClass Itinerary = itin; 1131} 1132 1133class MSA_BIT_H_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1134 ComplexPattern Imm, RegisterOperand ROWD, 1135 RegisterOperand ROWS = ROWD, 1136 InstrItinClass itin = NoItinerary> { 1137 dag OutOperandList = (outs ROWD:$wd); 1138 dag InOperandList = (ins ROWS:$ws, vsplat_uimm4:$m); 1139 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m"); 1140 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))]; 1141 InstrItinClass Itinerary = itin; 1142} 1143 1144class MSA_BIT_W_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1145 ComplexPattern Imm, RegisterOperand ROWD, 1146 RegisterOperand ROWS = ROWD, 1147 InstrItinClass itin = NoItinerary> { 1148 dag OutOperandList = (outs ROWD:$wd); 1149 dag InOperandList = (ins ROWS:$ws, vsplat_uimm5:$m); 1150 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m"); 1151 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))]; 1152 InstrItinClass Itinerary = itin; 1153} 1154 1155class MSA_BIT_D_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1156 ComplexPattern Imm, RegisterOperand ROWD, 1157 RegisterOperand ROWS = ROWD, 1158 InstrItinClass itin = NoItinerary> { 1159 dag OutOperandList = (outs ROWD:$wd); 1160 dag InOperandList = (ins ROWS:$ws, vsplat_uimm6:$m); 1161 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m"); 1162 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))]; 1163 InstrItinClass Itinerary = itin; 1164} 1165 1166class MSA_BIT_X_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1167 Operand ImmOp, ImmLeaf Imm, RegisterOperand ROWD, 1168 RegisterOperand ROWS = ROWD, 1169 InstrItinClass itin = NoItinerary> { 1170 dag OutOperandList = (outs ROWD:$wd); 1171 dag InOperandList = (ins ROWS:$ws, ImmOp:$m); 1172 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m"); 1173 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))]; 1174 InstrItinClass Itinerary = itin; 1175} 1176 1177class MSA_BIT_BINSXI_DESC_BASE<string instr_asm, ValueType Ty, 1178 SplatComplexPattern Mask, RegisterOperand ROWD, 1179 RegisterOperand ROWS = ROWD, 1180 InstrItinClass itin = NoItinerary> { 1181 dag OutOperandList = (outs ROWD:$wd); 1182 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, Mask.OpClass:$m); 1183 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m"); 1184 // Note that binsxi and vselect treat the condition operand the opposite 1185 // way to each other. 1186 // (vselect cond, if_set, if_clear) 1187 // (BSEL_V cond, if_clear, if_set) 1188 list<dag> Pattern = [(set ROWD:$wd, (vselect (Ty Mask:$m), (Ty ROWD:$ws), 1189 ROWS:$wd_in))]; 1190 InstrItinClass Itinerary = itin; 1191 string Constraints = "$wd = $wd_in"; 1192} 1193 1194class MSA_BIT_BINSLI_DESC_BASE<string instr_asm, ValueType Ty, 1195 SplatComplexPattern ImmOp, RegisterOperand ROWD, 1196 RegisterOperand ROWS = ROWD, 1197 InstrItinClass itin = NoItinerary> : 1198 MSA_BIT_BINSXI_DESC_BASE<instr_asm, Ty, ImmOp, ROWD, ROWS, itin>; 1199 1200class MSA_BIT_BINSRI_DESC_BASE<string instr_asm, ValueType Ty, 1201 SplatComplexPattern ImmOp, RegisterOperand ROWD, 1202 RegisterOperand ROWS = ROWD, 1203 InstrItinClass itin = NoItinerary> : 1204 MSA_BIT_BINSXI_DESC_BASE<instr_asm, Ty, ImmOp, ROWD, ROWS, itin>; 1205 1206class MSA_BIT_SPLAT_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1207 SplatComplexPattern SplatImm, 1208 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1209 InstrItinClass itin = NoItinerary> { 1210 dag OutOperandList = (outs ROWD:$wd); 1211 dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$m); 1212 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m"); 1213 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, SplatImm:$m))]; 1214 InstrItinClass Itinerary = itin; 1215} 1216 1217class MSA_COPY_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1218 ValueType VecTy, Operand ImmOp, ImmLeaf Imm, 1219 RegisterOperand ROD, RegisterOperand ROWS, 1220 InstrItinClass itin = NoItinerary> { 1221 dag OutOperandList = (outs ROD:$rd); 1222 dag InOperandList = (ins ROWS:$ws, ImmOp:$n); 1223 string AsmString = !strconcat(instr_asm, "\t$rd, $ws[$n]"); 1224 list<dag> Pattern = [(set ROD:$rd, (OpNode (VecTy ROWS:$ws), Imm:$n))]; 1225 InstrItinClass Itinerary = itin; 1226} 1227 1228class MSA_ELM_SLD_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1229 RegisterOperand ROWD, RegisterOperand ROWS, 1230 Operand ImmOp, ImmLeaf Imm, 1231 InstrItinClass itin = NoItinerary> { 1232 dag OutOperandList = (outs ROWD:$wd); 1233 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, ImmOp:$n); 1234 string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$n]"); 1235 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROWS:$ws, 1236 Imm:$n))]; 1237 string Constraints = "$wd = $wd_in"; 1238 InstrItinClass Itinerary = itin; 1239} 1240 1241class MSA_COPY_PSEUDO_BASE<SDPatternOperator OpNode, ValueType VecTy, 1242 Operand ImmOp, ImmLeaf Imm, RegisterClass RCD, 1243 RegisterClass RCWS> : 1244 MSAPseudo<(outs RCD:$wd), (ins RCWS:$ws, ImmOp:$n), 1245 [(set RCD:$wd, (OpNode (VecTy RCWS:$ws), Imm:$n))]> { 1246 bit usesCustomInserter = 1; 1247 bit hasNoSchedulingInfo = 1; 1248} 1249 1250class MSA_I5_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1251 SplatComplexPattern SplatImm, RegisterOperand ROWD, 1252 RegisterOperand ROWS = ROWD, 1253 InstrItinClass itin = NoItinerary> { 1254 dag OutOperandList = (outs ROWD:$wd); 1255 dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$imm); 1256 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $imm"); 1257 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, SplatImm:$imm))]; 1258 InstrItinClass Itinerary = itin; 1259} 1260 1261class MSA_I8_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1262 SplatComplexPattern SplatImm, RegisterOperand ROWD, 1263 RegisterOperand ROWS = ROWD, 1264 InstrItinClass itin = NoItinerary> { 1265 dag OutOperandList = (outs ROWD:$wd); 1266 dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$u8); 1267 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $u8"); 1268 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, SplatImm:$u8))]; 1269 InstrItinClass Itinerary = itin; 1270} 1271 1272class MSA_I8_SHF_DESC_BASE<string instr_asm, RegisterOperand ROWD, 1273 RegisterOperand ROWS = ROWD, 1274 InstrItinClass itin = NoItinerary> { 1275 dag OutOperandList = (outs ROWD:$wd); 1276 dag InOperandList = (ins ROWS:$ws, uimm8:$u8); 1277 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $u8"); 1278 list<dag> Pattern = [(set ROWD:$wd, (MipsSHF timmZExt8:$u8, ROWS:$ws))]; 1279 InstrItinClass Itinerary = itin; 1280} 1281 1282class MSA_I10_LDI_DESC_BASE<string instr_asm, RegisterOperand ROWD, 1283 InstrItinClass itin = NoItinerary> { 1284 dag OutOperandList = (outs ROWD:$wd); 1285 dag InOperandList = (ins vsplat_simm10:$s10); 1286 string AsmString = !strconcat(instr_asm, "\t$wd, $s10"); 1287 // LDI is matched using custom matching code in MipsSEISelDAGToDAG.cpp 1288 list<dag> Pattern = []; 1289 bit hasSideEffects = 0; 1290 bit isReMaterializable = 1; 1291 InstrItinClass Itinerary = itin; 1292} 1293 1294class MSA_2R_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1295 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1296 InstrItinClass itin = NoItinerary> { 1297 dag OutOperandList = (outs ROWD:$wd); 1298 dag InOperandList = (ins ROWS:$ws); 1299 string AsmString = !strconcat(instr_asm, "\t$wd, $ws"); 1300 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws))]; 1301 InstrItinClass Itinerary = itin; 1302} 1303 1304class MSA_2R_FILL_DESC_BASE<string instr_asm, ValueType VT, 1305 SDPatternOperator OpNode, RegisterOperand ROWD, 1306 RegisterOperand ROS = ROWD, 1307 InstrItinClass itin = NoItinerary> { 1308 dag OutOperandList = (outs ROWD:$wd); 1309 dag InOperandList = (ins ROS:$rs); 1310 string AsmString = !strconcat(instr_asm, "\t$wd, $rs"); 1311 list<dag> Pattern = [(set ROWD:$wd, (VT (OpNode ROS:$rs)))]; 1312 InstrItinClass Itinerary = itin; 1313} 1314 1315class MSA_2R_FILL_PSEUDO_BASE<ValueType VT, SDPatternOperator OpNode, 1316 RegisterClass RCWD, RegisterClass RCWS = RCWD> : 1317 MSAPseudo<(outs RCWD:$wd), (ins RCWS:$fs), 1318 [(set RCWD:$wd, (OpNode RCWS:$fs))]> { 1319 let usesCustomInserter = 1; 1320} 1321 1322class MSA_2RF_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1323 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1324 InstrItinClass itin = NoItinerary> { 1325 dag OutOperandList = (outs ROWD:$wd); 1326 dag InOperandList = (ins ROWS:$ws); 1327 string AsmString = !strconcat(instr_asm, "\t$wd, $ws"); 1328 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws))]; 1329 InstrItinClass Itinerary = itin; 1330} 1331 1332class MSA_3R_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1333 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1334 RegisterOperand ROWT = ROWD, 1335 InstrItinClass itin = NoItinerary> { 1336 dag OutOperandList = (outs ROWD:$wd); 1337 dag InOperandList = (ins ROWS:$ws, ROWT:$wt); 1338 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt"); 1339 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, ROWT:$wt))]; 1340 InstrItinClass Itinerary = itin; 1341} 1342 1343class MSA_3R_BINSX_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1344 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1345 RegisterOperand ROWT = ROWD, 1346 InstrItinClass itin = NoItinerary> { 1347 dag OutOperandList = (outs ROWD:$wd); 1348 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, ROWT:$wt); 1349 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt"); 1350 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROWS:$ws, 1351 ROWT:$wt))]; 1352 string Constraints = "$wd = $wd_in"; 1353 InstrItinClass Itinerary = itin; 1354} 1355 1356class MSA_3R_SPLAT_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1357 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1358 InstrItinClass itin = NoItinerary> { 1359 dag OutOperandList = (outs ROWD:$wd); 1360 dag InOperandList = (ins ROWS:$ws, GPR32Opnd:$rt); 1361 string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$rt]"); 1362 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, GPR32Opnd:$rt))]; 1363 InstrItinClass Itinerary = itin; 1364} 1365 1366class MSA_3R_VSHF_DESC_BASE<string instr_asm, RegisterOperand ROWD, 1367 RegisterOperand ROWS = ROWD, 1368 RegisterOperand ROWT = ROWD, 1369 InstrItinClass itin = NoItinerary> { 1370 dag OutOperandList = (outs ROWD:$wd); 1371 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, ROWT:$wt); 1372 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt"); 1373 list<dag> Pattern = [(set ROWD:$wd, (MipsVSHF ROWD:$wd_in, ROWS:$ws, 1374 ROWT:$wt))]; 1375 string Constraints = "$wd = $wd_in"; 1376 InstrItinClass Itinerary = itin; 1377} 1378 1379class MSA_3R_SLD_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1380 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1381 InstrItinClass itin = NoItinerary> { 1382 dag OutOperandList = (outs ROWD:$wd); 1383 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, GPR32Opnd:$rt); 1384 string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$rt]"); 1385 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROWS:$ws, 1386 GPR32Opnd:$rt))]; 1387 InstrItinClass Itinerary = itin; 1388 string Constraints = "$wd = $wd_in"; 1389} 1390 1391class MSA_3R_4R_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1392 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1393 RegisterOperand ROWT = ROWD, 1394 InstrItinClass itin = NoItinerary> { 1395 dag OutOperandList = (outs ROWD:$wd); 1396 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, ROWT:$wt); 1397 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt"); 1398 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROWS:$ws, 1399 ROWT:$wt))]; 1400 InstrItinClass Itinerary = itin; 1401 string Constraints = "$wd = $wd_in"; 1402} 1403 1404class MSA_3RF_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1405 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1406 RegisterOperand ROWT = ROWD, 1407 InstrItinClass itin = NoItinerary> : 1408 MSA_3R_DESC_BASE<instr_asm, OpNode, ROWD, ROWS, ROWT, itin>; 1409 1410class MSA_3RF_4RF_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1411 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1412 RegisterOperand ROWT = ROWD, 1413 InstrItinClass itin = NoItinerary> : 1414 MSA_3R_4R_DESC_BASE<instr_asm, OpNode, ROWD, ROWS, ROWT, itin>; 1415 1416class MSA_CBRANCH_DESC_BASE<string instr_asm, RegisterOperand ROWD> { 1417 dag OutOperandList = (outs); 1418 dag InOperandList = (ins ROWD:$wt, brtarget:$offset); 1419 string AsmString = !strconcat(instr_asm, "\t$wt, $offset"); 1420 list<dag> Pattern = []; 1421 InstrItinClass Itinerary = NoItinerary; 1422 bit isBranch = 1; 1423 bit isTerminator = 1; 1424 bit hasDelaySlot = 1; 1425 list<Register> Defs = [AT]; 1426} 1427 1428class MSA_INSERT_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1429 Operand ImmOp, ImmLeaf Imm, RegisterOperand ROWD, 1430 RegisterOperand ROS, 1431 InstrItinClass itin = NoItinerary> { 1432 dag OutOperandList = (outs ROWD:$wd); 1433 dag InOperandList = (ins ROWD:$wd_in, ROS:$rs, ImmOp:$n); 1434 string AsmString = !strconcat(instr_asm, "\t$wd[$n], $rs"); 1435 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROS:$rs, Imm:$n))]; 1436 InstrItinClass Itinerary = itin; 1437 string Constraints = "$wd = $wd_in"; 1438} 1439 1440class MSA_INSERT_PSEUDO_BASE<SDPatternOperator OpNode, ValueType Ty, 1441 Operand ImmOp, ImmLeaf Imm, RegisterOperand ROWD, 1442 RegisterOperand ROFS> : 1443 MSAPseudo<(outs ROWD:$wd), (ins ROWD:$wd_in, ImmOp:$n, ROFS:$fs), 1444 [(set ROWD:$wd, (OpNode (Ty ROWD:$wd_in), ROFS:$fs, Imm:$n))]> { 1445 bit usesCustomInserter = 1; 1446 string Constraints = "$wd = $wd_in"; 1447} 1448 1449class MSA_INSERT_VIDX_PSEUDO_BASE<SDPatternOperator OpNode, ValueType Ty, 1450 RegisterOperand ROWD, RegisterOperand ROFS, 1451 RegisterOperand ROIdx> : 1452 MSAPseudo<(outs ROWD:$wd), (ins ROWD:$wd_in, ROIdx:$n, ROFS:$fs), 1453 [(set ROWD:$wd, (OpNode (Ty ROWD:$wd_in), ROFS:$fs, 1454 ROIdx:$n))]> { 1455 bit usesCustomInserter = 1; 1456 bit hasNoSchedulingInfo = 1; 1457 string Constraints = "$wd = $wd_in"; 1458} 1459 1460class MSA_INSVE_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1461 Operand ImmOp, ImmLeaf Imm, RegisterOperand ROWD, 1462 RegisterOperand ROWS = ROWD, 1463 InstrItinClass itin = NoItinerary> { 1464 dag OutOperandList = (outs ROWD:$wd); 1465 dag InOperandList = (ins ROWD:$wd_in, ImmOp:$n, ROWS:$ws, uimmz:$n2); 1466 string AsmString = !strconcat(instr_asm, "\t$wd[$n], $ws[$n2]"); 1467 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, 1468 Imm:$n, 1469 ROWS:$ws, 1470 immz:$n2))]; 1471 InstrItinClass Itinerary = itin; 1472 string Constraints = "$wd = $wd_in"; 1473} 1474 1475class MSA_VEC_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1476 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1477 RegisterOperand ROWT = ROWD, 1478 InstrItinClass itin = NoItinerary> { 1479 dag OutOperandList = (outs ROWD:$wd); 1480 dag InOperandList = (ins ROWS:$ws, ROWT:$wt); 1481 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt"); 1482 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, ROWT:$wt))]; 1483 InstrItinClass Itinerary = itin; 1484} 1485 1486class MSA_ELM_SPLAT_DESC_BASE<string instr_asm, SplatComplexPattern SplatImm, 1487 RegisterOperand ROWD, 1488 RegisterOperand ROWS = ROWD, 1489 InstrItinClass itin = NoItinerary> { 1490 dag OutOperandList = (outs ROWD:$wd); 1491 dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$n); 1492 string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$n]"); 1493 list<dag> Pattern = [(set ROWD:$wd, (MipsVSHF SplatImm:$n, ROWS:$ws, 1494 ROWS:$ws))]; 1495 InstrItinClass Itinerary = itin; 1496} 1497 1498class MSA_VEC_PSEUDO_BASE<SDPatternOperator OpNode, RegisterOperand ROWD, 1499 RegisterOperand ROWS = ROWD, 1500 RegisterOperand ROWT = ROWD> : 1501 MSAPseudo<(outs ROWD:$wd), (ins ROWS:$ws, ROWT:$wt), 1502 [(set ROWD:$wd, (OpNode ROWS:$ws, ROWT:$wt))]>; 1503 1504class ADD_A_B_DESC : MSA_3R_DESC_BASE<"add_a.b", int_mips_add_a_b, MSA128BOpnd>, 1505 IsCommutable; 1506class ADD_A_H_DESC : MSA_3R_DESC_BASE<"add_a.h", int_mips_add_a_h, MSA128HOpnd>, 1507 IsCommutable; 1508class ADD_A_W_DESC : MSA_3R_DESC_BASE<"add_a.w", int_mips_add_a_w, MSA128WOpnd>, 1509 IsCommutable; 1510class ADD_A_D_DESC : MSA_3R_DESC_BASE<"add_a.d", int_mips_add_a_d, MSA128DOpnd>, 1511 IsCommutable; 1512 1513class ADDS_A_B_DESC : MSA_3R_DESC_BASE<"adds_a.b", int_mips_adds_a_b, 1514 MSA128BOpnd>, IsCommutable; 1515class ADDS_A_H_DESC : MSA_3R_DESC_BASE<"adds_a.h", int_mips_adds_a_h, 1516 MSA128HOpnd>, IsCommutable; 1517class ADDS_A_W_DESC : MSA_3R_DESC_BASE<"adds_a.w", int_mips_adds_a_w, 1518 MSA128WOpnd>, IsCommutable; 1519class ADDS_A_D_DESC : MSA_3R_DESC_BASE<"adds_a.d", int_mips_adds_a_d, 1520 MSA128DOpnd>, IsCommutable; 1521 1522class ADDS_S_B_DESC : MSA_3R_DESC_BASE<"adds_s.b", int_mips_adds_s_b, 1523 MSA128BOpnd>, IsCommutable; 1524class ADDS_S_H_DESC : MSA_3R_DESC_BASE<"adds_s.h", int_mips_adds_s_h, 1525 MSA128HOpnd>, IsCommutable; 1526class ADDS_S_W_DESC : MSA_3R_DESC_BASE<"adds_s.w", int_mips_adds_s_w, 1527 MSA128WOpnd>, IsCommutable; 1528class ADDS_S_D_DESC : MSA_3R_DESC_BASE<"adds_s.d", int_mips_adds_s_d, 1529 MSA128DOpnd>, IsCommutable; 1530 1531class ADDS_U_B_DESC : MSA_3R_DESC_BASE<"adds_u.b", int_mips_adds_u_b, 1532 MSA128BOpnd>, IsCommutable; 1533class ADDS_U_H_DESC : MSA_3R_DESC_BASE<"adds_u.h", int_mips_adds_u_h, 1534 MSA128HOpnd>, IsCommutable; 1535class ADDS_U_W_DESC : MSA_3R_DESC_BASE<"adds_u.w", int_mips_adds_u_w, 1536 MSA128WOpnd>, IsCommutable; 1537class ADDS_U_D_DESC : MSA_3R_DESC_BASE<"adds_u.d", int_mips_adds_u_d, 1538 MSA128DOpnd>, IsCommutable; 1539 1540class ADDV_B_DESC : MSA_3R_DESC_BASE<"addv.b", add, MSA128BOpnd>, IsCommutable; 1541class ADDV_H_DESC : MSA_3R_DESC_BASE<"addv.h", add, MSA128HOpnd>, IsCommutable; 1542class ADDV_W_DESC : MSA_3R_DESC_BASE<"addv.w", add, MSA128WOpnd>, IsCommutable; 1543class ADDV_D_DESC : MSA_3R_DESC_BASE<"addv.d", add, MSA128DOpnd>, IsCommutable; 1544 1545class ADDVI_B_DESC : MSA_I5_DESC_BASE<"addvi.b", add, vsplati8_uimm5, 1546 MSA128BOpnd>; 1547class ADDVI_H_DESC : MSA_I5_DESC_BASE<"addvi.h", add, vsplati16_uimm5, 1548 MSA128HOpnd>; 1549class ADDVI_W_DESC : MSA_I5_DESC_BASE<"addvi.w", add, vsplati32_uimm5, 1550 MSA128WOpnd>; 1551class ADDVI_D_DESC : MSA_I5_DESC_BASE<"addvi.d", add, vsplati64_uimm5, 1552 MSA128DOpnd>; 1553 1554class AND_V_DESC : MSA_VEC_DESC_BASE<"and.v", and, MSA128BOpnd>; 1555class AND_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<and, MSA128HOpnd>; 1556class AND_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<and, MSA128WOpnd>; 1557class AND_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<and, MSA128DOpnd>; 1558 1559class ANDI_B_DESC : MSA_I8_DESC_BASE<"andi.b", and, vsplati8_uimm8, 1560 MSA128BOpnd>; 1561 1562class ASUB_S_B_DESC : MSA_3R_DESC_BASE<"asub_s.b", int_mips_asub_s_b, 1563 MSA128BOpnd>; 1564class ASUB_S_H_DESC : MSA_3R_DESC_BASE<"asub_s.h", int_mips_asub_s_h, 1565 MSA128HOpnd>; 1566class ASUB_S_W_DESC : MSA_3R_DESC_BASE<"asub_s.w", int_mips_asub_s_w, 1567 MSA128WOpnd>; 1568class ASUB_S_D_DESC : MSA_3R_DESC_BASE<"asub_s.d", int_mips_asub_s_d, 1569 MSA128DOpnd>; 1570 1571class ASUB_U_B_DESC : MSA_3R_DESC_BASE<"asub_u.b", int_mips_asub_u_b, 1572 MSA128BOpnd>; 1573class ASUB_U_H_DESC : MSA_3R_DESC_BASE<"asub_u.h", int_mips_asub_u_h, 1574 MSA128HOpnd>; 1575class ASUB_U_W_DESC : MSA_3R_DESC_BASE<"asub_u.w", int_mips_asub_u_w, 1576 MSA128WOpnd>; 1577class ASUB_U_D_DESC : MSA_3R_DESC_BASE<"asub_u.d", int_mips_asub_u_d, 1578 MSA128DOpnd>; 1579 1580class AVE_S_B_DESC : MSA_3R_DESC_BASE<"ave_s.b", int_mips_ave_s_b, MSA128BOpnd>, 1581 IsCommutable; 1582class AVE_S_H_DESC : MSA_3R_DESC_BASE<"ave_s.h", int_mips_ave_s_h, MSA128HOpnd>, 1583 IsCommutable; 1584class AVE_S_W_DESC : MSA_3R_DESC_BASE<"ave_s.w", int_mips_ave_s_w, MSA128WOpnd>, 1585 IsCommutable; 1586class AVE_S_D_DESC : MSA_3R_DESC_BASE<"ave_s.d", int_mips_ave_s_d, MSA128DOpnd>, 1587 IsCommutable; 1588 1589class AVE_U_B_DESC : MSA_3R_DESC_BASE<"ave_u.b", int_mips_ave_u_b, MSA128BOpnd>, 1590 IsCommutable; 1591class AVE_U_H_DESC : MSA_3R_DESC_BASE<"ave_u.h", int_mips_ave_u_h, MSA128HOpnd>, 1592 IsCommutable; 1593class AVE_U_W_DESC : MSA_3R_DESC_BASE<"ave_u.w", int_mips_ave_u_w, MSA128WOpnd>, 1594 IsCommutable; 1595class AVE_U_D_DESC : MSA_3R_DESC_BASE<"ave_u.d", int_mips_ave_u_d, MSA128DOpnd>, 1596 IsCommutable; 1597 1598class AVER_S_B_DESC : MSA_3R_DESC_BASE<"aver_s.b", int_mips_aver_s_b, 1599 MSA128BOpnd>, IsCommutable; 1600class AVER_S_H_DESC : MSA_3R_DESC_BASE<"aver_s.h", int_mips_aver_s_h, 1601 MSA128HOpnd>, IsCommutable; 1602class AVER_S_W_DESC : MSA_3R_DESC_BASE<"aver_s.w", int_mips_aver_s_w, 1603 MSA128WOpnd>, IsCommutable; 1604class AVER_S_D_DESC : MSA_3R_DESC_BASE<"aver_s.d", int_mips_aver_s_d, 1605 MSA128DOpnd>, IsCommutable; 1606 1607class AVER_U_B_DESC : MSA_3R_DESC_BASE<"aver_u.b", int_mips_aver_u_b, 1608 MSA128BOpnd>, IsCommutable; 1609class AVER_U_H_DESC : MSA_3R_DESC_BASE<"aver_u.h", int_mips_aver_u_h, 1610 MSA128HOpnd>, IsCommutable; 1611class AVER_U_W_DESC : MSA_3R_DESC_BASE<"aver_u.w", int_mips_aver_u_w, 1612 MSA128WOpnd>, IsCommutable; 1613class AVER_U_D_DESC : MSA_3R_DESC_BASE<"aver_u.d", int_mips_aver_u_d, 1614 MSA128DOpnd>, IsCommutable; 1615 1616class BCLR_B_DESC : MSA_3R_DESC_BASE<"bclr.b", vbclr_b, MSA128BOpnd>; 1617class BCLR_H_DESC : MSA_3R_DESC_BASE<"bclr.h", vbclr_h, MSA128HOpnd>; 1618class BCLR_W_DESC : MSA_3R_DESC_BASE<"bclr.w", vbclr_w, MSA128WOpnd>; 1619class BCLR_D_DESC : MSA_3R_DESC_BASE<"bclr.d", vbclr_d, MSA128DOpnd>; 1620 1621class BCLRI_B_DESC : MSA_BIT_B_DESC_BASE<"bclri.b", and, vsplat_uimm_inv_pow2, 1622 MSA128BOpnd>; 1623class BCLRI_H_DESC : MSA_BIT_H_DESC_BASE<"bclri.h", and, vsplat_uimm_inv_pow2, 1624 MSA128HOpnd>; 1625class BCLRI_W_DESC : MSA_BIT_W_DESC_BASE<"bclri.w", and, vsplat_uimm_inv_pow2, 1626 MSA128WOpnd>; 1627class BCLRI_D_DESC : MSA_BIT_D_DESC_BASE<"bclri.d", and, vsplat_uimm_inv_pow2, 1628 MSA128DOpnd>; 1629 1630class BINSL_B_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.b", int_mips_binsl_b, 1631 MSA128BOpnd>; 1632class BINSL_H_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.h", int_mips_binsl_h, 1633 MSA128HOpnd>; 1634class BINSL_W_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.w", int_mips_binsl_w, 1635 MSA128WOpnd>; 1636class BINSL_D_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.d", int_mips_binsl_d, 1637 MSA128DOpnd>; 1638 1639class BINSLI_B_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.b", v16i8, vsplat_maskl_bits_uimm3, MSA128BOpnd>; 1640class BINSLI_H_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.h", v8i16, vsplat_maskl_bits_uimm4, MSA128HOpnd>; 1641class BINSLI_W_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.w", v4i32, vsplat_maskl_bits_uimm5, MSA128WOpnd>; 1642class BINSLI_D_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.d", v2i64, vsplat_maskl_bits_uimm6, MSA128DOpnd>; 1643 1644class BINSR_B_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.b", int_mips_binsr_b, 1645 MSA128BOpnd>; 1646class BINSR_H_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.h", int_mips_binsr_h, 1647 MSA128HOpnd>; 1648class BINSR_W_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.w", int_mips_binsr_w, 1649 MSA128WOpnd>; 1650class BINSR_D_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.d", int_mips_binsr_d, 1651 MSA128DOpnd>; 1652 1653class BINSRI_B_DESC 1654 : MSA_BIT_BINSRI_DESC_BASE<"binsri.b", v16i8, vsplat_maskr_bits_uimm3, 1655 MSA128BOpnd>; 1656class BINSRI_H_DESC 1657 : MSA_BIT_BINSRI_DESC_BASE<"binsri.h", v8i16, vsplat_maskr_bits_uimm4, 1658 MSA128HOpnd>; 1659class BINSRI_W_DESC 1660 : MSA_BIT_BINSRI_DESC_BASE<"binsri.w", v4i32, vsplat_maskr_bits_uimm5, 1661 MSA128WOpnd>; 1662class BINSRI_D_DESC 1663 : MSA_BIT_BINSRI_DESC_BASE<"binsri.d", v2i64, vsplat_maskr_bits_uimm6, 1664 MSA128DOpnd>; 1665 1666class BMNZ_V_DESC { 1667 dag OutOperandList = (outs MSA128BOpnd:$wd); 1668 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws, 1669 MSA128BOpnd:$wt); 1670 string AsmString = "bmnz.v\t$wd, $ws, $wt"; 1671 list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect MSA128BOpnd:$wt, 1672 MSA128BOpnd:$ws, 1673 MSA128BOpnd:$wd_in))]; 1674 InstrItinClass Itinerary = NoItinerary; 1675 string Constraints = "$wd = $wd_in"; 1676} 1677 1678class BMNZI_B_DESC { 1679 dag OutOperandList = (outs MSA128BOpnd:$wd); 1680 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws, 1681 vsplat_uimm8:$u8); 1682 string AsmString = "bmnzi.b\t$wd, $ws, $u8"; 1683 list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect vsplati8_uimm8:$u8, 1684 MSA128BOpnd:$ws, 1685 MSA128BOpnd:$wd_in))]; 1686 InstrItinClass Itinerary = NoItinerary; 1687 string Constraints = "$wd = $wd_in"; 1688} 1689 1690class BMZ_V_DESC { 1691 dag OutOperandList = (outs MSA128BOpnd:$wd); 1692 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws, 1693 MSA128BOpnd:$wt); 1694 string AsmString = "bmz.v\t$wd, $ws, $wt"; 1695 list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect MSA128BOpnd:$wt, 1696 MSA128BOpnd:$wd_in, 1697 MSA128BOpnd:$ws))]; 1698 InstrItinClass Itinerary = NoItinerary; 1699 string Constraints = "$wd = $wd_in"; 1700} 1701 1702class BMZI_B_DESC { 1703 dag OutOperandList = (outs MSA128BOpnd:$wd); 1704 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws, 1705 vsplat_uimm8:$u8); 1706 string AsmString = "bmzi.b\t$wd, $ws, $u8"; 1707 list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect vsplati8_uimm8:$u8, 1708 MSA128BOpnd:$wd_in, 1709 MSA128BOpnd:$ws))]; 1710 InstrItinClass Itinerary = NoItinerary; 1711 string Constraints = "$wd = $wd_in"; 1712} 1713 1714class BNEG_B_DESC : MSA_3R_DESC_BASE<"bneg.b", vbneg_b, MSA128BOpnd>; 1715class BNEG_H_DESC : MSA_3R_DESC_BASE<"bneg.h", vbneg_h, MSA128HOpnd>; 1716class BNEG_W_DESC : MSA_3R_DESC_BASE<"bneg.w", vbneg_w, MSA128WOpnd>; 1717class BNEG_D_DESC : MSA_3R_DESC_BASE<"bneg.d", vbneg_d, MSA128DOpnd>; 1718 1719class BNEGI_B_DESC : MSA_BIT_B_DESC_BASE<"bnegi.b", xor, vsplat_uimm_pow2, 1720 MSA128BOpnd>; 1721class BNEGI_H_DESC : MSA_BIT_H_DESC_BASE<"bnegi.h", xor, vsplat_uimm_pow2, 1722 MSA128HOpnd>; 1723class BNEGI_W_DESC : MSA_BIT_W_DESC_BASE<"bnegi.w", xor, vsplat_uimm_pow2, 1724 MSA128WOpnd>; 1725class BNEGI_D_DESC : MSA_BIT_D_DESC_BASE<"bnegi.d", xor, vsplat_uimm_pow2, 1726 MSA128DOpnd>; 1727 1728class BNZ_B_DESC : MSA_CBRANCH_DESC_BASE<"bnz.b", MSA128BOpnd>; 1729class BNZ_H_DESC : MSA_CBRANCH_DESC_BASE<"bnz.h", MSA128HOpnd>; 1730class BNZ_W_DESC : MSA_CBRANCH_DESC_BASE<"bnz.w", MSA128WOpnd>; 1731class BNZ_D_DESC : MSA_CBRANCH_DESC_BASE<"bnz.d", MSA128DOpnd>; 1732 1733class BNZ_V_DESC : MSA_CBRANCH_DESC_BASE<"bnz.v", MSA128BOpnd>; 1734 1735class BSEL_V_DESC { 1736 dag OutOperandList = (outs MSA128BOpnd:$wd); 1737 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws, 1738 MSA128BOpnd:$wt); 1739 string AsmString = "bsel.v\t$wd, $ws, $wt"; 1740 // Note that vselect and BSEL_V treat the condition operand the opposite way 1741 // from each other. 1742 // (vselect cond, if_set, if_clear) 1743 // (BSEL_V cond, if_clear, if_set) 1744 list<dag> Pattern = [(set MSA128BOpnd:$wd, 1745 (vselect MSA128BOpnd:$wd_in, MSA128BOpnd:$wt, 1746 MSA128BOpnd:$ws))]; 1747 InstrItinClass Itinerary = NoItinerary; 1748 string Constraints = "$wd = $wd_in"; 1749} 1750 1751class BSELI_B_DESC { 1752 dag OutOperandList = (outs MSA128BOpnd:$wd); 1753 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws, 1754 vsplat_uimm8:$u8); 1755 string AsmString = "bseli.b\t$wd, $ws, $u8"; 1756 // Note that vselect and BSEL_V treat the condition operand the opposite way 1757 // from each other. 1758 // (vselect cond, if_set, if_clear) 1759 // (BSEL_V cond, if_clear, if_set) 1760 list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect MSA128BOpnd:$wd_in, 1761 vsplati8_uimm8:$u8, 1762 MSA128BOpnd:$ws))]; 1763 InstrItinClass Itinerary = NoItinerary; 1764 string Constraints = "$wd = $wd_in"; 1765} 1766 1767class BSET_B_DESC : MSA_3R_DESC_BASE<"bset.b", vbset_b, MSA128BOpnd>; 1768class BSET_H_DESC : MSA_3R_DESC_BASE<"bset.h", vbset_h, MSA128HOpnd>; 1769class BSET_W_DESC : MSA_3R_DESC_BASE<"bset.w", vbset_w, MSA128WOpnd>; 1770class BSET_D_DESC : MSA_3R_DESC_BASE<"bset.d", vbset_d, MSA128DOpnd>; 1771 1772class BSETI_B_DESC : MSA_BIT_B_DESC_BASE<"bseti.b", or, vsplat_uimm_pow2, 1773 MSA128BOpnd>; 1774class BSETI_H_DESC : MSA_BIT_H_DESC_BASE<"bseti.h", or, vsplat_uimm_pow2, 1775 MSA128HOpnd>; 1776class BSETI_W_DESC : MSA_BIT_W_DESC_BASE<"bseti.w", or, vsplat_uimm_pow2, 1777 MSA128WOpnd>; 1778class BSETI_D_DESC : MSA_BIT_D_DESC_BASE<"bseti.d", or, vsplat_uimm_pow2, 1779 MSA128DOpnd>; 1780 1781class BZ_B_DESC : MSA_CBRANCH_DESC_BASE<"bz.b", MSA128BOpnd>; 1782class BZ_H_DESC : MSA_CBRANCH_DESC_BASE<"bz.h", MSA128HOpnd>; 1783class BZ_W_DESC : MSA_CBRANCH_DESC_BASE<"bz.w", MSA128WOpnd>; 1784class BZ_D_DESC : MSA_CBRANCH_DESC_BASE<"bz.d", MSA128DOpnd>; 1785 1786class BZ_V_DESC : MSA_CBRANCH_DESC_BASE<"bz.v", MSA128BOpnd>; 1787 1788class CEQ_B_DESC : MSA_3R_DESC_BASE<"ceq.b", vseteq_v16i8, MSA128BOpnd>, 1789 IsCommutable; 1790class CEQ_H_DESC : MSA_3R_DESC_BASE<"ceq.h", vseteq_v8i16, MSA128HOpnd>, 1791 IsCommutable; 1792class CEQ_W_DESC : MSA_3R_DESC_BASE<"ceq.w", vseteq_v4i32, MSA128WOpnd>, 1793 IsCommutable; 1794class CEQ_D_DESC : MSA_3R_DESC_BASE<"ceq.d", vseteq_v2i64, MSA128DOpnd>, 1795 IsCommutable; 1796 1797class CEQI_B_DESC : MSA_I5_DESC_BASE<"ceqi.b", vseteq_v16i8, vsplati8_simm5, 1798 MSA128BOpnd>; 1799class CEQI_H_DESC : MSA_I5_DESC_BASE<"ceqi.h", vseteq_v8i16, vsplati16_simm5, 1800 MSA128HOpnd>; 1801class CEQI_W_DESC : MSA_I5_DESC_BASE<"ceqi.w", vseteq_v4i32, vsplati32_simm5, 1802 MSA128WOpnd>; 1803class CEQI_D_DESC : MSA_I5_DESC_BASE<"ceqi.d", vseteq_v2i64, vsplati64_simm5, 1804 MSA128DOpnd>; 1805 1806class CFCMSA_DESC { 1807 dag OutOperandList = (outs GPR32Opnd:$rd); 1808 dag InOperandList = (ins MSA128CROpnd:$cs); 1809 string AsmString = "cfcmsa\t$rd, $cs"; 1810 InstrItinClass Itinerary = NoItinerary; 1811 bit hasSideEffects = 1; 1812 bit isMoveReg = 1; 1813} 1814 1815class CLE_S_B_DESC : MSA_3R_DESC_BASE<"cle_s.b", vsetle_v16i8, MSA128BOpnd>; 1816class CLE_S_H_DESC : MSA_3R_DESC_BASE<"cle_s.h", vsetle_v8i16, MSA128HOpnd>; 1817class CLE_S_W_DESC : MSA_3R_DESC_BASE<"cle_s.w", vsetle_v4i32, MSA128WOpnd>; 1818class CLE_S_D_DESC : MSA_3R_DESC_BASE<"cle_s.d", vsetle_v2i64, MSA128DOpnd>; 1819 1820class CLE_U_B_DESC : MSA_3R_DESC_BASE<"cle_u.b", vsetule_v16i8, MSA128BOpnd>; 1821class CLE_U_H_DESC : MSA_3R_DESC_BASE<"cle_u.h", vsetule_v8i16, MSA128HOpnd>; 1822class CLE_U_W_DESC : MSA_3R_DESC_BASE<"cle_u.w", vsetule_v4i32, MSA128WOpnd>; 1823class CLE_U_D_DESC : MSA_3R_DESC_BASE<"cle_u.d", vsetule_v2i64, MSA128DOpnd>; 1824 1825class CLEI_S_B_DESC : MSA_I5_DESC_BASE<"clei_s.b", vsetle_v16i8, 1826 vsplati8_simm5, MSA128BOpnd>; 1827class CLEI_S_H_DESC : MSA_I5_DESC_BASE<"clei_s.h", vsetle_v8i16, 1828 vsplati16_simm5, MSA128HOpnd>; 1829class CLEI_S_W_DESC : MSA_I5_DESC_BASE<"clei_s.w", vsetle_v4i32, 1830 vsplati32_simm5, MSA128WOpnd>; 1831class CLEI_S_D_DESC : MSA_I5_DESC_BASE<"clei_s.d", vsetle_v2i64, 1832 vsplati64_simm5, MSA128DOpnd>; 1833 1834class CLEI_U_B_DESC : MSA_I5_DESC_BASE<"clei_u.b", vsetule_v16i8, 1835 vsplati8_uimm5, MSA128BOpnd>; 1836class CLEI_U_H_DESC : MSA_I5_DESC_BASE<"clei_u.h", vsetule_v8i16, 1837 vsplati16_uimm5, MSA128HOpnd>; 1838class CLEI_U_W_DESC : MSA_I5_DESC_BASE<"clei_u.w", vsetule_v4i32, 1839 vsplati32_uimm5, MSA128WOpnd>; 1840class CLEI_U_D_DESC : MSA_I5_DESC_BASE<"clei_u.d", vsetule_v2i64, 1841 vsplati64_uimm5, MSA128DOpnd>; 1842 1843class CLT_S_B_DESC : MSA_3R_DESC_BASE<"clt_s.b", vsetlt_v16i8, MSA128BOpnd>; 1844class CLT_S_H_DESC : MSA_3R_DESC_BASE<"clt_s.h", vsetlt_v8i16, MSA128HOpnd>; 1845class CLT_S_W_DESC : MSA_3R_DESC_BASE<"clt_s.w", vsetlt_v4i32, MSA128WOpnd>; 1846class CLT_S_D_DESC : MSA_3R_DESC_BASE<"clt_s.d", vsetlt_v2i64, MSA128DOpnd>; 1847 1848class CLT_U_B_DESC : MSA_3R_DESC_BASE<"clt_u.b", vsetult_v16i8, MSA128BOpnd>; 1849class CLT_U_H_DESC : MSA_3R_DESC_BASE<"clt_u.h", vsetult_v8i16, MSA128HOpnd>; 1850class CLT_U_W_DESC : MSA_3R_DESC_BASE<"clt_u.w", vsetult_v4i32, MSA128WOpnd>; 1851class CLT_U_D_DESC : MSA_3R_DESC_BASE<"clt_u.d", vsetult_v2i64, MSA128DOpnd>; 1852 1853class CLTI_S_B_DESC : MSA_I5_DESC_BASE<"clti_s.b", vsetlt_v16i8, 1854 vsplati8_simm5, MSA128BOpnd>; 1855class CLTI_S_H_DESC : MSA_I5_DESC_BASE<"clti_s.h", vsetlt_v8i16, 1856 vsplati16_simm5, MSA128HOpnd>; 1857class CLTI_S_W_DESC : MSA_I5_DESC_BASE<"clti_s.w", vsetlt_v4i32, 1858 vsplati32_simm5, MSA128WOpnd>; 1859class CLTI_S_D_DESC : MSA_I5_DESC_BASE<"clti_s.d", vsetlt_v2i64, 1860 vsplati64_simm5, MSA128DOpnd>; 1861 1862class CLTI_U_B_DESC : MSA_I5_DESC_BASE<"clti_u.b", vsetult_v16i8, 1863 vsplati8_uimm5, MSA128BOpnd>; 1864class CLTI_U_H_DESC : MSA_I5_DESC_BASE<"clti_u.h", vsetult_v8i16, 1865 vsplati16_uimm5, MSA128HOpnd>; 1866class CLTI_U_W_DESC : MSA_I5_DESC_BASE<"clti_u.w", vsetult_v4i32, 1867 vsplati32_uimm5, MSA128WOpnd>; 1868class CLTI_U_D_DESC : MSA_I5_DESC_BASE<"clti_u.d", vsetult_v2i64, 1869 vsplati64_uimm5, MSA128DOpnd>; 1870 1871class COPY_S_B_DESC : MSA_COPY_DESC_BASE<"copy_s.b", vextract_sext_i8, v16i8, 1872 uimm4_ptr, immZExt4Ptr, GPR32Opnd, 1873 MSA128BOpnd>; 1874class COPY_S_H_DESC : MSA_COPY_DESC_BASE<"copy_s.h", vextract_sext_i16, v8i16, 1875 uimm3_ptr, immZExt3Ptr, GPR32Opnd, 1876 MSA128HOpnd>; 1877class COPY_S_W_DESC : MSA_COPY_DESC_BASE<"copy_s.w", vextract_sext_i32, v4i32, 1878 uimm2_ptr, immZExt2Ptr, GPR32Opnd, 1879 MSA128WOpnd>; 1880class COPY_S_D_DESC : MSA_COPY_DESC_BASE<"copy_s.d", vextract_sext_i64, v2i64, 1881 uimm1_ptr, immZExt1Ptr, GPR64Opnd, 1882 MSA128DOpnd>; 1883 1884class COPY_U_B_DESC : MSA_COPY_DESC_BASE<"copy_u.b", vextract_zext_i8, v16i8, 1885 uimm4_ptr, immZExt4Ptr, GPR32Opnd, 1886 MSA128BOpnd>; 1887class COPY_U_H_DESC : MSA_COPY_DESC_BASE<"copy_u.h", vextract_zext_i16, v8i16, 1888 uimm3_ptr, immZExt3Ptr, GPR32Opnd, 1889 MSA128HOpnd>; 1890class COPY_U_W_DESC : MSA_COPY_DESC_BASE<"copy_u.w", vextract_zext_i32, v4i32, 1891 uimm2_ptr, immZExt2Ptr, GPR32Opnd, 1892 MSA128WOpnd>; 1893 1894class COPY_FW_PSEUDO_DESC : MSA_COPY_PSEUDO_BASE<vector_extract, v4f32, 1895 uimm2_ptr, immZExt2Ptr, FGR32, 1896 MSA128W>; 1897class COPY_FD_PSEUDO_DESC : MSA_COPY_PSEUDO_BASE<vector_extract, v2f64, 1898 uimm1_ptr, immZExt1Ptr, FGR64, 1899 MSA128D>; 1900 1901class CTCMSA_DESC { 1902 dag OutOperandList = (outs); 1903 dag InOperandList = (ins MSA128CROpnd:$cd, GPR32Opnd:$rs); 1904 string AsmString = "ctcmsa\t$cd, $rs"; 1905 InstrItinClass Itinerary = NoItinerary; 1906 bit hasSideEffects = 1; 1907 bit isMoveReg = 1; 1908} 1909 1910class DIV_S_B_DESC : MSA_3R_DESC_BASE<"div_s.b", sdiv, MSA128BOpnd>; 1911class DIV_S_H_DESC : MSA_3R_DESC_BASE<"div_s.h", sdiv, MSA128HOpnd>; 1912class DIV_S_W_DESC : MSA_3R_DESC_BASE<"div_s.w", sdiv, MSA128WOpnd>; 1913class DIV_S_D_DESC : MSA_3R_DESC_BASE<"div_s.d", sdiv, MSA128DOpnd>; 1914 1915class DIV_U_B_DESC : MSA_3R_DESC_BASE<"div_u.b", udiv, MSA128BOpnd>; 1916class DIV_U_H_DESC : MSA_3R_DESC_BASE<"div_u.h", udiv, MSA128HOpnd>; 1917class DIV_U_W_DESC : MSA_3R_DESC_BASE<"div_u.w", udiv, MSA128WOpnd>; 1918class DIV_U_D_DESC : MSA_3R_DESC_BASE<"div_u.d", udiv, MSA128DOpnd>; 1919 1920class DOTP_S_H_DESC : MSA_3R_DESC_BASE<"dotp_s.h", int_mips_dotp_s_h, 1921 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>, 1922 IsCommutable; 1923class DOTP_S_W_DESC : MSA_3R_DESC_BASE<"dotp_s.w", int_mips_dotp_s_w, 1924 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>, 1925 IsCommutable; 1926class DOTP_S_D_DESC : MSA_3R_DESC_BASE<"dotp_s.d", int_mips_dotp_s_d, 1927 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>, 1928 IsCommutable; 1929 1930class DOTP_U_H_DESC : MSA_3R_DESC_BASE<"dotp_u.h", int_mips_dotp_u_h, 1931 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>, 1932 IsCommutable; 1933class DOTP_U_W_DESC : MSA_3R_DESC_BASE<"dotp_u.w", int_mips_dotp_u_w, 1934 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>, 1935 IsCommutable; 1936class DOTP_U_D_DESC : MSA_3R_DESC_BASE<"dotp_u.d", int_mips_dotp_u_d, 1937 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>, 1938 IsCommutable; 1939 1940class DPADD_S_H_DESC : MSA_3R_4R_DESC_BASE<"dpadd_s.h", int_mips_dpadd_s_h, 1941 MSA128HOpnd, MSA128BOpnd, 1942 MSA128BOpnd>, IsCommutable; 1943class DPADD_S_W_DESC : MSA_3R_4R_DESC_BASE<"dpadd_s.w", int_mips_dpadd_s_w, 1944 MSA128WOpnd, MSA128HOpnd, 1945 MSA128HOpnd>, IsCommutable; 1946class DPADD_S_D_DESC : MSA_3R_4R_DESC_BASE<"dpadd_s.d", int_mips_dpadd_s_d, 1947 MSA128DOpnd, MSA128WOpnd, 1948 MSA128WOpnd>, IsCommutable; 1949 1950class DPADD_U_H_DESC : MSA_3R_4R_DESC_BASE<"dpadd_u.h", int_mips_dpadd_u_h, 1951 MSA128HOpnd, MSA128BOpnd, 1952 MSA128BOpnd>, IsCommutable; 1953class DPADD_U_W_DESC : MSA_3R_4R_DESC_BASE<"dpadd_u.w", int_mips_dpadd_u_w, 1954 MSA128WOpnd, MSA128HOpnd, 1955 MSA128HOpnd>, IsCommutable; 1956class DPADD_U_D_DESC : MSA_3R_4R_DESC_BASE<"dpadd_u.d", int_mips_dpadd_u_d, 1957 MSA128DOpnd, MSA128WOpnd, 1958 MSA128WOpnd>, IsCommutable; 1959 1960class DPSUB_S_H_DESC : MSA_3R_4R_DESC_BASE<"dpsub_s.h", int_mips_dpsub_s_h, 1961 MSA128HOpnd, MSA128BOpnd, 1962 MSA128BOpnd>; 1963class DPSUB_S_W_DESC : MSA_3R_4R_DESC_BASE<"dpsub_s.w", int_mips_dpsub_s_w, 1964 MSA128WOpnd, MSA128HOpnd, 1965 MSA128HOpnd>; 1966class DPSUB_S_D_DESC : MSA_3R_4R_DESC_BASE<"dpsub_s.d", int_mips_dpsub_s_d, 1967 MSA128DOpnd, MSA128WOpnd, 1968 MSA128WOpnd>; 1969 1970class DPSUB_U_H_DESC : MSA_3R_4R_DESC_BASE<"dpsub_u.h", int_mips_dpsub_u_h, 1971 MSA128HOpnd, MSA128BOpnd, 1972 MSA128BOpnd>; 1973class DPSUB_U_W_DESC : MSA_3R_4R_DESC_BASE<"dpsub_u.w", int_mips_dpsub_u_w, 1974 MSA128WOpnd, MSA128HOpnd, 1975 MSA128HOpnd>; 1976class DPSUB_U_D_DESC : MSA_3R_4R_DESC_BASE<"dpsub_u.d", int_mips_dpsub_u_d, 1977 MSA128DOpnd, MSA128WOpnd, 1978 MSA128WOpnd>; 1979 1980class FADD_W_DESC : MSA_3RF_DESC_BASE<"fadd.w", fadd, MSA128WOpnd>, 1981 IsCommutable; 1982class FADD_D_DESC : MSA_3RF_DESC_BASE<"fadd.d", fadd, MSA128DOpnd>, 1983 IsCommutable; 1984 1985class FCAF_W_DESC : MSA_3RF_DESC_BASE<"fcaf.w", int_mips_fcaf_w, MSA128WOpnd>, 1986 IsCommutable; 1987class FCAF_D_DESC : MSA_3RF_DESC_BASE<"fcaf.d", int_mips_fcaf_d, MSA128DOpnd>, 1988 IsCommutable; 1989 1990class FCEQ_W_DESC : MSA_3RF_DESC_BASE<"fceq.w", vfsetoeq_v4f32, MSA128WOpnd>, 1991 IsCommutable; 1992class FCEQ_D_DESC : MSA_3RF_DESC_BASE<"fceq.d", vfsetoeq_v2f64, MSA128DOpnd>, 1993 IsCommutable; 1994 1995class FCLASS_W_DESC : MSA_2RF_DESC_BASE<"fclass.w", int_mips_fclass_w, 1996 MSA128WOpnd>; 1997class FCLASS_D_DESC : MSA_2RF_DESC_BASE<"fclass.d", int_mips_fclass_d, 1998 MSA128DOpnd>; 1999 2000class FCLE_W_DESC : MSA_3RF_DESC_BASE<"fcle.w", vfsetole_v4f32, MSA128WOpnd>; 2001class FCLE_D_DESC : MSA_3RF_DESC_BASE<"fcle.d", vfsetole_v2f64, MSA128DOpnd>; 2002 2003class FCLT_W_DESC : MSA_3RF_DESC_BASE<"fclt.w", vfsetolt_v4f32, MSA128WOpnd>; 2004class FCLT_D_DESC : MSA_3RF_DESC_BASE<"fclt.d", vfsetolt_v2f64, MSA128DOpnd>; 2005 2006class FCNE_W_DESC : MSA_3RF_DESC_BASE<"fcne.w", vfsetone_v4f32, MSA128WOpnd>, 2007 IsCommutable; 2008class FCNE_D_DESC : MSA_3RF_DESC_BASE<"fcne.d", vfsetone_v2f64, MSA128DOpnd>, 2009 IsCommutable; 2010 2011class FCOR_W_DESC : MSA_3RF_DESC_BASE<"fcor.w", vfsetord_v4f32, MSA128WOpnd>, 2012 IsCommutable; 2013class FCOR_D_DESC : MSA_3RF_DESC_BASE<"fcor.d", vfsetord_v2f64, MSA128DOpnd>, 2014 IsCommutable; 2015 2016class FCUEQ_W_DESC : MSA_3RF_DESC_BASE<"fcueq.w", vfsetueq_v4f32, MSA128WOpnd>, 2017 IsCommutable; 2018class FCUEQ_D_DESC : MSA_3RF_DESC_BASE<"fcueq.d", vfsetueq_v2f64, MSA128DOpnd>, 2019 IsCommutable; 2020 2021class FCULE_W_DESC : MSA_3RF_DESC_BASE<"fcule.w", vfsetule_v4f32, MSA128WOpnd>, 2022 IsCommutable; 2023class FCULE_D_DESC : MSA_3RF_DESC_BASE<"fcule.d", vfsetule_v2f64, MSA128DOpnd>, 2024 IsCommutable; 2025 2026class FCULT_W_DESC : MSA_3RF_DESC_BASE<"fcult.w", vfsetult_v4f32, MSA128WOpnd>, 2027 IsCommutable; 2028class FCULT_D_DESC : MSA_3RF_DESC_BASE<"fcult.d", vfsetult_v2f64, MSA128DOpnd>, 2029 IsCommutable; 2030 2031class FCUN_W_DESC : MSA_3RF_DESC_BASE<"fcun.w", vfsetun_v4f32, MSA128WOpnd>, 2032 IsCommutable; 2033class FCUN_D_DESC : MSA_3RF_DESC_BASE<"fcun.d", vfsetun_v2f64, MSA128DOpnd>, 2034 IsCommutable; 2035 2036class FCUNE_W_DESC : MSA_3RF_DESC_BASE<"fcune.w", vfsetune_v4f32, MSA128WOpnd>, 2037 IsCommutable; 2038class FCUNE_D_DESC : MSA_3RF_DESC_BASE<"fcune.d", vfsetune_v2f64, MSA128DOpnd>, 2039 IsCommutable; 2040 2041class FDIV_W_DESC : MSA_3RF_DESC_BASE<"fdiv.w", fdiv, MSA128WOpnd>; 2042class FDIV_D_DESC : MSA_3RF_DESC_BASE<"fdiv.d", fdiv, MSA128DOpnd>; 2043 2044class FEXDO_H_DESC : MSA_3RF_DESC_BASE<"fexdo.h", int_mips_fexdo_h, 2045 MSA128HOpnd, MSA128WOpnd, MSA128WOpnd>; 2046class FEXDO_W_DESC : MSA_3RF_DESC_BASE<"fexdo.w", int_mips_fexdo_w, 2047 MSA128WOpnd, MSA128DOpnd, MSA128DOpnd>; 2048 2049// The fexp2.df instruction multiplies the first operand by 2 to the power of 2050// the second operand. We therefore need a pseudo-insn in order to invent the 2051// 1.0 when we only need to match ISD::FEXP2. 2052class FEXP2_W_DESC : MSA_3RF_DESC_BASE<"fexp2.w", mul_fexp2, MSA128WOpnd>; 2053class FEXP2_D_DESC : MSA_3RF_DESC_BASE<"fexp2.d", mul_fexp2, MSA128DOpnd>; 2054let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in { 2055 class FEXP2_W_1_PSEUDO_DESC : 2056 MSAPseudo<(outs MSA128W:$wd), (ins MSA128W:$ws), 2057 [(set MSA128W:$wd, (fexp2 MSA128W:$ws))]>; 2058 class FEXP2_D_1_PSEUDO_DESC : 2059 MSAPseudo<(outs MSA128D:$wd), (ins MSA128D:$ws), 2060 [(set MSA128D:$wd, (fexp2 MSA128D:$ws))]>; 2061} 2062 2063class FEXUPL_W_DESC : MSA_2RF_DESC_BASE<"fexupl.w", int_mips_fexupl_w, 2064 MSA128WOpnd, MSA128HOpnd>; 2065class FEXUPL_D_DESC : MSA_2RF_DESC_BASE<"fexupl.d", int_mips_fexupl_d, 2066 MSA128DOpnd, MSA128WOpnd>; 2067 2068class FEXUPR_W_DESC : MSA_2RF_DESC_BASE<"fexupr.w", int_mips_fexupr_w, 2069 MSA128WOpnd, MSA128HOpnd>; 2070class FEXUPR_D_DESC : MSA_2RF_DESC_BASE<"fexupr.d", int_mips_fexupr_d, 2071 MSA128DOpnd, MSA128WOpnd>; 2072 2073class FFINT_S_W_DESC : MSA_2RF_DESC_BASE<"ffint_s.w", sint_to_fp, MSA128WOpnd>; 2074class FFINT_S_D_DESC : MSA_2RF_DESC_BASE<"ffint_s.d", sint_to_fp, MSA128DOpnd>; 2075 2076class FFINT_U_W_DESC : MSA_2RF_DESC_BASE<"ffint_u.w", uint_to_fp, MSA128WOpnd>; 2077class FFINT_U_D_DESC : MSA_2RF_DESC_BASE<"ffint_u.d", uint_to_fp, MSA128DOpnd>; 2078 2079class FFQL_W_DESC : MSA_2RF_DESC_BASE<"ffql.w", int_mips_ffql_w, 2080 MSA128WOpnd, MSA128HOpnd>; 2081class FFQL_D_DESC : MSA_2RF_DESC_BASE<"ffql.d", int_mips_ffql_d, 2082 MSA128DOpnd, MSA128WOpnd>; 2083 2084class FFQR_W_DESC : MSA_2RF_DESC_BASE<"ffqr.w", int_mips_ffqr_w, 2085 MSA128WOpnd, MSA128HOpnd>; 2086class FFQR_D_DESC : MSA_2RF_DESC_BASE<"ffqr.d", int_mips_ffqr_d, 2087 MSA128DOpnd, MSA128WOpnd>; 2088 2089class FILL_B_DESC : MSA_2R_FILL_DESC_BASE<"fill.b", v16i8, vsplati8, 2090 MSA128BOpnd, GPR32Opnd>; 2091class FILL_H_DESC : MSA_2R_FILL_DESC_BASE<"fill.h", v8i16, vsplati16, 2092 MSA128HOpnd, GPR32Opnd>; 2093class FILL_W_DESC : MSA_2R_FILL_DESC_BASE<"fill.w", v4i32, vsplati32, 2094 MSA128WOpnd, GPR32Opnd>; 2095class FILL_D_DESC : MSA_2R_FILL_DESC_BASE<"fill.d", v2i64, vsplati64, 2096 MSA128DOpnd, GPR64Opnd>; 2097 2098class FILL_FW_PSEUDO_DESC : MSA_2R_FILL_PSEUDO_BASE<v4f32, vsplatf32, MSA128W, 2099 FGR32>; 2100class FILL_FD_PSEUDO_DESC : MSA_2R_FILL_PSEUDO_BASE<v2f64, vsplatf64, MSA128D, 2101 FGR64>; 2102 2103class FLOG2_W_DESC : MSA_2RF_DESC_BASE<"flog2.w", flog2, MSA128WOpnd>; 2104class FLOG2_D_DESC : MSA_2RF_DESC_BASE<"flog2.d", flog2, MSA128DOpnd>; 2105 2106class FMADD_W_DESC : MSA_3RF_4RF_DESC_BASE<"fmadd.w", fma, MSA128WOpnd>; 2107class FMADD_D_DESC : MSA_3RF_4RF_DESC_BASE<"fmadd.d", fma, MSA128DOpnd>; 2108 2109class FMAX_W_DESC : MSA_3RF_DESC_BASE<"fmax.w", int_mips_fmax_w, MSA128WOpnd>; 2110class FMAX_D_DESC : MSA_3RF_DESC_BASE<"fmax.d", int_mips_fmax_d, MSA128DOpnd>; 2111 2112class FMAX_A_W_DESC : MSA_3RF_DESC_BASE<"fmax_a.w", int_mips_fmax_a_w, 2113 MSA128WOpnd>; 2114class FMAX_A_D_DESC : MSA_3RF_DESC_BASE<"fmax_a.d", int_mips_fmax_a_d, 2115 MSA128DOpnd>; 2116 2117class FMIN_W_DESC : MSA_3RF_DESC_BASE<"fmin.w", int_mips_fmin_w, MSA128WOpnd>; 2118class FMIN_D_DESC : MSA_3RF_DESC_BASE<"fmin.d", int_mips_fmin_d, MSA128DOpnd>; 2119 2120class FMIN_A_W_DESC : MSA_3RF_DESC_BASE<"fmin_a.w", int_mips_fmin_a_w, 2121 MSA128WOpnd>; 2122class FMIN_A_D_DESC : MSA_3RF_DESC_BASE<"fmin_a.d", int_mips_fmin_a_d, 2123 MSA128DOpnd>; 2124 2125class FMSUB_W_DESC : MSA_3RF_4RF_DESC_BASE<"fmsub.w", MipsFMS, MSA128WOpnd>; 2126class FMSUB_D_DESC : MSA_3RF_4RF_DESC_BASE<"fmsub.d", MipsFMS, MSA128DOpnd>; 2127 2128class FMUL_W_DESC : MSA_3RF_DESC_BASE<"fmul.w", fmul, MSA128WOpnd>; 2129class FMUL_D_DESC : MSA_3RF_DESC_BASE<"fmul.d", fmul, MSA128DOpnd>; 2130 2131class FRINT_W_DESC : MSA_2RF_DESC_BASE<"frint.w", frint, MSA128WOpnd>; 2132class FRINT_D_DESC : MSA_2RF_DESC_BASE<"frint.d", frint, MSA128DOpnd>; 2133 2134class FRCP_W_DESC : MSA_2RF_DESC_BASE<"frcp.w", int_mips_frcp_w, MSA128WOpnd>; 2135class FRCP_D_DESC : MSA_2RF_DESC_BASE<"frcp.d", int_mips_frcp_d, MSA128DOpnd>; 2136 2137class FRSQRT_W_DESC : MSA_2RF_DESC_BASE<"frsqrt.w", int_mips_frsqrt_w, 2138 MSA128WOpnd>; 2139class FRSQRT_D_DESC : MSA_2RF_DESC_BASE<"frsqrt.d", int_mips_frsqrt_d, 2140 MSA128DOpnd>; 2141 2142class FSAF_W_DESC : MSA_3RF_DESC_BASE<"fsaf.w", int_mips_fsaf_w, MSA128WOpnd>; 2143class FSAF_D_DESC : MSA_3RF_DESC_BASE<"fsaf.d", int_mips_fsaf_d, MSA128DOpnd>; 2144 2145class FSEQ_W_DESC : MSA_3RF_DESC_BASE<"fseq.w", int_mips_fseq_w, MSA128WOpnd>; 2146class FSEQ_D_DESC : MSA_3RF_DESC_BASE<"fseq.d", int_mips_fseq_d, MSA128DOpnd>; 2147 2148class FSLE_W_DESC : MSA_3RF_DESC_BASE<"fsle.w", int_mips_fsle_w, MSA128WOpnd>; 2149class FSLE_D_DESC : MSA_3RF_DESC_BASE<"fsle.d", int_mips_fsle_d, MSA128DOpnd>; 2150 2151class FSLT_W_DESC : MSA_3RF_DESC_BASE<"fslt.w", int_mips_fslt_w, MSA128WOpnd>; 2152class FSLT_D_DESC : MSA_3RF_DESC_BASE<"fslt.d", int_mips_fslt_d, MSA128DOpnd>; 2153 2154class FSNE_W_DESC : MSA_3RF_DESC_BASE<"fsne.w", int_mips_fsne_w, MSA128WOpnd>; 2155class FSNE_D_DESC : MSA_3RF_DESC_BASE<"fsne.d", int_mips_fsne_d, MSA128DOpnd>; 2156 2157class FSOR_W_DESC : MSA_3RF_DESC_BASE<"fsor.w", int_mips_fsor_w, MSA128WOpnd>; 2158class FSOR_D_DESC : MSA_3RF_DESC_BASE<"fsor.d", int_mips_fsor_d, MSA128DOpnd>; 2159 2160class FSQRT_W_DESC : MSA_2RF_DESC_BASE<"fsqrt.w", fsqrt, MSA128WOpnd>; 2161class FSQRT_D_DESC : MSA_2RF_DESC_BASE<"fsqrt.d", fsqrt, MSA128DOpnd>; 2162 2163class FSUB_W_DESC : MSA_3RF_DESC_BASE<"fsub.w", fsub, MSA128WOpnd>; 2164class FSUB_D_DESC : MSA_3RF_DESC_BASE<"fsub.d", fsub, MSA128DOpnd>; 2165 2166class FSUEQ_W_DESC : MSA_3RF_DESC_BASE<"fsueq.w", int_mips_fsueq_w, 2167 MSA128WOpnd>; 2168class FSUEQ_D_DESC : MSA_3RF_DESC_BASE<"fsueq.d", int_mips_fsueq_d, 2169 MSA128DOpnd>; 2170 2171class FSULE_W_DESC : MSA_3RF_DESC_BASE<"fsule.w", int_mips_fsule_w, 2172 MSA128WOpnd>; 2173class FSULE_D_DESC : MSA_3RF_DESC_BASE<"fsule.d", int_mips_fsule_d, 2174 MSA128DOpnd>; 2175 2176class FSULT_W_DESC : MSA_3RF_DESC_BASE<"fsult.w", int_mips_fsult_w, 2177 MSA128WOpnd>; 2178class FSULT_D_DESC : MSA_3RF_DESC_BASE<"fsult.d", int_mips_fsult_d, 2179 MSA128DOpnd>; 2180 2181class FSUN_W_DESC : MSA_3RF_DESC_BASE<"fsun.w", int_mips_fsun_w, 2182 MSA128WOpnd>; 2183class FSUN_D_DESC : MSA_3RF_DESC_BASE<"fsun.d", int_mips_fsun_d, 2184 MSA128DOpnd>; 2185 2186class FSUNE_W_DESC : MSA_3RF_DESC_BASE<"fsune.w", int_mips_fsune_w, 2187 MSA128WOpnd>; 2188class FSUNE_D_DESC : MSA_3RF_DESC_BASE<"fsune.d", int_mips_fsune_d, 2189 MSA128DOpnd>; 2190 2191class FTINT_S_W_DESC : MSA_2RF_DESC_BASE<"ftint_s.w", int_mips_ftint_s_w, 2192 MSA128WOpnd>; 2193class FTINT_S_D_DESC : MSA_2RF_DESC_BASE<"ftint_s.d", int_mips_ftint_s_d, 2194 MSA128DOpnd>; 2195 2196class FTINT_U_W_DESC : MSA_2RF_DESC_BASE<"ftint_u.w", int_mips_ftint_u_w, 2197 MSA128WOpnd>; 2198class FTINT_U_D_DESC : MSA_2RF_DESC_BASE<"ftint_u.d", int_mips_ftint_u_d, 2199 MSA128DOpnd>; 2200 2201class FTQ_H_DESC : MSA_3RF_DESC_BASE<"ftq.h", int_mips_ftq_h, 2202 MSA128HOpnd, MSA128WOpnd, MSA128WOpnd>; 2203class FTQ_W_DESC : MSA_3RF_DESC_BASE<"ftq.w", int_mips_ftq_w, 2204 MSA128WOpnd, MSA128DOpnd, MSA128DOpnd>; 2205 2206class FTRUNC_S_W_DESC : MSA_2RF_DESC_BASE<"ftrunc_s.w", fp_to_sint, 2207 MSA128WOpnd>; 2208class FTRUNC_S_D_DESC : MSA_2RF_DESC_BASE<"ftrunc_s.d", fp_to_sint, 2209 MSA128DOpnd>; 2210 2211class FTRUNC_U_W_DESC : MSA_2RF_DESC_BASE<"ftrunc_u.w", fp_to_uint, 2212 MSA128WOpnd>; 2213class FTRUNC_U_D_DESC : MSA_2RF_DESC_BASE<"ftrunc_u.d", fp_to_uint, 2214 MSA128DOpnd>; 2215 2216class HADD_S_H_DESC : MSA_3R_DESC_BASE<"hadd_s.h", int_mips_hadd_s_h, 2217 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>; 2218class HADD_S_W_DESC : MSA_3R_DESC_BASE<"hadd_s.w", int_mips_hadd_s_w, 2219 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>; 2220class HADD_S_D_DESC : MSA_3R_DESC_BASE<"hadd_s.d", int_mips_hadd_s_d, 2221 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>; 2222 2223class HADD_U_H_DESC : MSA_3R_DESC_BASE<"hadd_u.h", int_mips_hadd_u_h, 2224 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>; 2225class HADD_U_W_DESC : MSA_3R_DESC_BASE<"hadd_u.w", int_mips_hadd_u_w, 2226 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>; 2227class HADD_U_D_DESC : MSA_3R_DESC_BASE<"hadd_u.d", int_mips_hadd_u_d, 2228 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>; 2229 2230class HSUB_S_H_DESC : MSA_3R_DESC_BASE<"hsub_s.h", int_mips_hsub_s_h, 2231 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>; 2232class HSUB_S_W_DESC : MSA_3R_DESC_BASE<"hsub_s.w", int_mips_hsub_s_w, 2233 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>; 2234class HSUB_S_D_DESC : MSA_3R_DESC_BASE<"hsub_s.d", int_mips_hsub_s_d, 2235 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>; 2236 2237class HSUB_U_H_DESC : MSA_3R_DESC_BASE<"hsub_u.h", int_mips_hsub_u_h, 2238 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>; 2239class HSUB_U_W_DESC : MSA_3R_DESC_BASE<"hsub_u.w", int_mips_hsub_u_w, 2240 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>; 2241class HSUB_U_D_DESC : MSA_3R_DESC_BASE<"hsub_u.d", int_mips_hsub_u_d, 2242 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>; 2243 2244class ILVEV_B_DESC : MSA_3R_DESC_BASE<"ilvev.b", MipsILVEV, MSA128BOpnd>; 2245class ILVEV_H_DESC : MSA_3R_DESC_BASE<"ilvev.h", MipsILVEV, MSA128HOpnd>; 2246class ILVEV_W_DESC : MSA_3R_DESC_BASE<"ilvev.w", MipsILVEV, MSA128WOpnd>; 2247class ILVEV_D_DESC : MSA_3R_DESC_BASE<"ilvev.d", MipsILVEV, MSA128DOpnd>; 2248 2249class ILVL_B_DESC : MSA_3R_DESC_BASE<"ilvl.b", MipsILVL, MSA128BOpnd>; 2250class ILVL_H_DESC : MSA_3R_DESC_BASE<"ilvl.h", MipsILVL, MSA128HOpnd>; 2251class ILVL_W_DESC : MSA_3R_DESC_BASE<"ilvl.w", MipsILVL, MSA128WOpnd>; 2252class ILVL_D_DESC : MSA_3R_DESC_BASE<"ilvl.d", MipsILVL, MSA128DOpnd>; 2253 2254class ILVOD_B_DESC : MSA_3R_DESC_BASE<"ilvod.b", MipsILVOD, MSA128BOpnd>; 2255class ILVOD_H_DESC : MSA_3R_DESC_BASE<"ilvod.h", MipsILVOD, MSA128HOpnd>; 2256class ILVOD_W_DESC : MSA_3R_DESC_BASE<"ilvod.w", MipsILVOD, MSA128WOpnd>; 2257class ILVOD_D_DESC : MSA_3R_DESC_BASE<"ilvod.d", MipsILVOD, MSA128DOpnd>; 2258 2259class ILVR_B_DESC : MSA_3R_DESC_BASE<"ilvr.b", MipsILVR, MSA128BOpnd>; 2260class ILVR_H_DESC : MSA_3R_DESC_BASE<"ilvr.h", MipsILVR, MSA128HOpnd>; 2261class ILVR_W_DESC : MSA_3R_DESC_BASE<"ilvr.w", MipsILVR, MSA128WOpnd>; 2262class ILVR_D_DESC : MSA_3R_DESC_BASE<"ilvr.d", MipsILVR, MSA128DOpnd>; 2263 2264class INSERT_B_DESC : MSA_INSERT_DESC_BASE<"insert.b", vinsert_v16i8, uimm4, 2265 immZExt4Ptr, MSA128BOpnd, GPR32Opnd>; 2266class INSERT_H_DESC : MSA_INSERT_DESC_BASE<"insert.h", vinsert_v8i16, uimm3, 2267 immZExt3Ptr, MSA128HOpnd, GPR32Opnd>; 2268class INSERT_W_DESC : MSA_INSERT_DESC_BASE<"insert.w", vinsert_v4i32, uimm2, 2269 immZExt2Ptr, MSA128WOpnd, GPR32Opnd>; 2270class INSERT_D_DESC : MSA_INSERT_DESC_BASE<"insert.d", vinsert_v2i64, uimm1, 2271 immZExt1Ptr, MSA128DOpnd, GPR64Opnd>; 2272 2273class INSERT_B_VIDX_PSEUDO_DESC : 2274 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v16i8, MSA128BOpnd, GPR32Opnd, GPR32Opnd>; 2275class INSERT_H_VIDX_PSEUDO_DESC : 2276 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v8i16, MSA128HOpnd, GPR32Opnd, GPR32Opnd>; 2277class INSERT_W_VIDX_PSEUDO_DESC : 2278 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v4i32, MSA128WOpnd, GPR32Opnd, GPR32Opnd>; 2279class INSERT_D_VIDX_PSEUDO_DESC : 2280 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v2i64, MSA128DOpnd, GPR64Opnd, GPR32Opnd>; 2281 2282class INSERT_FW_PSEUDO_DESC : MSA_INSERT_PSEUDO_BASE<vector_insert, v4f32, 2283 uimm2, immZExt2Ptr, 2284 MSA128WOpnd, FGR32Opnd>; 2285class INSERT_FD_PSEUDO_DESC : MSA_INSERT_PSEUDO_BASE<vector_insert, v2f64, 2286 uimm1, immZExt1Ptr, 2287 MSA128DOpnd, FGR64Opnd>; 2288 2289class INSERT_FW_VIDX_PSEUDO_DESC : 2290 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v4f32, MSA128WOpnd, FGR32Opnd, GPR32Opnd>; 2291class INSERT_FD_VIDX_PSEUDO_DESC : 2292 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v2f64, MSA128DOpnd, FGR64Opnd, GPR32Opnd>; 2293 2294class INSERT_B_VIDX64_PSEUDO_DESC : 2295 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v16i8, MSA128BOpnd, GPR32Opnd, GPR64Opnd>; 2296class INSERT_H_VIDX64_PSEUDO_DESC : 2297 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v8i16, MSA128HOpnd, GPR32Opnd, GPR64Opnd>; 2298class INSERT_W_VIDX64_PSEUDO_DESC : 2299 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v4i32, MSA128WOpnd, GPR32Opnd, GPR64Opnd>; 2300class INSERT_D_VIDX64_PSEUDO_DESC : 2301 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v2i64, MSA128DOpnd, GPR64Opnd, GPR64Opnd>; 2302 2303class INSERT_FW_VIDX64_PSEUDO_DESC : 2304 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v4f32, MSA128WOpnd, FGR32Opnd, GPR64Opnd>; 2305class INSERT_FD_VIDX64_PSEUDO_DESC : 2306 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v2f64, MSA128DOpnd, FGR64Opnd, GPR64Opnd>; 2307 2308class INSVE_B_DESC : MSA_INSVE_DESC_BASE<"insve.b", insve_v16i8, uimm4, timmZExt4, 2309 MSA128BOpnd>; 2310class INSVE_H_DESC : MSA_INSVE_DESC_BASE<"insve.h", insve_v8i16, uimm3, timmZExt3, 2311 MSA128HOpnd>; 2312class INSVE_W_DESC : MSA_INSVE_DESC_BASE<"insve.w", insve_v4i32, uimm2, timmZExt2, 2313 MSA128WOpnd>; 2314class INSVE_D_DESC : MSA_INSVE_DESC_BASE<"insve.d", insve_v2i64, uimm1, timmZExt1, 2315 MSA128DOpnd>; 2316 2317class LD_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 2318 ValueType TyNode, RegisterOperand ROWD, 2319 Operand MemOpnd, ComplexPattern Addr = addrimm10, 2320 InstrItinClass itin = NoItinerary> { 2321 dag OutOperandList = (outs ROWD:$wd); 2322 dag InOperandList = (ins MemOpnd:$addr); 2323 string AsmString = !strconcat(instr_asm, "\t$wd, $addr"); 2324 list<dag> Pattern = [(set ROWD:$wd, (TyNode (OpNode Addr:$addr)))]; 2325 InstrItinClass Itinerary = itin; 2326 string DecoderMethod = "DecodeMSA128Mem"; 2327} 2328 2329class LD_B_DESC : LD_DESC_BASE<"ld.b", load, v16i8, MSA128BOpnd, mem_simm10>; 2330class LD_H_DESC : LD_DESC_BASE<"ld.h", load, v8i16, MSA128HOpnd, 2331 mem_simm10_lsl1, addrimm10lsl1>; 2332class LD_W_DESC : LD_DESC_BASE<"ld.w", load, v4i32, MSA128WOpnd, 2333 mem_simm10_lsl2, addrimm10lsl2>; 2334class LD_D_DESC : LD_DESC_BASE<"ld.d", load, v2i64, MSA128DOpnd, 2335 mem_simm10_lsl3, addrimm10lsl3>; 2336 2337class LDI_B_DESC : MSA_I10_LDI_DESC_BASE<"ldi.b", MSA128BOpnd>; 2338class LDI_H_DESC : MSA_I10_LDI_DESC_BASE<"ldi.h", MSA128HOpnd>; 2339class LDI_W_DESC : MSA_I10_LDI_DESC_BASE<"ldi.w", MSA128WOpnd>; 2340class LDI_D_DESC : MSA_I10_LDI_DESC_BASE<"ldi.d", MSA128DOpnd>; 2341 2342class LSA_DESC_BASE<string instr_asm, RegisterOperand RORD, 2343 InstrItinClass itin = NoItinerary> { 2344 dag OutOperandList = (outs RORD:$rd); 2345 dag InOperandList = (ins RORD:$rs, RORD:$rt, uimm2_plus1:$sa); 2346 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $sa"); 2347 list<dag> Pattern = [(set RORD:$rd, (add RORD:$rt, 2348 (shl RORD:$rs, 2349 immZExt2Lsa:$sa)))]; 2350 InstrItinClass Itinerary = itin; 2351} 2352 2353class LSA_DESC : LSA_DESC_BASE<"lsa", GPR32Opnd, II_LSA>; 2354class DLSA_DESC : LSA_DESC_BASE<"dlsa", GPR64Opnd, II_DLSA>; 2355 2356class MADD_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"madd_q.h", int_mips_madd_q_h, 2357 MSA128HOpnd>; 2358class MADD_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"madd_q.w", int_mips_madd_q_w, 2359 MSA128WOpnd>; 2360 2361class MADDR_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"maddr_q.h", int_mips_maddr_q_h, 2362 MSA128HOpnd>; 2363class MADDR_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"maddr_q.w", int_mips_maddr_q_w, 2364 MSA128WOpnd>; 2365 2366class MADDV_B_DESC : MSA_3R_4R_DESC_BASE<"maddv.b", muladd, MSA128BOpnd>; 2367class MADDV_H_DESC : MSA_3R_4R_DESC_BASE<"maddv.h", muladd, MSA128HOpnd>; 2368class MADDV_W_DESC : MSA_3R_4R_DESC_BASE<"maddv.w", muladd, MSA128WOpnd>; 2369class MADDV_D_DESC : MSA_3R_4R_DESC_BASE<"maddv.d", muladd, MSA128DOpnd>; 2370 2371class MAX_A_B_DESC : MSA_3R_DESC_BASE<"max_a.b", int_mips_max_a_b, MSA128BOpnd>; 2372class MAX_A_H_DESC : MSA_3R_DESC_BASE<"max_a.h", int_mips_max_a_h, MSA128HOpnd>; 2373class MAX_A_W_DESC : MSA_3R_DESC_BASE<"max_a.w", int_mips_max_a_w, MSA128WOpnd>; 2374class MAX_A_D_DESC : MSA_3R_DESC_BASE<"max_a.d", int_mips_max_a_d, MSA128DOpnd>; 2375 2376class MAX_S_B_DESC : MSA_3R_DESC_BASE<"max_s.b", smax, MSA128BOpnd>; 2377class MAX_S_H_DESC : MSA_3R_DESC_BASE<"max_s.h", smax, MSA128HOpnd>; 2378class MAX_S_W_DESC : MSA_3R_DESC_BASE<"max_s.w", smax, MSA128WOpnd>; 2379class MAX_S_D_DESC : MSA_3R_DESC_BASE<"max_s.d", smax, MSA128DOpnd>; 2380 2381class MAX_U_B_DESC : MSA_3R_DESC_BASE<"max_u.b", umax, MSA128BOpnd>; 2382class MAX_U_H_DESC : MSA_3R_DESC_BASE<"max_u.h", umax, MSA128HOpnd>; 2383class MAX_U_W_DESC : MSA_3R_DESC_BASE<"max_u.w", umax, MSA128WOpnd>; 2384class MAX_U_D_DESC : MSA_3R_DESC_BASE<"max_u.d", umax, MSA128DOpnd>; 2385 2386class MAXI_S_B_DESC : MSA_I5_DESC_BASE<"maxi_s.b", smax, vsplati8_simm5, 2387 MSA128BOpnd>; 2388class MAXI_S_H_DESC : MSA_I5_DESC_BASE<"maxi_s.h", smax, vsplati16_simm5, 2389 MSA128HOpnd>; 2390class MAXI_S_W_DESC : MSA_I5_DESC_BASE<"maxi_s.w", smax, vsplati32_simm5, 2391 MSA128WOpnd>; 2392class MAXI_S_D_DESC : MSA_I5_DESC_BASE<"maxi_s.d", smax, vsplati64_simm5, 2393 MSA128DOpnd>; 2394 2395class MAXI_U_B_DESC : MSA_I5_DESC_BASE<"maxi_u.b", umax, vsplati8_uimm5, 2396 MSA128BOpnd>; 2397class MAXI_U_H_DESC : MSA_I5_DESC_BASE<"maxi_u.h", umax, vsplati16_uimm5, 2398 MSA128HOpnd>; 2399class MAXI_U_W_DESC : MSA_I5_DESC_BASE<"maxi_u.w", umax, vsplati32_uimm5, 2400 MSA128WOpnd>; 2401class MAXI_U_D_DESC : MSA_I5_DESC_BASE<"maxi_u.d", umax, vsplati64_uimm5, 2402 MSA128DOpnd>; 2403 2404class MIN_A_B_DESC : MSA_3R_DESC_BASE<"min_a.b", int_mips_min_a_b, MSA128BOpnd>; 2405class MIN_A_H_DESC : MSA_3R_DESC_BASE<"min_a.h", int_mips_min_a_h, MSA128HOpnd>; 2406class MIN_A_W_DESC : MSA_3R_DESC_BASE<"min_a.w", int_mips_min_a_w, MSA128WOpnd>; 2407class MIN_A_D_DESC : MSA_3R_DESC_BASE<"min_a.d", int_mips_min_a_d, MSA128DOpnd>; 2408 2409class MIN_S_B_DESC : MSA_3R_DESC_BASE<"min_s.b", smin, MSA128BOpnd>; 2410class MIN_S_H_DESC : MSA_3R_DESC_BASE<"min_s.h", smin, MSA128HOpnd>; 2411class MIN_S_W_DESC : MSA_3R_DESC_BASE<"min_s.w", smin, MSA128WOpnd>; 2412class MIN_S_D_DESC : MSA_3R_DESC_BASE<"min_s.d", smin, MSA128DOpnd>; 2413 2414class MIN_U_B_DESC : MSA_3R_DESC_BASE<"min_u.b", umin, MSA128BOpnd>; 2415class MIN_U_H_DESC : MSA_3R_DESC_BASE<"min_u.h", umin, MSA128HOpnd>; 2416class MIN_U_W_DESC : MSA_3R_DESC_BASE<"min_u.w", umin, MSA128WOpnd>; 2417class MIN_U_D_DESC : MSA_3R_DESC_BASE<"min_u.d", umin, MSA128DOpnd>; 2418 2419class MINI_S_B_DESC : MSA_I5_DESC_BASE<"mini_s.b", smin, vsplati8_simm5, 2420 MSA128BOpnd>; 2421class MINI_S_H_DESC : MSA_I5_DESC_BASE<"mini_s.h", smin, vsplati16_simm5, 2422 MSA128HOpnd>; 2423class MINI_S_W_DESC : MSA_I5_DESC_BASE<"mini_s.w", smin, vsplati32_simm5, 2424 MSA128WOpnd>; 2425class MINI_S_D_DESC : MSA_I5_DESC_BASE<"mini_s.d", smin, vsplati64_simm5, 2426 MSA128DOpnd>; 2427 2428class MINI_U_B_DESC : MSA_I5_DESC_BASE<"mini_u.b", umin, vsplati8_uimm5, 2429 MSA128BOpnd>; 2430class MINI_U_H_DESC : MSA_I5_DESC_BASE<"mini_u.h", umin, vsplati16_uimm5, 2431 MSA128HOpnd>; 2432class MINI_U_W_DESC : MSA_I5_DESC_BASE<"mini_u.w", umin, vsplati32_uimm5, 2433 MSA128WOpnd>; 2434class MINI_U_D_DESC : MSA_I5_DESC_BASE<"mini_u.d", umin, vsplati64_uimm5, 2435 MSA128DOpnd>; 2436 2437class MOD_S_B_DESC : MSA_3R_DESC_BASE<"mod_s.b", srem, MSA128BOpnd>; 2438class MOD_S_H_DESC : MSA_3R_DESC_BASE<"mod_s.h", srem, MSA128HOpnd>; 2439class MOD_S_W_DESC : MSA_3R_DESC_BASE<"mod_s.w", srem, MSA128WOpnd>; 2440class MOD_S_D_DESC : MSA_3R_DESC_BASE<"mod_s.d", srem, MSA128DOpnd>; 2441 2442class MOD_U_B_DESC : MSA_3R_DESC_BASE<"mod_u.b", urem, MSA128BOpnd>; 2443class MOD_U_H_DESC : MSA_3R_DESC_BASE<"mod_u.h", urem, MSA128HOpnd>; 2444class MOD_U_W_DESC : MSA_3R_DESC_BASE<"mod_u.w", urem, MSA128WOpnd>; 2445class MOD_U_D_DESC : MSA_3R_DESC_BASE<"mod_u.d", urem, MSA128DOpnd>; 2446 2447class MOVE_V_DESC { 2448 dag OutOperandList = (outs MSA128BOpnd:$wd); 2449 dag InOperandList = (ins MSA128BOpnd:$ws); 2450 string AsmString = "move.v\t$wd, $ws"; 2451 list<dag> Pattern = []; 2452 InstrItinClass Itinerary = NoItinerary; 2453 bit isMoveReg = 1; 2454} 2455 2456class MSUB_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"msub_q.h", int_mips_msub_q_h, 2457 MSA128HOpnd>; 2458class MSUB_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"msub_q.w", int_mips_msub_q_w, 2459 MSA128WOpnd>; 2460 2461class MSUBR_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"msubr_q.h", int_mips_msubr_q_h, 2462 MSA128HOpnd>; 2463class MSUBR_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"msubr_q.w", int_mips_msubr_q_w, 2464 MSA128WOpnd>; 2465 2466class MSUBV_B_DESC : MSA_3R_4R_DESC_BASE<"msubv.b", mulsub, MSA128BOpnd>; 2467class MSUBV_H_DESC : MSA_3R_4R_DESC_BASE<"msubv.h", mulsub, MSA128HOpnd>; 2468class MSUBV_W_DESC : MSA_3R_4R_DESC_BASE<"msubv.w", mulsub, MSA128WOpnd>; 2469class MSUBV_D_DESC : MSA_3R_4R_DESC_BASE<"msubv.d", mulsub, MSA128DOpnd>; 2470 2471class MUL_Q_H_DESC : MSA_3RF_DESC_BASE<"mul_q.h", int_mips_mul_q_h, 2472 MSA128HOpnd>; 2473class MUL_Q_W_DESC : MSA_3RF_DESC_BASE<"mul_q.w", int_mips_mul_q_w, 2474 MSA128WOpnd>; 2475 2476class MULR_Q_H_DESC : MSA_3RF_DESC_BASE<"mulr_q.h", int_mips_mulr_q_h, 2477 MSA128HOpnd>; 2478class MULR_Q_W_DESC : MSA_3RF_DESC_BASE<"mulr_q.w", int_mips_mulr_q_w, 2479 MSA128WOpnd>; 2480 2481class MULV_B_DESC : MSA_3R_DESC_BASE<"mulv.b", mul, MSA128BOpnd>; 2482class MULV_H_DESC : MSA_3R_DESC_BASE<"mulv.h", mul, MSA128HOpnd>; 2483class MULV_W_DESC : MSA_3R_DESC_BASE<"mulv.w", mul, MSA128WOpnd>; 2484class MULV_D_DESC : MSA_3R_DESC_BASE<"mulv.d", mul, MSA128DOpnd>; 2485 2486class NLOC_B_DESC : MSA_2R_DESC_BASE<"nloc.b", int_mips_nloc_b, MSA128BOpnd>; 2487class NLOC_H_DESC : MSA_2R_DESC_BASE<"nloc.h", int_mips_nloc_h, MSA128HOpnd>; 2488class NLOC_W_DESC : MSA_2R_DESC_BASE<"nloc.w", int_mips_nloc_w, MSA128WOpnd>; 2489class NLOC_D_DESC : MSA_2R_DESC_BASE<"nloc.d", int_mips_nloc_d, MSA128DOpnd>; 2490 2491class NLZC_B_DESC : MSA_2R_DESC_BASE<"nlzc.b", ctlz, MSA128BOpnd>; 2492class NLZC_H_DESC : MSA_2R_DESC_BASE<"nlzc.h", ctlz, MSA128HOpnd>; 2493class NLZC_W_DESC : MSA_2R_DESC_BASE<"nlzc.w", ctlz, MSA128WOpnd>; 2494class NLZC_D_DESC : MSA_2R_DESC_BASE<"nlzc.d", ctlz, MSA128DOpnd>; 2495 2496class NOR_V_DESC : MSA_VEC_DESC_BASE<"nor.v", MipsVNOR, MSA128BOpnd>; 2497class NOR_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<MipsVNOR, MSA128HOpnd>; 2498class NOR_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<MipsVNOR, MSA128WOpnd>; 2499class NOR_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<MipsVNOR, MSA128DOpnd>; 2500 2501class NORI_B_DESC : MSA_I8_DESC_BASE<"nori.b", MipsVNOR, vsplati8_uimm8, 2502 MSA128BOpnd>; 2503 2504class OR_V_DESC : MSA_VEC_DESC_BASE<"or.v", or, MSA128BOpnd>; 2505class OR_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<or, MSA128HOpnd>; 2506class OR_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<or, MSA128WOpnd>; 2507class OR_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<or, MSA128DOpnd>; 2508 2509class ORI_B_DESC : MSA_I8_DESC_BASE<"ori.b", or, vsplati8_uimm8, MSA128BOpnd>; 2510 2511class PCKEV_B_DESC : MSA_3R_DESC_BASE<"pckev.b", MipsPCKEV, MSA128BOpnd>; 2512class PCKEV_H_DESC : MSA_3R_DESC_BASE<"pckev.h", MipsPCKEV, MSA128HOpnd>; 2513class PCKEV_W_DESC : MSA_3R_DESC_BASE<"pckev.w", MipsPCKEV, MSA128WOpnd>; 2514class PCKEV_D_DESC : MSA_3R_DESC_BASE<"pckev.d", MipsPCKEV, MSA128DOpnd>; 2515 2516class PCKOD_B_DESC : MSA_3R_DESC_BASE<"pckod.b", MipsPCKOD, MSA128BOpnd>; 2517class PCKOD_H_DESC : MSA_3R_DESC_BASE<"pckod.h", MipsPCKOD, MSA128HOpnd>; 2518class PCKOD_W_DESC : MSA_3R_DESC_BASE<"pckod.w", MipsPCKOD, MSA128WOpnd>; 2519class PCKOD_D_DESC : MSA_3R_DESC_BASE<"pckod.d", MipsPCKOD, MSA128DOpnd>; 2520 2521class PCNT_B_DESC : MSA_2R_DESC_BASE<"pcnt.b", ctpop, MSA128BOpnd>; 2522class PCNT_H_DESC : MSA_2R_DESC_BASE<"pcnt.h", ctpop, MSA128HOpnd>; 2523class PCNT_W_DESC : MSA_2R_DESC_BASE<"pcnt.w", ctpop, MSA128WOpnd>; 2524class PCNT_D_DESC : MSA_2R_DESC_BASE<"pcnt.d", ctpop, MSA128DOpnd>; 2525 2526class SAT_S_B_DESC : MSA_BIT_X_DESC_BASE<"sat_s.b", int_mips_sat_s_b, uimm3, 2527 timmZExt3, MSA128BOpnd>; 2528class SAT_S_H_DESC : MSA_BIT_X_DESC_BASE<"sat_s.h", int_mips_sat_s_h, uimm4, 2529 timmZExt4, MSA128HOpnd>; 2530class SAT_S_W_DESC : MSA_BIT_X_DESC_BASE<"sat_s.w", int_mips_sat_s_w, uimm5, 2531 timmZExt5, MSA128WOpnd>; 2532class SAT_S_D_DESC : MSA_BIT_X_DESC_BASE<"sat_s.d", int_mips_sat_s_d, uimm6, 2533 timmZExt6, MSA128DOpnd>; 2534 2535class SAT_U_B_DESC : MSA_BIT_X_DESC_BASE<"sat_u.b", int_mips_sat_u_b, uimm3, 2536 timmZExt3, MSA128BOpnd>; 2537class SAT_U_H_DESC : MSA_BIT_X_DESC_BASE<"sat_u.h", int_mips_sat_u_h, uimm4, 2538 timmZExt4, MSA128HOpnd>; 2539class SAT_U_W_DESC : MSA_BIT_X_DESC_BASE<"sat_u.w", int_mips_sat_u_w, uimm5, 2540 timmZExt5, MSA128WOpnd>; 2541class SAT_U_D_DESC : MSA_BIT_X_DESC_BASE<"sat_u.d", int_mips_sat_u_d, uimm6, 2542 timmZExt6, MSA128DOpnd>; 2543 2544class SHF_B_DESC : MSA_I8_SHF_DESC_BASE<"shf.b", MSA128BOpnd>; 2545class SHF_H_DESC : MSA_I8_SHF_DESC_BASE<"shf.h", MSA128HOpnd>; 2546class SHF_W_DESC : MSA_I8_SHF_DESC_BASE<"shf.w", MSA128WOpnd>; 2547 2548class SLD_B_DESC : MSA_3R_SLD_DESC_BASE<"sld.b", int_mips_sld_b, MSA128BOpnd>; 2549class SLD_H_DESC : MSA_3R_SLD_DESC_BASE<"sld.h", int_mips_sld_h, MSA128HOpnd>; 2550class SLD_W_DESC : MSA_3R_SLD_DESC_BASE<"sld.w", int_mips_sld_w, MSA128WOpnd>; 2551class SLD_D_DESC : MSA_3R_SLD_DESC_BASE<"sld.d", int_mips_sld_d, MSA128DOpnd>; 2552 2553class SLDI_B_DESC : MSA_ELM_SLD_DESC_BASE<"sldi.b", int_mips_sldi_b, 2554 MSA128BOpnd, MSA128BOpnd, uimm4, 2555 timmZExt4>; 2556class SLDI_H_DESC : MSA_ELM_SLD_DESC_BASE<"sldi.h", int_mips_sldi_h, 2557 MSA128HOpnd, MSA128HOpnd, uimm3, 2558 timmZExt3>; 2559class SLDI_W_DESC : MSA_ELM_SLD_DESC_BASE<"sldi.w", int_mips_sldi_w, 2560 MSA128WOpnd, MSA128WOpnd, uimm2, 2561 timmZExt2>; 2562class SLDI_D_DESC : MSA_ELM_SLD_DESC_BASE<"sldi.d", int_mips_sldi_d, 2563 MSA128DOpnd, MSA128DOpnd, uimm1, 2564 timmZExt1>; 2565 2566class SLL_B_DESC : MSA_3R_DESC_BASE<"sll.b", shl, MSA128BOpnd>; 2567class SLL_H_DESC : MSA_3R_DESC_BASE<"sll.h", shl, MSA128HOpnd>; 2568class SLL_W_DESC : MSA_3R_DESC_BASE<"sll.w", shl, MSA128WOpnd>; 2569class SLL_D_DESC : MSA_3R_DESC_BASE<"sll.d", shl, MSA128DOpnd>; 2570 2571class SLLI_B_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.b", shl, vsplati8_uimm3, 2572 MSA128BOpnd>; 2573class SLLI_H_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.h", shl, vsplati16_uimm4, 2574 MSA128HOpnd>; 2575class SLLI_W_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.w", shl, vsplati32_uimm5, 2576 MSA128WOpnd>; 2577class SLLI_D_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.d", shl, vsplati64_uimm6, 2578 MSA128DOpnd>; 2579 2580class SPLAT_B_DESC : MSA_3R_SPLAT_DESC_BASE<"splat.b", vsplati8_elt, 2581 MSA128BOpnd>; 2582class SPLAT_H_DESC : MSA_3R_SPLAT_DESC_BASE<"splat.h", vsplati16_elt, 2583 MSA128HOpnd>; 2584class SPLAT_W_DESC : MSA_3R_SPLAT_DESC_BASE<"splat.w", vsplati32_elt, 2585 MSA128WOpnd>; 2586class SPLAT_D_DESC : MSA_3R_SPLAT_DESC_BASE<"splat.d", vsplati64_elt, 2587 MSA128DOpnd>; 2588 2589class SPLATI_B_DESC : MSA_ELM_SPLAT_DESC_BASE<"splati.b", vsplati8_uimm4, 2590 MSA128BOpnd>; 2591class SPLATI_H_DESC : MSA_ELM_SPLAT_DESC_BASE<"splati.h", vsplati16_uimm3, 2592 MSA128HOpnd>; 2593class SPLATI_W_DESC : MSA_ELM_SPLAT_DESC_BASE<"splati.w", vsplati32_uimm2, 2594 MSA128WOpnd>; 2595class SPLATI_D_DESC : MSA_ELM_SPLAT_DESC_BASE<"splati.d", vsplati64_uimm1, 2596 MSA128DOpnd>; 2597 2598class SRA_B_DESC : MSA_3R_DESC_BASE<"sra.b", sra, MSA128BOpnd>; 2599class SRA_H_DESC : MSA_3R_DESC_BASE<"sra.h", sra, MSA128HOpnd>; 2600class SRA_W_DESC : MSA_3R_DESC_BASE<"sra.w", sra, MSA128WOpnd>; 2601class SRA_D_DESC : MSA_3R_DESC_BASE<"sra.d", sra, MSA128DOpnd>; 2602 2603class SRAI_B_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.b", sra, vsplati8_uimm3, 2604 MSA128BOpnd>; 2605class SRAI_H_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.h", sra, vsplati16_uimm4, 2606 MSA128HOpnd>; 2607class SRAI_W_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.w", sra, vsplati32_uimm5, 2608 MSA128WOpnd>; 2609class SRAI_D_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.d", sra, vsplati64_uimm6, 2610 MSA128DOpnd>; 2611 2612class SRAR_B_DESC : MSA_3R_DESC_BASE<"srar.b", int_mips_srar_b, MSA128BOpnd>; 2613class SRAR_H_DESC : MSA_3R_DESC_BASE<"srar.h", int_mips_srar_h, MSA128HOpnd>; 2614class SRAR_W_DESC : MSA_3R_DESC_BASE<"srar.w", int_mips_srar_w, MSA128WOpnd>; 2615class SRAR_D_DESC : MSA_3R_DESC_BASE<"srar.d", int_mips_srar_d, MSA128DOpnd>; 2616 2617class SRARI_B_DESC : MSA_BIT_X_DESC_BASE<"srari.b", int_mips_srari_b, uimm3, 2618 timmZExt3, MSA128BOpnd>; 2619class SRARI_H_DESC : MSA_BIT_X_DESC_BASE<"srari.h", int_mips_srari_h, uimm4, 2620 timmZExt4, MSA128HOpnd>; 2621class SRARI_W_DESC : MSA_BIT_X_DESC_BASE<"srari.w", int_mips_srari_w, uimm5, 2622 timmZExt5, MSA128WOpnd>; 2623class SRARI_D_DESC : MSA_BIT_X_DESC_BASE<"srari.d", int_mips_srari_d, uimm6, 2624 timmZExt6, MSA128DOpnd>; 2625 2626class SRL_B_DESC : MSA_3R_DESC_BASE<"srl.b", srl, MSA128BOpnd>; 2627class SRL_H_DESC : MSA_3R_DESC_BASE<"srl.h", srl, MSA128HOpnd>; 2628class SRL_W_DESC : MSA_3R_DESC_BASE<"srl.w", srl, MSA128WOpnd>; 2629class SRL_D_DESC : MSA_3R_DESC_BASE<"srl.d", srl, MSA128DOpnd>; 2630 2631class SRLI_B_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.b", srl, vsplati8_uimm3, 2632 MSA128BOpnd>; 2633class SRLI_H_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.h", srl, vsplati16_uimm4, 2634 MSA128HOpnd>; 2635class SRLI_W_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.w", srl, vsplati32_uimm5, 2636 MSA128WOpnd>; 2637class SRLI_D_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.d", srl, vsplati64_uimm6, 2638 MSA128DOpnd>; 2639 2640class SRLR_B_DESC : MSA_3R_DESC_BASE<"srlr.b", int_mips_srlr_b, MSA128BOpnd>; 2641class SRLR_H_DESC : MSA_3R_DESC_BASE<"srlr.h", int_mips_srlr_h, MSA128HOpnd>; 2642class SRLR_W_DESC : MSA_3R_DESC_BASE<"srlr.w", int_mips_srlr_w, MSA128WOpnd>; 2643class SRLR_D_DESC : MSA_3R_DESC_BASE<"srlr.d", int_mips_srlr_d, MSA128DOpnd>; 2644 2645class SRLRI_B_DESC : MSA_BIT_X_DESC_BASE<"srlri.b", int_mips_srlri_b, uimm3, 2646 timmZExt3, MSA128BOpnd>; 2647class SRLRI_H_DESC : MSA_BIT_X_DESC_BASE<"srlri.h", int_mips_srlri_h, uimm4, 2648 timmZExt4, MSA128HOpnd>; 2649class SRLRI_W_DESC : MSA_BIT_X_DESC_BASE<"srlri.w", int_mips_srlri_w, uimm5, 2650 timmZExt5, MSA128WOpnd>; 2651class SRLRI_D_DESC : MSA_BIT_X_DESC_BASE<"srlri.d", int_mips_srlri_d, uimm6, 2652 timmZExt6, MSA128DOpnd>; 2653 2654class ST_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 2655 ValueType TyNode, RegisterOperand ROWD, 2656 Operand MemOpnd, ComplexPattern Addr = addrimm10, 2657 InstrItinClass itin = NoItinerary> { 2658 dag OutOperandList = (outs); 2659 dag InOperandList = (ins ROWD:$wd, MemOpnd:$addr); 2660 string AsmString = !strconcat(instr_asm, "\t$wd, $addr"); 2661 list<dag> Pattern = [(OpNode (TyNode ROWD:$wd), Addr:$addr)]; 2662 InstrItinClass Itinerary = itin; 2663 string DecoderMethod = "DecodeMSA128Mem"; 2664} 2665 2666class ST_B_DESC : ST_DESC_BASE<"st.b", store, v16i8, MSA128BOpnd, mem_simm10>; 2667class ST_H_DESC : ST_DESC_BASE<"st.h", store, v8i16, MSA128HOpnd, 2668 mem_simm10_lsl1, addrimm10lsl1>; 2669class ST_W_DESC : ST_DESC_BASE<"st.w", store, v4i32, MSA128WOpnd, 2670 mem_simm10_lsl2, addrimm10lsl2>; 2671class ST_D_DESC : ST_DESC_BASE<"st.d", store, v2i64, MSA128DOpnd, 2672 mem_simm10_lsl3, addrimm10lsl3>; 2673 2674class SUBS_S_B_DESC : MSA_3R_DESC_BASE<"subs_s.b", int_mips_subs_s_b, 2675 MSA128BOpnd>; 2676class SUBS_S_H_DESC : MSA_3R_DESC_BASE<"subs_s.h", int_mips_subs_s_h, 2677 MSA128HOpnd>; 2678class SUBS_S_W_DESC : MSA_3R_DESC_BASE<"subs_s.w", int_mips_subs_s_w, 2679 MSA128WOpnd>; 2680class SUBS_S_D_DESC : MSA_3R_DESC_BASE<"subs_s.d", int_mips_subs_s_d, 2681 MSA128DOpnd>; 2682 2683class SUBS_U_B_DESC : MSA_3R_DESC_BASE<"subs_u.b", int_mips_subs_u_b, 2684 MSA128BOpnd>; 2685class SUBS_U_H_DESC : MSA_3R_DESC_BASE<"subs_u.h", int_mips_subs_u_h, 2686 MSA128HOpnd>; 2687class SUBS_U_W_DESC : MSA_3R_DESC_BASE<"subs_u.w", int_mips_subs_u_w, 2688 MSA128WOpnd>; 2689class SUBS_U_D_DESC : MSA_3R_DESC_BASE<"subs_u.d", int_mips_subs_u_d, 2690 MSA128DOpnd>; 2691 2692class SUBSUS_U_B_DESC : MSA_3R_DESC_BASE<"subsus_u.b", int_mips_subsus_u_b, 2693 MSA128BOpnd>; 2694class SUBSUS_U_H_DESC : MSA_3R_DESC_BASE<"subsus_u.h", int_mips_subsus_u_h, 2695 MSA128HOpnd>; 2696class SUBSUS_U_W_DESC : MSA_3R_DESC_BASE<"subsus_u.w", int_mips_subsus_u_w, 2697 MSA128WOpnd>; 2698class SUBSUS_U_D_DESC : MSA_3R_DESC_BASE<"subsus_u.d", int_mips_subsus_u_d, 2699 MSA128DOpnd>; 2700 2701class SUBSUU_S_B_DESC : MSA_3R_DESC_BASE<"subsuu_s.b", int_mips_subsuu_s_b, 2702 MSA128BOpnd>; 2703class SUBSUU_S_H_DESC : MSA_3R_DESC_BASE<"subsuu_s.h", int_mips_subsuu_s_h, 2704 MSA128HOpnd>; 2705class SUBSUU_S_W_DESC : MSA_3R_DESC_BASE<"subsuu_s.w", int_mips_subsuu_s_w, 2706 MSA128WOpnd>; 2707class SUBSUU_S_D_DESC : MSA_3R_DESC_BASE<"subsuu_s.d", int_mips_subsuu_s_d, 2708 MSA128DOpnd>; 2709 2710class SUBV_B_DESC : MSA_3R_DESC_BASE<"subv.b", sub, MSA128BOpnd>; 2711class SUBV_H_DESC : MSA_3R_DESC_BASE<"subv.h", sub, MSA128HOpnd>; 2712class SUBV_W_DESC : MSA_3R_DESC_BASE<"subv.w", sub, MSA128WOpnd>; 2713class SUBV_D_DESC : MSA_3R_DESC_BASE<"subv.d", sub, MSA128DOpnd>; 2714 2715class SUBVI_B_DESC : MSA_I5_DESC_BASE<"subvi.b", sub, vsplati8_uimm5, 2716 MSA128BOpnd>; 2717class SUBVI_H_DESC : MSA_I5_DESC_BASE<"subvi.h", sub, vsplati16_uimm5, 2718 MSA128HOpnd>; 2719class SUBVI_W_DESC : MSA_I5_DESC_BASE<"subvi.w", sub, vsplati32_uimm5, 2720 MSA128WOpnd>; 2721class SUBVI_D_DESC : MSA_I5_DESC_BASE<"subvi.d", sub, vsplati64_uimm5, 2722 MSA128DOpnd>; 2723 2724class VSHF_B_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.b", MSA128BOpnd>; 2725class VSHF_H_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.h", MSA128HOpnd>; 2726class VSHF_W_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.w", MSA128WOpnd>; 2727class VSHF_D_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.d", MSA128DOpnd>; 2728 2729class XOR_V_DESC : MSA_VEC_DESC_BASE<"xor.v", xor, MSA128BOpnd>; 2730class XOR_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<xor, MSA128HOpnd>; 2731class XOR_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<xor, MSA128WOpnd>; 2732class XOR_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<xor, MSA128DOpnd>; 2733 2734class XORI_B_DESC : MSA_I8_DESC_BASE<"xori.b", xor, vsplati8_uimm8, 2735 MSA128BOpnd>; 2736 2737// Instruction defs. 2738def ADD_A_B : ADD_A_B_ENC, ADD_A_B_DESC; 2739def ADD_A_H : ADD_A_H_ENC, ADD_A_H_DESC; 2740def ADD_A_W : ADD_A_W_ENC, ADD_A_W_DESC; 2741def ADD_A_D : ADD_A_D_ENC, ADD_A_D_DESC; 2742 2743def ADDS_A_B : ADDS_A_B_ENC, ADDS_A_B_DESC; 2744def ADDS_A_H : ADDS_A_H_ENC, ADDS_A_H_DESC; 2745def ADDS_A_W : ADDS_A_W_ENC, ADDS_A_W_DESC; 2746def ADDS_A_D : ADDS_A_D_ENC, ADDS_A_D_DESC; 2747 2748def ADDS_S_B : ADDS_S_B_ENC, ADDS_S_B_DESC; 2749def ADDS_S_H : ADDS_S_H_ENC, ADDS_S_H_DESC; 2750def ADDS_S_W : ADDS_S_W_ENC, ADDS_S_W_DESC; 2751def ADDS_S_D : ADDS_S_D_ENC, ADDS_S_D_DESC; 2752 2753def ADDS_U_B : ADDS_U_B_ENC, ADDS_U_B_DESC; 2754def ADDS_U_H : ADDS_U_H_ENC, ADDS_U_H_DESC; 2755def ADDS_U_W : ADDS_U_W_ENC, ADDS_U_W_DESC; 2756def ADDS_U_D : ADDS_U_D_ENC, ADDS_U_D_DESC; 2757 2758def ADDV_B : ADDV_B_ENC, ADDV_B_DESC; 2759def ADDV_H : ADDV_H_ENC, ADDV_H_DESC; 2760def ADDV_W : ADDV_W_ENC, ADDV_W_DESC; 2761def ADDV_D : ADDV_D_ENC, ADDV_D_DESC; 2762 2763def ADDVI_B : ADDVI_B_ENC, ADDVI_B_DESC; 2764def ADDVI_H : ADDVI_H_ENC, ADDVI_H_DESC; 2765def ADDVI_W : ADDVI_W_ENC, ADDVI_W_DESC; 2766def ADDVI_D : ADDVI_D_ENC, ADDVI_D_DESC; 2767 2768def AND_V : AND_V_ENC, AND_V_DESC; 2769def AND_V_H_PSEUDO : AND_V_H_PSEUDO_DESC, 2770 PseudoInstExpansion<(AND_V MSA128BOpnd:$wd, 2771 MSA128BOpnd:$ws, 2772 MSA128BOpnd:$wt)>; 2773def AND_V_W_PSEUDO : AND_V_W_PSEUDO_DESC, 2774 PseudoInstExpansion<(AND_V MSA128BOpnd:$wd, 2775 MSA128BOpnd:$ws, 2776 MSA128BOpnd:$wt)>; 2777def AND_V_D_PSEUDO : AND_V_D_PSEUDO_DESC, 2778 PseudoInstExpansion<(AND_V MSA128BOpnd:$wd, 2779 MSA128BOpnd:$ws, 2780 MSA128BOpnd:$wt)>; 2781 2782def ANDI_B : ANDI_B_ENC, ANDI_B_DESC; 2783 2784def ASUB_S_B : ASUB_S_B_ENC, ASUB_S_B_DESC; 2785def ASUB_S_H : ASUB_S_H_ENC, ASUB_S_H_DESC; 2786def ASUB_S_W : ASUB_S_W_ENC, ASUB_S_W_DESC; 2787def ASUB_S_D : ASUB_S_D_ENC, ASUB_S_D_DESC; 2788 2789def ASUB_U_B : ASUB_U_B_ENC, ASUB_U_B_DESC; 2790def ASUB_U_H : ASUB_U_H_ENC, ASUB_U_H_DESC; 2791def ASUB_U_W : ASUB_U_W_ENC, ASUB_U_W_DESC; 2792def ASUB_U_D : ASUB_U_D_ENC, ASUB_U_D_DESC; 2793 2794def AVE_S_B : AVE_S_B_ENC, AVE_S_B_DESC; 2795def AVE_S_H : AVE_S_H_ENC, AVE_S_H_DESC; 2796def AVE_S_W : AVE_S_W_ENC, AVE_S_W_DESC; 2797def AVE_S_D : AVE_S_D_ENC, AVE_S_D_DESC; 2798 2799def AVE_U_B : AVE_U_B_ENC, AVE_U_B_DESC; 2800def AVE_U_H : AVE_U_H_ENC, AVE_U_H_DESC; 2801def AVE_U_W : AVE_U_W_ENC, AVE_U_W_DESC; 2802def AVE_U_D : AVE_U_D_ENC, AVE_U_D_DESC; 2803 2804def AVER_S_B : AVER_S_B_ENC, AVER_S_B_DESC; 2805def AVER_S_H : AVER_S_H_ENC, AVER_S_H_DESC; 2806def AVER_S_W : AVER_S_W_ENC, AVER_S_W_DESC; 2807def AVER_S_D : AVER_S_D_ENC, AVER_S_D_DESC; 2808 2809def AVER_U_B : AVER_U_B_ENC, AVER_U_B_DESC; 2810def AVER_U_H : AVER_U_H_ENC, AVER_U_H_DESC; 2811def AVER_U_W : AVER_U_W_ENC, AVER_U_W_DESC; 2812def AVER_U_D : AVER_U_D_ENC, AVER_U_D_DESC; 2813 2814def BCLR_B : BCLR_B_ENC, BCLR_B_DESC; 2815def BCLR_H : BCLR_H_ENC, BCLR_H_DESC; 2816def BCLR_W : BCLR_W_ENC, BCLR_W_DESC; 2817def BCLR_D : BCLR_D_ENC, BCLR_D_DESC; 2818 2819def BCLRI_B : BCLRI_B_ENC, BCLRI_B_DESC; 2820def BCLRI_H : BCLRI_H_ENC, BCLRI_H_DESC; 2821def BCLRI_W : BCLRI_W_ENC, BCLRI_W_DESC; 2822def BCLRI_D : BCLRI_D_ENC, BCLRI_D_DESC; 2823 2824def BINSL_B : BINSL_B_ENC, BINSL_B_DESC; 2825def BINSL_H : BINSL_H_ENC, BINSL_H_DESC; 2826def BINSL_W : BINSL_W_ENC, BINSL_W_DESC; 2827def BINSL_D : BINSL_D_ENC, BINSL_D_DESC; 2828 2829def BINSLI_B : BINSLI_B_ENC, BINSLI_B_DESC; 2830def BINSLI_H : BINSLI_H_ENC, BINSLI_H_DESC; 2831def BINSLI_W : BINSLI_W_ENC, BINSLI_W_DESC; 2832def BINSLI_D : BINSLI_D_ENC, BINSLI_D_DESC; 2833 2834def BINSR_B : BINSR_B_ENC, BINSR_B_DESC; 2835def BINSR_H : BINSR_H_ENC, BINSR_H_DESC; 2836def BINSR_W : BINSR_W_ENC, BINSR_W_DESC; 2837def BINSR_D : BINSR_D_ENC, BINSR_D_DESC; 2838 2839def BINSRI_B : BINSRI_B_ENC, BINSRI_B_DESC; 2840def BINSRI_H : BINSRI_H_ENC, BINSRI_H_DESC; 2841def BINSRI_W : BINSRI_W_ENC, BINSRI_W_DESC; 2842def BINSRI_D : BINSRI_D_ENC, BINSRI_D_DESC; 2843 2844def BMNZ_V : BMNZ_V_ENC, BMNZ_V_DESC; 2845 2846def BMNZI_B : BMNZI_B_ENC, BMNZI_B_DESC; 2847 2848def BMZ_V : BMZ_V_ENC, BMZ_V_DESC; 2849 2850def BMZI_B : BMZI_B_ENC, BMZI_B_DESC; 2851 2852def BNEG_B : BNEG_B_ENC, BNEG_B_DESC; 2853def BNEG_H : BNEG_H_ENC, BNEG_H_DESC; 2854def BNEG_W : BNEG_W_ENC, BNEG_W_DESC; 2855def BNEG_D : BNEG_D_ENC, BNEG_D_DESC; 2856 2857def BNEGI_B : BNEGI_B_ENC, BNEGI_B_DESC; 2858def BNEGI_H : BNEGI_H_ENC, BNEGI_H_DESC; 2859def BNEGI_W : BNEGI_W_ENC, BNEGI_W_DESC; 2860def BNEGI_D : BNEGI_D_ENC, BNEGI_D_DESC; 2861 2862def BNZ_B : BNZ_B_ENC, BNZ_B_DESC; 2863def BNZ_H : BNZ_H_ENC, BNZ_H_DESC; 2864def BNZ_W : BNZ_W_ENC, BNZ_W_DESC; 2865def BNZ_D : BNZ_D_ENC, BNZ_D_DESC; 2866 2867def BNZ_V : BNZ_V_ENC, BNZ_V_DESC; 2868 2869def BSEL_V : BSEL_V_ENC, BSEL_V_DESC; 2870 2871class MSA_BSEL_PSEUDO_BASE<RegisterOperand RO, ValueType Ty> : 2872 MSAPseudo<(outs RO:$wd), (ins RO:$wd_in, RO:$ws, RO:$wt), 2873 [(set RO:$wd, (Ty (vselect RO:$wd_in, RO:$wt, RO:$ws)))]>, 2874 // Note that vselect and BSEL_V treat the condition operand the opposite way 2875 // from each other. 2876 // (vselect cond, if_set, if_clear) 2877 // (BSEL_V cond, if_clear, if_set) 2878 PseudoInstExpansion<(BSEL_V MSA128BOpnd:$wd, MSA128BOpnd:$wd_in, 2879 MSA128BOpnd:$ws, MSA128BOpnd:$wt)> { 2880 let Constraints = "$wd_in = $wd"; 2881} 2882 2883def BSEL_H_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128HOpnd, v8i16>; 2884def BSEL_W_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128WOpnd, v4i32>; 2885def BSEL_D_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128DOpnd, v2i64>; 2886def BSEL_FW_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128WOpnd, v4f32>; 2887def BSEL_FD_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128DOpnd, v2f64>; 2888 2889def BSELI_B : BSELI_B_ENC, BSELI_B_DESC; 2890 2891def BSET_B : BSET_B_ENC, BSET_B_DESC; 2892def BSET_H : BSET_H_ENC, BSET_H_DESC; 2893def BSET_W : BSET_W_ENC, BSET_W_DESC; 2894def BSET_D : BSET_D_ENC, BSET_D_DESC; 2895 2896def BSETI_B : BSETI_B_ENC, BSETI_B_DESC; 2897def BSETI_H : BSETI_H_ENC, BSETI_H_DESC; 2898def BSETI_W : BSETI_W_ENC, BSETI_W_DESC; 2899def BSETI_D : BSETI_D_ENC, BSETI_D_DESC; 2900 2901def BZ_B : BZ_B_ENC, BZ_B_DESC; 2902def BZ_H : BZ_H_ENC, BZ_H_DESC; 2903def BZ_W : BZ_W_ENC, BZ_W_DESC; 2904def BZ_D : BZ_D_ENC, BZ_D_DESC; 2905 2906def BZ_V : BZ_V_ENC, BZ_V_DESC; 2907 2908def CEQ_B : CEQ_B_ENC, CEQ_B_DESC; 2909def CEQ_H : CEQ_H_ENC, CEQ_H_DESC; 2910def CEQ_W : CEQ_W_ENC, CEQ_W_DESC; 2911def CEQ_D : CEQ_D_ENC, CEQ_D_DESC; 2912 2913def CEQI_B : CEQI_B_ENC, CEQI_B_DESC; 2914def CEQI_H : CEQI_H_ENC, CEQI_H_DESC; 2915def CEQI_W : CEQI_W_ENC, CEQI_W_DESC; 2916def CEQI_D : CEQI_D_ENC, CEQI_D_DESC; 2917 2918def CFCMSA : CFCMSA_ENC, CFCMSA_DESC; 2919 2920def CLE_S_B : CLE_S_B_ENC, CLE_S_B_DESC; 2921def CLE_S_H : CLE_S_H_ENC, CLE_S_H_DESC; 2922def CLE_S_W : CLE_S_W_ENC, CLE_S_W_DESC; 2923def CLE_S_D : CLE_S_D_ENC, CLE_S_D_DESC; 2924 2925def CLE_U_B : CLE_U_B_ENC, CLE_U_B_DESC; 2926def CLE_U_H : CLE_U_H_ENC, CLE_U_H_DESC; 2927def CLE_U_W : CLE_U_W_ENC, CLE_U_W_DESC; 2928def CLE_U_D : CLE_U_D_ENC, CLE_U_D_DESC; 2929 2930def CLEI_S_B : CLEI_S_B_ENC, CLEI_S_B_DESC; 2931def CLEI_S_H : CLEI_S_H_ENC, CLEI_S_H_DESC; 2932def CLEI_S_W : CLEI_S_W_ENC, CLEI_S_W_DESC; 2933def CLEI_S_D : CLEI_S_D_ENC, CLEI_S_D_DESC; 2934 2935def CLEI_U_B : CLEI_U_B_ENC, CLEI_U_B_DESC; 2936def CLEI_U_H : CLEI_U_H_ENC, CLEI_U_H_DESC; 2937def CLEI_U_W : CLEI_U_W_ENC, CLEI_U_W_DESC; 2938def CLEI_U_D : CLEI_U_D_ENC, CLEI_U_D_DESC; 2939 2940def CLT_S_B : CLT_S_B_ENC, CLT_S_B_DESC; 2941def CLT_S_H : CLT_S_H_ENC, CLT_S_H_DESC; 2942def CLT_S_W : CLT_S_W_ENC, CLT_S_W_DESC; 2943def CLT_S_D : CLT_S_D_ENC, CLT_S_D_DESC; 2944 2945def CLT_U_B : CLT_U_B_ENC, CLT_U_B_DESC; 2946def CLT_U_H : CLT_U_H_ENC, CLT_U_H_DESC; 2947def CLT_U_W : CLT_U_W_ENC, CLT_U_W_DESC; 2948def CLT_U_D : CLT_U_D_ENC, CLT_U_D_DESC; 2949 2950def CLTI_S_B : CLTI_S_B_ENC, CLTI_S_B_DESC; 2951def CLTI_S_H : CLTI_S_H_ENC, CLTI_S_H_DESC; 2952def CLTI_S_W : CLTI_S_W_ENC, CLTI_S_W_DESC; 2953def CLTI_S_D : CLTI_S_D_ENC, CLTI_S_D_DESC; 2954 2955def CLTI_U_B : CLTI_U_B_ENC, CLTI_U_B_DESC; 2956def CLTI_U_H : CLTI_U_H_ENC, CLTI_U_H_DESC; 2957def CLTI_U_W : CLTI_U_W_ENC, CLTI_U_W_DESC; 2958def CLTI_U_D : CLTI_U_D_ENC, CLTI_U_D_DESC; 2959 2960def COPY_S_B : COPY_S_B_ENC, COPY_S_B_DESC; 2961def COPY_S_H : COPY_S_H_ENC, COPY_S_H_DESC; 2962def COPY_S_W : COPY_S_W_ENC, COPY_S_W_DESC; 2963def COPY_S_D : COPY_S_D_ENC, COPY_S_D_DESC, ASE_MSA64; 2964 2965def COPY_U_B : COPY_U_B_ENC, COPY_U_B_DESC; 2966def COPY_U_H : COPY_U_H_ENC, COPY_U_H_DESC; 2967def COPY_U_W : COPY_U_W_ENC, COPY_U_W_DESC, ASE_MSA64; 2968 2969def COPY_FW_PSEUDO : COPY_FW_PSEUDO_DESC; 2970def COPY_FD_PSEUDO : COPY_FD_PSEUDO_DESC; 2971 2972def CTCMSA : CTCMSA_ENC, CTCMSA_DESC; 2973 2974def DIV_S_B : DIV_S_B_ENC, DIV_S_B_DESC; 2975def DIV_S_H : DIV_S_H_ENC, DIV_S_H_DESC; 2976def DIV_S_W : DIV_S_W_ENC, DIV_S_W_DESC; 2977def DIV_S_D : DIV_S_D_ENC, DIV_S_D_DESC; 2978 2979def DIV_U_B : DIV_U_B_ENC, DIV_U_B_DESC; 2980def DIV_U_H : DIV_U_H_ENC, DIV_U_H_DESC; 2981def DIV_U_W : DIV_U_W_ENC, DIV_U_W_DESC; 2982def DIV_U_D : DIV_U_D_ENC, DIV_U_D_DESC; 2983 2984def DOTP_S_H : DOTP_S_H_ENC, DOTP_S_H_DESC; 2985def DOTP_S_W : DOTP_S_W_ENC, DOTP_S_W_DESC; 2986def DOTP_S_D : DOTP_S_D_ENC, DOTP_S_D_DESC; 2987 2988def DOTP_U_H : DOTP_U_H_ENC, DOTP_U_H_DESC; 2989def DOTP_U_W : DOTP_U_W_ENC, DOTP_U_W_DESC; 2990def DOTP_U_D : DOTP_U_D_ENC, DOTP_U_D_DESC; 2991 2992def DPADD_S_H : DPADD_S_H_ENC, DPADD_S_H_DESC; 2993def DPADD_S_W : DPADD_S_W_ENC, DPADD_S_W_DESC; 2994def DPADD_S_D : DPADD_S_D_ENC, DPADD_S_D_DESC; 2995 2996def DPADD_U_H : DPADD_U_H_ENC, DPADD_U_H_DESC; 2997def DPADD_U_W : DPADD_U_W_ENC, DPADD_U_W_DESC; 2998def DPADD_U_D : DPADD_U_D_ENC, DPADD_U_D_DESC; 2999 3000def DPSUB_S_H : DPSUB_S_H_ENC, DPSUB_S_H_DESC; 3001def DPSUB_S_W : DPSUB_S_W_ENC, DPSUB_S_W_DESC; 3002def DPSUB_S_D : DPSUB_S_D_ENC, DPSUB_S_D_DESC; 3003 3004def DPSUB_U_H : DPSUB_U_H_ENC, DPSUB_U_H_DESC; 3005def DPSUB_U_W : DPSUB_U_W_ENC, DPSUB_U_W_DESC; 3006def DPSUB_U_D : DPSUB_U_D_ENC, DPSUB_U_D_DESC; 3007 3008def FADD_W : FADD_W_ENC, FADD_W_DESC; 3009def FADD_D : FADD_D_ENC, FADD_D_DESC; 3010 3011def FCAF_W : FCAF_W_ENC, FCAF_W_DESC; 3012def FCAF_D : FCAF_D_ENC, FCAF_D_DESC; 3013 3014def FCEQ_W : FCEQ_W_ENC, FCEQ_W_DESC; 3015def FCEQ_D : FCEQ_D_ENC, FCEQ_D_DESC; 3016 3017def FCLE_W : FCLE_W_ENC, FCLE_W_DESC; 3018def FCLE_D : FCLE_D_ENC, FCLE_D_DESC; 3019 3020def FCLT_W : FCLT_W_ENC, FCLT_W_DESC; 3021def FCLT_D : FCLT_D_ENC, FCLT_D_DESC; 3022 3023def FCLASS_W : FCLASS_W_ENC, FCLASS_W_DESC; 3024def FCLASS_D : FCLASS_D_ENC, FCLASS_D_DESC; 3025 3026def FCNE_W : FCNE_W_ENC, FCNE_W_DESC; 3027def FCNE_D : FCNE_D_ENC, FCNE_D_DESC; 3028 3029def FCOR_W : FCOR_W_ENC, FCOR_W_DESC; 3030def FCOR_D : FCOR_D_ENC, FCOR_D_DESC; 3031 3032def FCUEQ_W : FCUEQ_W_ENC, FCUEQ_W_DESC; 3033def FCUEQ_D : FCUEQ_D_ENC, FCUEQ_D_DESC; 3034 3035def FCULE_W : FCULE_W_ENC, FCULE_W_DESC; 3036def FCULE_D : FCULE_D_ENC, FCULE_D_DESC; 3037 3038def FCULT_W : FCULT_W_ENC, FCULT_W_DESC; 3039def FCULT_D : FCULT_D_ENC, FCULT_D_DESC; 3040 3041def FCUN_W : FCUN_W_ENC, FCUN_W_DESC; 3042def FCUN_D : FCUN_D_ENC, FCUN_D_DESC; 3043 3044def FCUNE_W : FCUNE_W_ENC, FCUNE_W_DESC; 3045def FCUNE_D : FCUNE_D_ENC, FCUNE_D_DESC; 3046 3047def FDIV_W : FDIV_W_ENC, FDIV_W_DESC; 3048def FDIV_D : FDIV_D_ENC, FDIV_D_DESC; 3049 3050def FEXDO_H : FEXDO_H_ENC, FEXDO_H_DESC; 3051def FEXDO_W : FEXDO_W_ENC, FEXDO_W_DESC; 3052 3053def FEXP2_W : FEXP2_W_ENC, FEXP2_W_DESC; 3054def FEXP2_D : FEXP2_D_ENC, FEXP2_D_DESC; 3055def FEXP2_W_1_PSEUDO : FEXP2_W_1_PSEUDO_DESC; 3056def FEXP2_D_1_PSEUDO : FEXP2_D_1_PSEUDO_DESC; 3057 3058def FEXUPL_W : FEXUPL_W_ENC, FEXUPL_W_DESC; 3059def FEXUPL_D : FEXUPL_D_ENC, FEXUPL_D_DESC; 3060 3061def FEXUPR_W : FEXUPR_W_ENC, FEXUPR_W_DESC; 3062def FEXUPR_D : FEXUPR_D_ENC, FEXUPR_D_DESC; 3063 3064def FFINT_S_W : FFINT_S_W_ENC, FFINT_S_W_DESC; 3065def FFINT_S_D : FFINT_S_D_ENC, FFINT_S_D_DESC; 3066 3067def FFINT_U_W : FFINT_U_W_ENC, FFINT_U_W_DESC; 3068def FFINT_U_D : FFINT_U_D_ENC, FFINT_U_D_DESC; 3069 3070def FFQL_W : FFQL_W_ENC, FFQL_W_DESC; 3071def FFQL_D : FFQL_D_ENC, FFQL_D_DESC; 3072 3073def FFQR_W : FFQR_W_ENC, FFQR_W_DESC; 3074def FFQR_D : FFQR_D_ENC, FFQR_D_DESC; 3075 3076def FILL_B : FILL_B_ENC, FILL_B_DESC; 3077def FILL_H : FILL_H_ENC, FILL_H_DESC; 3078def FILL_W : FILL_W_ENC, FILL_W_DESC; 3079def FILL_D : FILL_D_ENC, FILL_D_DESC, ASE_MSA64; 3080def FILL_FW_PSEUDO : FILL_FW_PSEUDO_DESC; 3081def FILL_FD_PSEUDO : FILL_FD_PSEUDO_DESC; 3082 3083def FLOG2_W : FLOG2_W_ENC, FLOG2_W_DESC; 3084def FLOG2_D : FLOG2_D_ENC, FLOG2_D_DESC; 3085 3086def FMADD_W : FMADD_W_ENC, FMADD_W_DESC; 3087def FMADD_D : FMADD_D_ENC, FMADD_D_DESC; 3088 3089def FMAX_W : FMAX_W_ENC, FMAX_W_DESC; 3090def FMAX_D : FMAX_D_ENC, FMAX_D_DESC; 3091 3092def FMAX_A_W : FMAX_A_W_ENC, FMAX_A_W_DESC; 3093def FMAX_A_D : FMAX_A_D_ENC, FMAX_A_D_DESC; 3094 3095def FMIN_W : FMIN_W_ENC, FMIN_W_DESC; 3096def FMIN_D : FMIN_D_ENC, FMIN_D_DESC; 3097 3098def FMIN_A_W : FMIN_A_W_ENC, FMIN_A_W_DESC; 3099def FMIN_A_D : FMIN_A_D_ENC, FMIN_A_D_DESC; 3100 3101def FMSUB_W : FMSUB_W_ENC, FMSUB_W_DESC; 3102def FMSUB_D : FMSUB_D_ENC, FMSUB_D_DESC; 3103 3104def FMUL_W : FMUL_W_ENC, FMUL_W_DESC; 3105def FMUL_D : FMUL_D_ENC, FMUL_D_DESC; 3106 3107def FRINT_W : FRINT_W_ENC, FRINT_W_DESC; 3108def FRINT_D : FRINT_D_ENC, FRINT_D_DESC; 3109 3110def FRCP_W : FRCP_W_ENC, FRCP_W_DESC; 3111def FRCP_D : FRCP_D_ENC, FRCP_D_DESC; 3112 3113def FRSQRT_W : FRSQRT_W_ENC, FRSQRT_W_DESC; 3114def FRSQRT_D : FRSQRT_D_ENC, FRSQRT_D_DESC; 3115 3116def FSAF_W : FSAF_W_ENC, FSAF_W_DESC; 3117def FSAF_D : FSAF_D_ENC, FSAF_D_DESC; 3118 3119def FSEQ_W : FSEQ_W_ENC, FSEQ_W_DESC; 3120def FSEQ_D : FSEQ_D_ENC, FSEQ_D_DESC; 3121 3122def FSLE_W : FSLE_W_ENC, FSLE_W_DESC; 3123def FSLE_D : FSLE_D_ENC, FSLE_D_DESC; 3124 3125def FSLT_W : FSLT_W_ENC, FSLT_W_DESC; 3126def FSLT_D : FSLT_D_ENC, FSLT_D_DESC; 3127 3128def FSNE_W : FSNE_W_ENC, FSNE_W_DESC; 3129def FSNE_D : FSNE_D_ENC, FSNE_D_DESC; 3130 3131def FSOR_W : FSOR_W_ENC, FSOR_W_DESC; 3132def FSOR_D : FSOR_D_ENC, FSOR_D_DESC; 3133 3134def FSQRT_W : FSQRT_W_ENC, FSQRT_W_DESC; 3135def FSQRT_D : FSQRT_D_ENC, FSQRT_D_DESC; 3136 3137def FSUB_W : FSUB_W_ENC, FSUB_W_DESC; 3138def FSUB_D : FSUB_D_ENC, FSUB_D_DESC; 3139 3140def FSUEQ_W : FSUEQ_W_ENC, FSUEQ_W_DESC; 3141def FSUEQ_D : FSUEQ_D_ENC, FSUEQ_D_DESC; 3142 3143def FSULE_W : FSULE_W_ENC, FSULE_W_DESC; 3144def FSULE_D : FSULE_D_ENC, FSULE_D_DESC; 3145 3146def FSULT_W : FSULT_W_ENC, FSULT_W_DESC; 3147def FSULT_D : FSULT_D_ENC, FSULT_D_DESC; 3148 3149def FSUN_W : FSUN_W_ENC, FSUN_W_DESC; 3150def FSUN_D : FSUN_D_ENC, FSUN_D_DESC; 3151 3152def FSUNE_W : FSUNE_W_ENC, FSUNE_W_DESC; 3153def FSUNE_D : FSUNE_D_ENC, FSUNE_D_DESC; 3154 3155def FTINT_S_W : FTINT_S_W_ENC, FTINT_S_W_DESC; 3156def FTINT_S_D : FTINT_S_D_ENC, FTINT_S_D_DESC; 3157 3158def FTINT_U_W : FTINT_U_W_ENC, FTINT_U_W_DESC; 3159def FTINT_U_D : FTINT_U_D_ENC, FTINT_U_D_DESC; 3160 3161def FTQ_H : FTQ_H_ENC, FTQ_H_DESC; 3162def FTQ_W : FTQ_W_ENC, FTQ_W_DESC; 3163 3164def FTRUNC_S_W : FTRUNC_S_W_ENC, FTRUNC_S_W_DESC; 3165def FTRUNC_S_D : FTRUNC_S_D_ENC, FTRUNC_S_D_DESC; 3166 3167def FTRUNC_U_W : FTRUNC_U_W_ENC, FTRUNC_U_W_DESC; 3168def FTRUNC_U_D : FTRUNC_U_D_ENC, FTRUNC_U_D_DESC; 3169 3170def : MipsPat<(fsub MSA128WOpnd:$wd, (fmul MSA128WOpnd:$ws, MSA128WOpnd:$wt)), 3171 (FMSUB_W MSA128WOpnd:$wd, MSA128WOpnd:$ws, MSA128WOpnd:$wt)>, 3172 ISA_MIPS1, ASE_MSA, FPOP_FUSION_FAST; 3173def : MipsPat<(fsub MSA128DOpnd:$wd, (fmul MSA128DOpnd:$ws, MSA128DOpnd:$wt)), 3174 (FMSUB_D MSA128DOpnd:$wd, MSA128DOpnd:$ws, MSA128DOpnd:$wt)>, 3175 ISA_MIPS1, ASE_MSA, FPOP_FUSION_FAST; 3176 3177def : MipsPat<(fadd MSA128WOpnd:$wd, (fmul MSA128WOpnd:$ws, MSA128WOpnd:$wt)), 3178 (FMADD_W MSA128WOpnd:$wd, MSA128WOpnd:$ws, MSA128WOpnd:$wt)>, 3179 ISA_MIPS1, ASE_MSA, FPOP_FUSION_FAST; 3180def : MipsPat<(fadd MSA128DOpnd:$wd, (fmul MSA128DOpnd:$ws, MSA128DOpnd:$wt)), 3181 (FMADD_D MSA128DOpnd:$wd, MSA128DOpnd:$ws, MSA128DOpnd:$wt)>, 3182 ISA_MIPS1, ASE_MSA, FPOP_FUSION_FAST; 3183 3184def HADD_S_H : HADD_S_H_ENC, HADD_S_H_DESC; 3185def HADD_S_W : HADD_S_W_ENC, HADD_S_W_DESC; 3186def HADD_S_D : HADD_S_D_ENC, HADD_S_D_DESC; 3187 3188def HADD_U_H : HADD_U_H_ENC, HADD_U_H_DESC; 3189def HADD_U_W : HADD_U_W_ENC, HADD_U_W_DESC; 3190def HADD_U_D : HADD_U_D_ENC, HADD_U_D_DESC; 3191 3192def HSUB_S_H : HSUB_S_H_ENC, HSUB_S_H_DESC; 3193def HSUB_S_W : HSUB_S_W_ENC, HSUB_S_W_DESC; 3194def HSUB_S_D : HSUB_S_D_ENC, HSUB_S_D_DESC; 3195 3196def HSUB_U_H : HSUB_U_H_ENC, HSUB_U_H_DESC; 3197def HSUB_U_W : HSUB_U_W_ENC, HSUB_U_W_DESC; 3198def HSUB_U_D : HSUB_U_D_ENC, HSUB_U_D_DESC; 3199 3200def ILVEV_B : ILVEV_B_ENC, ILVEV_B_DESC; 3201def ILVEV_H : ILVEV_H_ENC, ILVEV_H_DESC; 3202def ILVEV_W : ILVEV_W_ENC, ILVEV_W_DESC; 3203def ILVEV_D : ILVEV_D_ENC, ILVEV_D_DESC; 3204 3205def ILVL_B : ILVL_B_ENC, ILVL_B_DESC; 3206def ILVL_H : ILVL_H_ENC, ILVL_H_DESC; 3207def ILVL_W : ILVL_W_ENC, ILVL_W_DESC; 3208def ILVL_D : ILVL_D_ENC, ILVL_D_DESC; 3209 3210def ILVOD_B : ILVOD_B_ENC, ILVOD_B_DESC; 3211def ILVOD_H : ILVOD_H_ENC, ILVOD_H_DESC; 3212def ILVOD_W : ILVOD_W_ENC, ILVOD_W_DESC; 3213def ILVOD_D : ILVOD_D_ENC, ILVOD_D_DESC; 3214 3215def ILVR_B : ILVR_B_ENC, ILVR_B_DESC; 3216def ILVR_H : ILVR_H_ENC, ILVR_H_DESC; 3217def ILVR_W : ILVR_W_ENC, ILVR_W_DESC; 3218def ILVR_D : ILVR_D_ENC, ILVR_D_DESC; 3219 3220def INSERT_B : INSERT_B_ENC, INSERT_B_DESC; 3221def INSERT_H : INSERT_H_ENC, INSERT_H_DESC; 3222def INSERT_W : INSERT_W_ENC, INSERT_W_DESC; 3223def INSERT_D : INSERT_D_ENC, INSERT_D_DESC, ASE_MSA64; 3224 3225// INSERT_FW_PSEUDO defined after INSVE_W 3226// INSERT_FD_PSEUDO defined after INSVE_D 3227 3228// There is a fourth operand that is not present in the encoding. Use a 3229// custom decoder to get a chance to add it. 3230let DecoderMethod = "DecodeINSVE_DF" in { 3231 def INSVE_B : INSVE_B_ENC, INSVE_B_DESC; 3232 def INSVE_H : INSVE_H_ENC, INSVE_H_DESC; 3233 def INSVE_W : INSVE_W_ENC, INSVE_W_DESC; 3234 def INSVE_D : INSVE_D_ENC, INSVE_D_DESC; 3235} 3236 3237def INSERT_FW_PSEUDO : INSERT_FW_PSEUDO_DESC; 3238def INSERT_FD_PSEUDO : INSERT_FD_PSEUDO_DESC; 3239 3240def INSERT_B_VIDX_PSEUDO : INSERT_B_VIDX_PSEUDO_DESC; 3241def INSERT_H_VIDX_PSEUDO : INSERT_H_VIDX_PSEUDO_DESC; 3242def INSERT_W_VIDX_PSEUDO : INSERT_W_VIDX_PSEUDO_DESC; 3243def INSERT_D_VIDX_PSEUDO : INSERT_D_VIDX_PSEUDO_DESC; 3244def INSERT_FW_VIDX_PSEUDO : INSERT_FW_VIDX_PSEUDO_DESC; 3245def INSERT_FD_VIDX_PSEUDO : INSERT_FD_VIDX_PSEUDO_DESC; 3246 3247def INSERT_B_VIDX64_PSEUDO : INSERT_B_VIDX64_PSEUDO_DESC; 3248def INSERT_H_VIDX64_PSEUDO : INSERT_H_VIDX64_PSEUDO_DESC; 3249def INSERT_W_VIDX64_PSEUDO : INSERT_W_VIDX64_PSEUDO_DESC; 3250def INSERT_D_VIDX64_PSEUDO : INSERT_D_VIDX64_PSEUDO_DESC; 3251def INSERT_FW_VIDX64_PSEUDO : INSERT_FW_VIDX64_PSEUDO_DESC; 3252def INSERT_FD_VIDX64_PSEUDO : INSERT_FD_VIDX64_PSEUDO_DESC; 3253 3254def LD_B: LD_B_ENC, LD_B_DESC; 3255def LD_H: LD_H_ENC, LD_H_DESC; 3256def LD_W: LD_W_ENC, LD_W_DESC; 3257def LD_D: LD_D_ENC, LD_D_DESC; 3258 3259def LDI_B : LDI_B_ENC, LDI_B_DESC; 3260def LDI_H : LDI_H_ENC, LDI_H_DESC; 3261def LDI_W : LDI_W_ENC, LDI_W_DESC; 3262def LDI_D : LDI_D_ENC, LDI_D_DESC; 3263 3264def LSA : LSA_ENC, LSA_DESC; 3265def DLSA : DLSA_ENC, DLSA_DESC, ASE_MSA64; 3266 3267def MADD_Q_H : MADD_Q_H_ENC, MADD_Q_H_DESC; 3268def MADD_Q_W : MADD_Q_W_ENC, MADD_Q_W_DESC; 3269 3270def MADDR_Q_H : MADDR_Q_H_ENC, MADDR_Q_H_DESC; 3271def MADDR_Q_W : MADDR_Q_W_ENC, MADDR_Q_W_DESC; 3272 3273def MADDV_B : MADDV_B_ENC, MADDV_B_DESC; 3274def MADDV_H : MADDV_H_ENC, MADDV_H_DESC; 3275def MADDV_W : MADDV_W_ENC, MADDV_W_DESC; 3276def MADDV_D : MADDV_D_ENC, MADDV_D_DESC; 3277 3278def MAX_A_B : MAX_A_B_ENC, MAX_A_B_DESC; 3279def MAX_A_H : MAX_A_H_ENC, MAX_A_H_DESC; 3280def MAX_A_W : MAX_A_W_ENC, MAX_A_W_DESC; 3281def MAX_A_D : MAX_A_D_ENC, MAX_A_D_DESC; 3282 3283def MAX_S_B : MAX_S_B_ENC, MAX_S_B_DESC; 3284def MAX_S_H : MAX_S_H_ENC, MAX_S_H_DESC; 3285def MAX_S_W : MAX_S_W_ENC, MAX_S_W_DESC; 3286def MAX_S_D : MAX_S_D_ENC, MAX_S_D_DESC; 3287 3288def MAX_U_B : MAX_U_B_ENC, MAX_U_B_DESC; 3289def MAX_U_H : MAX_U_H_ENC, MAX_U_H_DESC; 3290def MAX_U_W : MAX_U_W_ENC, MAX_U_W_DESC; 3291def MAX_U_D : MAX_U_D_ENC, MAX_U_D_DESC; 3292 3293def MAXI_S_B : MAXI_S_B_ENC, MAXI_S_B_DESC; 3294def MAXI_S_H : MAXI_S_H_ENC, MAXI_S_H_DESC; 3295def MAXI_S_W : MAXI_S_W_ENC, MAXI_S_W_DESC; 3296def MAXI_S_D : MAXI_S_D_ENC, MAXI_S_D_DESC; 3297 3298def MAXI_U_B : MAXI_U_B_ENC, MAXI_U_B_DESC; 3299def MAXI_U_H : MAXI_U_H_ENC, MAXI_U_H_DESC; 3300def MAXI_U_W : MAXI_U_W_ENC, MAXI_U_W_DESC; 3301def MAXI_U_D : MAXI_U_D_ENC, MAXI_U_D_DESC; 3302 3303def MIN_A_B : MIN_A_B_ENC, MIN_A_B_DESC; 3304def MIN_A_H : MIN_A_H_ENC, MIN_A_H_DESC; 3305def MIN_A_W : MIN_A_W_ENC, MIN_A_W_DESC; 3306def MIN_A_D : MIN_A_D_ENC, MIN_A_D_DESC; 3307 3308def MIN_S_B : MIN_S_B_ENC, MIN_S_B_DESC; 3309def MIN_S_H : MIN_S_H_ENC, MIN_S_H_DESC; 3310def MIN_S_W : MIN_S_W_ENC, MIN_S_W_DESC; 3311def MIN_S_D : MIN_S_D_ENC, MIN_S_D_DESC; 3312 3313def MIN_U_B : MIN_U_B_ENC, MIN_U_B_DESC; 3314def MIN_U_H : MIN_U_H_ENC, MIN_U_H_DESC; 3315def MIN_U_W : MIN_U_W_ENC, MIN_U_W_DESC; 3316def MIN_U_D : MIN_U_D_ENC, MIN_U_D_DESC; 3317 3318def MINI_S_B : MINI_S_B_ENC, MINI_S_B_DESC; 3319def MINI_S_H : MINI_S_H_ENC, MINI_S_H_DESC; 3320def MINI_S_W : MINI_S_W_ENC, MINI_S_W_DESC; 3321def MINI_S_D : MINI_S_D_ENC, MINI_S_D_DESC; 3322 3323def MINI_U_B : MINI_U_B_ENC, MINI_U_B_DESC; 3324def MINI_U_H : MINI_U_H_ENC, MINI_U_H_DESC; 3325def MINI_U_W : MINI_U_W_ENC, MINI_U_W_DESC; 3326def MINI_U_D : MINI_U_D_ENC, MINI_U_D_DESC; 3327 3328def MOD_S_B : MOD_S_B_ENC, MOD_S_B_DESC; 3329def MOD_S_H : MOD_S_H_ENC, MOD_S_H_DESC; 3330def MOD_S_W : MOD_S_W_ENC, MOD_S_W_DESC; 3331def MOD_S_D : MOD_S_D_ENC, MOD_S_D_DESC; 3332 3333def MOD_U_B : MOD_U_B_ENC, MOD_U_B_DESC; 3334def MOD_U_H : MOD_U_H_ENC, MOD_U_H_DESC; 3335def MOD_U_W : MOD_U_W_ENC, MOD_U_W_DESC; 3336def MOD_U_D : MOD_U_D_ENC, MOD_U_D_DESC; 3337 3338def MOVE_V : MOVE_V_ENC, MOVE_V_DESC; 3339 3340def MSUB_Q_H : MSUB_Q_H_ENC, MSUB_Q_H_DESC; 3341def MSUB_Q_W : MSUB_Q_W_ENC, MSUB_Q_W_DESC; 3342 3343def MSUBR_Q_H : MSUBR_Q_H_ENC, MSUBR_Q_H_DESC; 3344def MSUBR_Q_W : MSUBR_Q_W_ENC, MSUBR_Q_W_DESC; 3345 3346def MSUBV_B : MSUBV_B_ENC, MSUBV_B_DESC; 3347def MSUBV_H : MSUBV_H_ENC, MSUBV_H_DESC; 3348def MSUBV_W : MSUBV_W_ENC, MSUBV_W_DESC; 3349def MSUBV_D : MSUBV_D_ENC, MSUBV_D_DESC; 3350 3351def MUL_Q_H : MUL_Q_H_ENC, MUL_Q_H_DESC; 3352def MUL_Q_W : MUL_Q_W_ENC, MUL_Q_W_DESC; 3353 3354def MULR_Q_H : MULR_Q_H_ENC, MULR_Q_H_DESC; 3355def MULR_Q_W : MULR_Q_W_ENC, MULR_Q_W_DESC; 3356 3357def MULV_B : MULV_B_ENC, MULV_B_DESC; 3358def MULV_H : MULV_H_ENC, MULV_H_DESC; 3359def MULV_W : MULV_W_ENC, MULV_W_DESC; 3360def MULV_D : MULV_D_ENC, MULV_D_DESC; 3361 3362def NLOC_B : NLOC_B_ENC, NLOC_B_DESC; 3363def NLOC_H : NLOC_H_ENC, NLOC_H_DESC; 3364def NLOC_W : NLOC_W_ENC, NLOC_W_DESC; 3365def NLOC_D : NLOC_D_ENC, NLOC_D_DESC; 3366 3367def NLZC_B : NLZC_B_ENC, NLZC_B_DESC; 3368def NLZC_H : NLZC_H_ENC, NLZC_H_DESC; 3369def NLZC_W : NLZC_W_ENC, NLZC_W_DESC; 3370def NLZC_D : NLZC_D_ENC, NLZC_D_DESC; 3371 3372def NOR_V : NOR_V_ENC, NOR_V_DESC; 3373def NOR_V_H_PSEUDO : NOR_V_H_PSEUDO_DESC, 3374 PseudoInstExpansion<(NOR_V MSA128BOpnd:$wd, 3375 MSA128BOpnd:$ws, 3376 MSA128BOpnd:$wt)>; 3377def NOR_V_W_PSEUDO : NOR_V_W_PSEUDO_DESC, 3378 PseudoInstExpansion<(NOR_V MSA128BOpnd:$wd, 3379 MSA128BOpnd:$ws, 3380 MSA128BOpnd:$wt)>; 3381def NOR_V_D_PSEUDO : NOR_V_D_PSEUDO_DESC, 3382 PseudoInstExpansion<(NOR_V MSA128BOpnd:$wd, 3383 MSA128BOpnd:$ws, 3384 MSA128BOpnd:$wt)>; 3385 3386def NORI_B : NORI_B_ENC, NORI_B_DESC; 3387 3388def OR_V : OR_V_ENC, OR_V_DESC; 3389def OR_V_H_PSEUDO : OR_V_H_PSEUDO_DESC, 3390 PseudoInstExpansion<(OR_V MSA128BOpnd:$wd, 3391 MSA128BOpnd:$ws, 3392 MSA128BOpnd:$wt)>; 3393def OR_V_W_PSEUDO : OR_V_W_PSEUDO_DESC, 3394 PseudoInstExpansion<(OR_V MSA128BOpnd:$wd, 3395 MSA128BOpnd:$ws, 3396 MSA128BOpnd:$wt)>; 3397def OR_V_D_PSEUDO : OR_V_D_PSEUDO_DESC, 3398 PseudoInstExpansion<(OR_V MSA128BOpnd:$wd, 3399 MSA128BOpnd:$ws, 3400 MSA128BOpnd:$wt)>; 3401 3402def ORI_B : ORI_B_ENC, ORI_B_DESC; 3403 3404def PCKEV_B : PCKEV_B_ENC, PCKEV_B_DESC; 3405def PCKEV_H : PCKEV_H_ENC, PCKEV_H_DESC; 3406def PCKEV_W : PCKEV_W_ENC, PCKEV_W_DESC; 3407def PCKEV_D : PCKEV_D_ENC, PCKEV_D_DESC; 3408 3409def PCKOD_B : PCKOD_B_ENC, PCKOD_B_DESC; 3410def PCKOD_H : PCKOD_H_ENC, PCKOD_H_DESC; 3411def PCKOD_W : PCKOD_W_ENC, PCKOD_W_DESC; 3412def PCKOD_D : PCKOD_D_ENC, PCKOD_D_DESC; 3413 3414def PCNT_B : PCNT_B_ENC, PCNT_B_DESC; 3415def PCNT_H : PCNT_H_ENC, PCNT_H_DESC; 3416def PCNT_W : PCNT_W_ENC, PCNT_W_DESC; 3417def PCNT_D : PCNT_D_ENC, PCNT_D_DESC; 3418 3419def SAT_S_B : SAT_S_B_ENC, SAT_S_B_DESC; 3420def SAT_S_H : SAT_S_H_ENC, SAT_S_H_DESC; 3421def SAT_S_W : SAT_S_W_ENC, SAT_S_W_DESC; 3422def SAT_S_D : SAT_S_D_ENC, SAT_S_D_DESC; 3423 3424def SAT_U_B : SAT_U_B_ENC, SAT_U_B_DESC; 3425def SAT_U_H : SAT_U_H_ENC, SAT_U_H_DESC; 3426def SAT_U_W : SAT_U_W_ENC, SAT_U_W_DESC; 3427def SAT_U_D : SAT_U_D_ENC, SAT_U_D_DESC; 3428 3429def SHF_B : SHF_B_ENC, SHF_B_DESC; 3430def SHF_H : SHF_H_ENC, SHF_H_DESC; 3431def SHF_W : SHF_W_ENC, SHF_W_DESC; 3432 3433def SLD_B : SLD_B_ENC, SLD_B_DESC; 3434def SLD_H : SLD_H_ENC, SLD_H_DESC; 3435def SLD_W : SLD_W_ENC, SLD_W_DESC; 3436def SLD_D : SLD_D_ENC, SLD_D_DESC; 3437 3438def SLDI_B : SLDI_B_ENC, SLDI_B_DESC; 3439def SLDI_H : SLDI_H_ENC, SLDI_H_DESC; 3440def SLDI_W : SLDI_W_ENC, SLDI_W_DESC; 3441def SLDI_D : SLDI_D_ENC, SLDI_D_DESC; 3442 3443def SLL_B : SLL_B_ENC, SLL_B_DESC; 3444def SLL_H : SLL_H_ENC, SLL_H_DESC; 3445def SLL_W : SLL_W_ENC, SLL_W_DESC; 3446def SLL_D : SLL_D_ENC, SLL_D_DESC; 3447 3448def SLLI_B : SLLI_B_ENC, SLLI_B_DESC; 3449def SLLI_H : SLLI_H_ENC, SLLI_H_DESC; 3450def SLLI_W : SLLI_W_ENC, SLLI_W_DESC; 3451def SLLI_D : SLLI_D_ENC, SLLI_D_DESC; 3452 3453def SPLAT_B : SPLAT_B_ENC, SPLAT_B_DESC; 3454def SPLAT_H : SPLAT_H_ENC, SPLAT_H_DESC; 3455def SPLAT_W : SPLAT_W_ENC, SPLAT_W_DESC; 3456def SPLAT_D : SPLAT_D_ENC, SPLAT_D_DESC; 3457 3458def SPLATI_B : SPLATI_B_ENC, SPLATI_B_DESC; 3459def SPLATI_H : SPLATI_H_ENC, SPLATI_H_DESC; 3460def SPLATI_W : SPLATI_W_ENC, SPLATI_W_DESC; 3461def SPLATI_D : SPLATI_D_ENC, SPLATI_D_DESC; 3462 3463def SRA_B : SRA_B_ENC, SRA_B_DESC; 3464def SRA_H : SRA_H_ENC, SRA_H_DESC; 3465def SRA_W : SRA_W_ENC, SRA_W_DESC; 3466def SRA_D : SRA_D_ENC, SRA_D_DESC; 3467 3468def SRAI_B : SRAI_B_ENC, SRAI_B_DESC; 3469def SRAI_H : SRAI_H_ENC, SRAI_H_DESC; 3470def SRAI_W : SRAI_W_ENC, SRAI_W_DESC; 3471def SRAI_D : SRAI_D_ENC, SRAI_D_DESC; 3472 3473def SRAR_B : SRAR_B_ENC, SRAR_B_DESC; 3474def SRAR_H : SRAR_H_ENC, SRAR_H_DESC; 3475def SRAR_W : SRAR_W_ENC, SRAR_W_DESC; 3476def SRAR_D : SRAR_D_ENC, SRAR_D_DESC; 3477 3478def SRARI_B : SRARI_B_ENC, SRARI_B_DESC; 3479def SRARI_H : SRARI_H_ENC, SRARI_H_DESC; 3480def SRARI_W : SRARI_W_ENC, SRARI_W_DESC; 3481def SRARI_D : SRARI_D_ENC, SRARI_D_DESC; 3482 3483def SRL_B : SRL_B_ENC, SRL_B_DESC; 3484def SRL_H : SRL_H_ENC, SRL_H_DESC; 3485def SRL_W : SRL_W_ENC, SRL_W_DESC; 3486def SRL_D : SRL_D_ENC, SRL_D_DESC; 3487 3488def SRLI_B : SRLI_B_ENC, SRLI_B_DESC; 3489def SRLI_H : SRLI_H_ENC, SRLI_H_DESC; 3490def SRLI_W : SRLI_W_ENC, SRLI_W_DESC; 3491def SRLI_D : SRLI_D_ENC, SRLI_D_DESC; 3492 3493def SRLR_B : SRLR_B_ENC, SRLR_B_DESC; 3494def SRLR_H : SRLR_H_ENC, SRLR_H_DESC; 3495def SRLR_W : SRLR_W_ENC, SRLR_W_DESC; 3496def SRLR_D : SRLR_D_ENC, SRLR_D_DESC; 3497 3498def SRLRI_B : SRLRI_B_ENC, SRLRI_B_DESC; 3499def SRLRI_H : SRLRI_H_ENC, SRLRI_H_DESC; 3500def SRLRI_W : SRLRI_W_ENC, SRLRI_W_DESC; 3501def SRLRI_D : SRLRI_D_ENC, SRLRI_D_DESC; 3502 3503def ST_B: ST_B_ENC, ST_B_DESC; 3504def ST_H: ST_H_ENC, ST_H_DESC; 3505def ST_W: ST_W_ENC, ST_W_DESC; 3506def ST_D: ST_D_ENC, ST_D_DESC; 3507 3508def SUBS_S_B : SUBS_S_B_ENC, SUBS_S_B_DESC; 3509def SUBS_S_H : SUBS_S_H_ENC, SUBS_S_H_DESC; 3510def SUBS_S_W : SUBS_S_W_ENC, SUBS_S_W_DESC; 3511def SUBS_S_D : SUBS_S_D_ENC, SUBS_S_D_DESC; 3512 3513def SUBS_U_B : SUBS_U_B_ENC, SUBS_U_B_DESC; 3514def SUBS_U_H : SUBS_U_H_ENC, SUBS_U_H_DESC; 3515def SUBS_U_W : SUBS_U_W_ENC, SUBS_U_W_DESC; 3516def SUBS_U_D : SUBS_U_D_ENC, SUBS_U_D_DESC; 3517 3518def SUBSUS_U_B : SUBSUS_U_B_ENC, SUBSUS_U_B_DESC; 3519def SUBSUS_U_H : SUBSUS_U_H_ENC, SUBSUS_U_H_DESC; 3520def SUBSUS_U_W : SUBSUS_U_W_ENC, SUBSUS_U_W_DESC; 3521def SUBSUS_U_D : SUBSUS_U_D_ENC, SUBSUS_U_D_DESC; 3522 3523def SUBSUU_S_B : SUBSUU_S_B_ENC, SUBSUU_S_B_DESC; 3524def SUBSUU_S_H : SUBSUU_S_H_ENC, SUBSUU_S_H_DESC; 3525def SUBSUU_S_W : SUBSUU_S_W_ENC, SUBSUU_S_W_DESC; 3526def SUBSUU_S_D : SUBSUU_S_D_ENC, SUBSUU_S_D_DESC; 3527 3528def SUBV_B : SUBV_B_ENC, SUBV_B_DESC; 3529def SUBV_H : SUBV_H_ENC, SUBV_H_DESC; 3530def SUBV_W : SUBV_W_ENC, SUBV_W_DESC; 3531def SUBV_D : SUBV_D_ENC, SUBV_D_DESC; 3532 3533def SUBVI_B : SUBVI_B_ENC, SUBVI_B_DESC; 3534def SUBVI_H : SUBVI_H_ENC, SUBVI_H_DESC; 3535def SUBVI_W : SUBVI_W_ENC, SUBVI_W_DESC; 3536def SUBVI_D : SUBVI_D_ENC, SUBVI_D_DESC; 3537 3538def VSHF_B : VSHF_B_ENC, VSHF_B_DESC; 3539def VSHF_H : VSHF_H_ENC, VSHF_H_DESC; 3540def VSHF_W : VSHF_W_ENC, VSHF_W_DESC; 3541def VSHF_D : VSHF_D_ENC, VSHF_D_DESC; 3542 3543def XOR_V : XOR_V_ENC, XOR_V_DESC; 3544def XOR_V_H_PSEUDO : XOR_V_H_PSEUDO_DESC, 3545 PseudoInstExpansion<(XOR_V MSA128BOpnd:$wd, 3546 MSA128BOpnd:$ws, 3547 MSA128BOpnd:$wt)>; 3548def XOR_V_W_PSEUDO : XOR_V_W_PSEUDO_DESC, 3549 PseudoInstExpansion<(XOR_V MSA128BOpnd:$wd, 3550 MSA128BOpnd:$ws, 3551 MSA128BOpnd:$wt)>; 3552def XOR_V_D_PSEUDO : XOR_V_D_PSEUDO_DESC, 3553 PseudoInstExpansion<(XOR_V MSA128BOpnd:$wd, 3554 MSA128BOpnd:$ws, 3555 MSA128BOpnd:$wt)>; 3556 3557def XORI_B : XORI_B_ENC, XORI_B_DESC; 3558 3559// Patterns. 3560class MSAPat<dag pattern, dag result, list<Predicate> pred = [HasMSA]> : 3561 Pat<pattern, result>, Requires<pred>; 3562 3563def : MSAPat<(extractelt (v4i32 MSA128W:$ws), immZExt4:$idx), 3564 (COPY_S_W MSA128W:$ws, immZExt4:$idx)>; 3565 3566def : MSAPat<(v8f16 (load addrimm10lsl1:$addr)), (LD_H addrimm10lsl1:$addr)>; 3567def : MSAPat<(v4f32 (load addrimm10lsl2:$addr)), (LD_W addrimm10lsl2:$addr)>; 3568def : MSAPat<(v2f64 (load addrimm10lsl3:$addr)), (LD_D addrimm10lsl3:$addr)>; 3569 3570def ST_FH : MSAPat<(store (v8f16 MSA128H:$ws), addrimm10lsl1:$addr), 3571 (ST_H MSA128H:$ws, addrimm10lsl1:$addr)>; 3572def ST_FW : MSAPat<(store (v4f32 MSA128W:$ws), addrimm10lsl2:$addr), 3573 (ST_W MSA128W:$ws, addrimm10lsl2:$addr)>; 3574def ST_FD : MSAPat<(store (v2f64 MSA128D:$ws), addrimm10lsl3:$addr), 3575 (ST_D MSA128D:$ws, addrimm10lsl3:$addr)>; 3576 3577class MSA_FABS_PSEUDO_DESC_BASE<RegisterOperand ROWD, 3578 RegisterOperand ROWS = ROWD, 3579 InstrItinClass itin = NoItinerary> : 3580 MSAPseudo<(outs ROWD:$wd), 3581 (ins ROWS:$ws), 3582 [(set ROWD:$wd, (fabs ROWS:$ws))]> { 3583 InstrItinClass Itinerary = itin; 3584} 3585def FABS_W : MSA_FABS_PSEUDO_DESC_BASE<MSA128WOpnd>, 3586 PseudoInstExpansion<(FMAX_A_W MSA128WOpnd:$wd, MSA128WOpnd:$ws, 3587 MSA128WOpnd:$ws)>; 3588def FABS_D : MSA_FABS_PSEUDO_DESC_BASE<MSA128DOpnd>, 3589 PseudoInstExpansion<(FMAX_A_D MSA128DOpnd:$wd, MSA128DOpnd:$ws, 3590 MSA128DOpnd:$ws)>; 3591 3592class MSABitconvertPat<ValueType DstVT, ValueType SrcVT, 3593 RegisterClass DstRC, list<Predicate> preds = [HasMSA]> : 3594 MSAPat<(DstVT (bitconvert SrcVT:$src)), 3595 (COPY_TO_REGCLASS SrcVT:$src, DstRC), preds>; 3596 3597// These are endian-independent because the element size doesnt change 3598def : MSABitconvertPat<v8i16, v8f16, MSA128H>; 3599def : MSABitconvertPat<v4i32, v4f32, MSA128W>; 3600def : MSABitconvertPat<v2i64, v2f64, MSA128D>; 3601def : MSABitconvertPat<v8f16, v8i16, MSA128H>; 3602def : MSABitconvertPat<v4f32, v4i32, MSA128W>; 3603def : MSABitconvertPat<v2f64, v2i64, MSA128D>; 3604 3605// Little endian bitcasts are always no-ops 3606def : MSABitconvertPat<v16i8, v8i16, MSA128B, [HasMSA, IsLE]>; 3607def : MSABitconvertPat<v16i8, v4i32, MSA128B, [HasMSA, IsLE]>; 3608def : MSABitconvertPat<v16i8, v2i64, MSA128B, [HasMSA, IsLE]>; 3609def : MSABitconvertPat<v16i8, v8f16, MSA128B, [HasMSA, IsLE]>; 3610def : MSABitconvertPat<v16i8, v4f32, MSA128B, [HasMSA, IsLE]>; 3611def : MSABitconvertPat<v16i8, v2f64, MSA128B, [HasMSA, IsLE]>; 3612 3613def : MSABitconvertPat<v8i16, v16i8, MSA128H, [HasMSA, IsLE]>; 3614def : MSABitconvertPat<v8i16, v4i32, MSA128H, [HasMSA, IsLE]>; 3615def : MSABitconvertPat<v8i16, v2i64, MSA128H, [HasMSA, IsLE]>; 3616def : MSABitconvertPat<v8i16, v4f32, MSA128H, [HasMSA, IsLE]>; 3617def : MSABitconvertPat<v8i16, v2f64, MSA128H, [HasMSA, IsLE]>; 3618 3619def : MSABitconvertPat<v4i32, v16i8, MSA128W, [HasMSA, IsLE]>; 3620def : MSABitconvertPat<v4i32, v8i16, MSA128W, [HasMSA, IsLE]>; 3621def : MSABitconvertPat<v4i32, v2i64, MSA128W, [HasMSA, IsLE]>; 3622def : MSABitconvertPat<v4i32, v8f16, MSA128W, [HasMSA, IsLE]>; 3623def : MSABitconvertPat<v4i32, v2f64, MSA128W, [HasMSA, IsLE]>; 3624 3625def : MSABitconvertPat<v2i64, v16i8, MSA128D, [HasMSA, IsLE]>; 3626def : MSABitconvertPat<v2i64, v8i16, MSA128D, [HasMSA, IsLE]>; 3627def : MSABitconvertPat<v2i64, v4i32, MSA128D, [HasMSA, IsLE]>; 3628def : MSABitconvertPat<v2i64, v8f16, MSA128D, [HasMSA, IsLE]>; 3629def : MSABitconvertPat<v2i64, v4f32, MSA128D, [HasMSA, IsLE]>; 3630 3631def : MSABitconvertPat<v4f32, v16i8, MSA128W, [HasMSA, IsLE]>; 3632def : MSABitconvertPat<v4f32, v8i16, MSA128W, [HasMSA, IsLE]>; 3633def : MSABitconvertPat<v4f32, v2i64, MSA128W, [HasMSA, IsLE]>; 3634def : MSABitconvertPat<v4f32, v8f16, MSA128W, [HasMSA, IsLE]>; 3635def : MSABitconvertPat<v4f32, v2f64, MSA128W, [HasMSA, IsLE]>; 3636 3637def : MSABitconvertPat<v2f64, v16i8, MSA128D, [HasMSA, IsLE]>; 3638def : MSABitconvertPat<v2f64, v8i16, MSA128D, [HasMSA, IsLE]>; 3639def : MSABitconvertPat<v2f64, v4i32, MSA128D, [HasMSA, IsLE]>; 3640def : MSABitconvertPat<v2f64, v8f16, MSA128D, [HasMSA, IsLE]>; 3641def : MSABitconvertPat<v2f64, v4f32, MSA128D, [HasMSA, IsLE]>; 3642 3643// Big endian bitcasts expand to shuffle instructions. 3644// This is because bitcast is defined to be a store/load sequence and the 3645// vector store/load instructions are mixed-endian with respect to the vector 3646// as a whole (little endian with respect to element order, but big endian 3647// elements). 3648 3649class MSABitconvertReverseQuartersPat<ValueType DstVT, ValueType SrcVT, 3650 RegisterClass DstRC, MSAInst Insn, 3651 RegisterClass ViaRC> : 3652 MSAPat<(DstVT (bitconvert SrcVT:$src)), 3653 (COPY_TO_REGCLASS (Insn (COPY_TO_REGCLASS SrcVT:$src, ViaRC), 27), 3654 DstRC), 3655 [HasMSA, IsBE]>; 3656 3657class MSABitconvertReverseHalvesPat<ValueType DstVT, ValueType SrcVT, 3658 RegisterClass DstRC, MSAInst Insn, 3659 RegisterClass ViaRC> : 3660 MSAPat<(DstVT (bitconvert SrcVT:$src)), 3661 (COPY_TO_REGCLASS (Insn (COPY_TO_REGCLASS SrcVT:$src, ViaRC), 177), 3662 DstRC), 3663 [HasMSA, IsBE]>; 3664 3665class MSABitconvertReverseBInHPat<ValueType DstVT, ValueType SrcVT, 3666 RegisterClass DstRC> : 3667 MSABitconvertReverseHalvesPat<DstVT, SrcVT, DstRC, SHF_B, MSA128B>; 3668 3669class MSABitconvertReverseBInWPat<ValueType DstVT, ValueType SrcVT, 3670 RegisterClass DstRC> : 3671 MSABitconvertReverseQuartersPat<DstVT, SrcVT, DstRC, SHF_B, MSA128B>; 3672 3673class MSABitconvertReverseBInDPat<ValueType DstVT, ValueType SrcVT, 3674 RegisterClass DstRC> : 3675 MSAPat<(DstVT (bitconvert SrcVT:$src)), 3676 (COPY_TO_REGCLASS 3677 (SHF_W 3678 (COPY_TO_REGCLASS 3679 (SHF_B (COPY_TO_REGCLASS SrcVT:$src, MSA128B), 27), 3680 MSA128W), 177), 3681 DstRC), 3682 [HasMSA, IsBE]>; 3683 3684class MSABitconvertReverseHInWPat<ValueType DstVT, ValueType SrcVT, 3685 RegisterClass DstRC> : 3686 MSABitconvertReverseHalvesPat<DstVT, SrcVT, DstRC, SHF_H, MSA128H>; 3687 3688class MSABitconvertReverseHInDPat<ValueType DstVT, ValueType SrcVT, 3689 RegisterClass DstRC> : 3690 MSABitconvertReverseQuartersPat<DstVT, SrcVT, DstRC, SHF_H, MSA128H>; 3691 3692class MSABitconvertReverseWInDPat<ValueType DstVT, ValueType SrcVT, 3693 RegisterClass DstRC> : 3694 MSABitconvertReverseHalvesPat<DstVT, SrcVT, DstRC, SHF_W, MSA128W>; 3695 3696def : MSABitconvertReverseBInHPat<v8i16, v16i8, MSA128H>; 3697def : MSABitconvertReverseBInHPat<v8f16, v16i8, MSA128H>; 3698def : MSABitconvertReverseBInWPat<v4i32, v16i8, MSA128W>; 3699def : MSABitconvertReverseBInWPat<v4f32, v16i8, MSA128W>; 3700def : MSABitconvertReverseBInDPat<v2i64, v16i8, MSA128D>; 3701def : MSABitconvertReverseBInDPat<v2f64, v16i8, MSA128D>; 3702 3703def : MSABitconvertReverseBInHPat<v16i8, v8i16, MSA128B>; 3704def : MSABitconvertReverseHInWPat<v4i32, v8i16, MSA128W>; 3705def : MSABitconvertReverseHInWPat<v4f32, v8i16, MSA128W>; 3706def : MSABitconvertReverseHInDPat<v2i64, v8i16, MSA128D>; 3707def : MSABitconvertReverseHInDPat<v2f64, v8i16, MSA128D>; 3708 3709def : MSABitconvertReverseBInHPat<v16i8, v8f16, MSA128B>; 3710def : MSABitconvertReverseHInWPat<v4i32, v8f16, MSA128W>; 3711def : MSABitconvertReverseHInWPat<v4f32, v8f16, MSA128W>; 3712def : MSABitconvertReverseHInDPat<v2i64, v8f16, MSA128D>; 3713def : MSABitconvertReverseHInDPat<v2f64, v8f16, MSA128D>; 3714 3715def : MSABitconvertReverseBInWPat<v16i8, v4i32, MSA128B>; 3716def : MSABitconvertReverseHInWPat<v8i16, v4i32, MSA128H>; 3717def : MSABitconvertReverseHInWPat<v8f16, v4i32, MSA128H>; 3718def : MSABitconvertReverseWInDPat<v2i64, v4i32, MSA128D>; 3719def : MSABitconvertReverseWInDPat<v2f64, v4i32, MSA128D>; 3720 3721def : MSABitconvertReverseBInWPat<v16i8, v4f32, MSA128B>; 3722def : MSABitconvertReverseHInWPat<v8i16, v4f32, MSA128H>; 3723def : MSABitconvertReverseHInWPat<v8f16, v4f32, MSA128H>; 3724def : MSABitconvertReverseWInDPat<v2i64, v4f32, MSA128D>; 3725def : MSABitconvertReverseWInDPat<v2f64, v4f32, MSA128D>; 3726 3727def : MSABitconvertReverseBInDPat<v16i8, v2i64, MSA128B>; 3728def : MSABitconvertReverseHInDPat<v8i16, v2i64, MSA128H>; 3729def : MSABitconvertReverseHInDPat<v8f16, v2i64, MSA128H>; 3730def : MSABitconvertReverseWInDPat<v4i32, v2i64, MSA128W>; 3731def : MSABitconvertReverseWInDPat<v4f32, v2i64, MSA128W>; 3732 3733def : MSABitconvertReverseBInDPat<v16i8, v2f64, MSA128B>; 3734def : MSABitconvertReverseHInDPat<v8i16, v2f64, MSA128H>; 3735def : MSABitconvertReverseHInDPat<v8f16, v2f64, MSA128H>; 3736def : MSABitconvertReverseWInDPat<v4i32, v2f64, MSA128W>; 3737def : MSABitconvertReverseWInDPat<v4f32, v2f64, MSA128W>; 3738 3739// Pseudos used to implement BNZ.df, and BZ.df 3740 3741class MSA_CBRANCH_PSEUDO_DESC_BASE<SDPatternOperator OpNode, ValueType TyNode, 3742 RegisterClass RCWS, 3743 InstrItinClass itin = NoItinerary> : 3744 MipsPseudo<(outs GPR32:$dst), 3745 (ins RCWS:$ws), 3746 [(set GPR32:$dst, (OpNode (TyNode RCWS:$ws)))]> { 3747 bit usesCustomInserter = 1; 3748 bit hasNoSchedulingInfo = 1; 3749} 3750 3751def SNZ_B_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v16i8, 3752 MSA128B, NoItinerary>; 3753def SNZ_H_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v8i16, 3754 MSA128H, NoItinerary>; 3755def SNZ_W_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v4i32, 3756 MSA128W, NoItinerary>; 3757def SNZ_D_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v2i64, 3758 MSA128D, NoItinerary>; 3759def SNZ_V_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAnyNonZero, v16i8, 3760 MSA128B, NoItinerary>; 3761 3762def SZ_B_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v16i8, 3763 MSA128B, NoItinerary>; 3764def SZ_H_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v8i16, 3765 MSA128H, NoItinerary>; 3766def SZ_W_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v4i32, 3767 MSA128W, NoItinerary>; 3768def SZ_D_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v2i64, 3769 MSA128D, NoItinerary>; 3770def SZ_V_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAnyZero, v16i8, 3771 MSA128B, NoItinerary>; 3772 3773// Pseudoes used to implement transparent fp16 support. 3774 3775let ASEPredicate = [HasMSA] in { 3776 let usesCustomInserter = 1 in { 3777 def ST_F16 : 3778 MipsPseudo<(outs), (ins MSA128F16:$ws, mem_simm10:$addr), 3779 [(store (f16 MSA128F16:$ws), (addrimm10:$addr))]>; 3780 def LD_F16 : 3781 MipsPseudo<(outs MSA128F16:$ws), (ins mem_simm10:$addr), 3782 [(set MSA128F16:$ws, (f16 (load addrimm10:$addr)))]>; 3783 } 3784 3785 let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in { 3786 def MSA_FP_EXTEND_W_PSEUDO : 3787 MipsPseudo<(outs FGR32Opnd:$fd), (ins MSA128F16:$ws), 3788 [(set FGR32Opnd:$fd, (f32 (fpextend MSA128F16:$ws)))]>; 3789 def MSA_FP_ROUND_W_PSEUDO : 3790 MipsPseudo<(outs MSA128F16:$wd), (ins FGR32Opnd:$fs), 3791 [(set MSA128F16:$wd, (f16 (fpround FGR32Opnd:$fs)))]>; 3792 def MSA_FP_EXTEND_D_PSEUDO : 3793 MipsPseudo<(outs FGR64Opnd:$fd), (ins MSA128F16:$ws), 3794 [(set FGR64Opnd:$fd, (f64 (fpextend MSA128F16:$ws)))]>; 3795 def MSA_FP_ROUND_D_PSEUDO : 3796 MipsPseudo<(outs MSA128F16:$wd), (ins FGR64Opnd:$fs), 3797 [(set MSA128F16:$wd, (f16 (fpround FGR64Opnd:$fs)))]>; 3798 } 3799 3800 def : MipsPat<(MipsTruncIntFP MSA128F16:$ws), 3801 (TRUNC_W_D64 (MSA_FP_EXTEND_D_PSEUDO MSA128F16:$ws))>, 3802 ISA_MIPS1, ASE_MSA; 3803 3804 def : MipsPat<(MipsFPCmp MSA128F16:$ws, MSA128F16:$wt, imm:$cond), 3805 (FCMP_S32 (MSA_FP_EXTEND_W_PSEUDO MSA128F16:$ws), 3806 (MSA_FP_EXTEND_W_PSEUDO MSA128F16:$wt), imm:$cond)>, 3807 ISA_MIPS1_NOT_32R6_64R6, ASE_MSA; 3808} 3809 3810def vsplati64_imm_eq_63 : PatLeaf<(bitconvert (v4i32 (build_vector))), [{ 3811 APInt Imm; 3812 SDNode *BV = N->getOperand(0).getNode(); 3813 EVT EltTy = N->getValueType(0).getVectorElementType(); 3814 3815 return selectVSplat(BV, Imm, EltTy.getSizeInBits()) && 3816 Imm.getBitWidth() == EltTy.getSizeInBits() && Imm == 63; 3817}]>; 3818 3819def immi32Cst7 : ImmLeaf<i32, [{return isUInt<32>(Imm) && Imm == 7;}]>; 3820def immi32Cst15 : ImmLeaf<i32, [{return isUInt<32>(Imm) && Imm == 15;}]>; 3821def immi32Cst31 : ImmLeaf<i32, [{return isUInt<32>(Imm) && Imm == 31;}]>; 3822 3823def vsplati8imm7 : PatFrag<(ops node:$wt), 3824 (and node:$wt, (vsplati8 immi32Cst7))>; 3825def vsplati16imm15 : PatFrag<(ops node:$wt), 3826 (and node:$wt, (vsplati16 immi32Cst15))>; 3827def vsplati32imm31 : PatFrag<(ops node:$wt), 3828 (and node:$wt, (vsplati32 immi32Cst31))>; 3829def vsplati64imm63 : PatFrag<(ops node:$wt), 3830 (and node:$wt, vsplati64_imm_eq_63)>; 3831 3832class MSAShiftPat<SDNode Node, ValueType VT, MSAInst Insn, dag Vec> : 3833 MSAPat<(VT (Node VT:$ws, (VT (and VT:$wt, Vec)))), 3834 (VT (Insn VT:$ws, VT:$wt))>; 3835 3836class MSABitPat<SDNode Node, ValueType VT, MSAInst Insn, PatFrag Frag> : 3837 MSAPat<(VT (Node VT:$ws, (shl vsplat_imm_eq_1, (Frag VT:$wt)))), 3838 (VT (Insn VT:$ws, VT:$wt))>; 3839 3840multiclass MSAShiftPats<SDNode Node, string Insn> { 3841 def : MSAShiftPat<Node, v16i8, !cast<MSAInst>(Insn#_B), 3842 (vsplati8 immi32Cst7)>; 3843 def : MSAShiftPat<Node, v8i16, !cast<MSAInst>(Insn#_H), 3844 (vsplati16 immi32Cst15)>; 3845 def : MSAShiftPat<Node, v4i32, !cast<MSAInst>(Insn#_W), 3846 (vsplati32 immi32Cst31)>; 3847 def : MSAPat<(v2i64 (Node v2i64:$ws, (v2i64 (and v2i64:$wt, 3848 vsplati64_imm_eq_63)))), 3849 (v2i64 (!cast<MSAInst>(Insn#_D) v2i64:$ws, v2i64:$wt))>; 3850} 3851 3852multiclass MSABitPats<SDNode Node, string Insn> { 3853 def : MSABitPat<Node, v16i8, !cast<MSAInst>(Insn#_B), vsplati8imm7>; 3854 def : MSABitPat<Node, v8i16, !cast<MSAInst>(Insn#_H), vsplati16imm15>; 3855 def : MSABitPat<Node, v4i32, !cast<MSAInst>(Insn#_W), vsplati32imm31>; 3856 def : MSAPat<(Node v2i64:$ws, (shl (v2i64 vsplati64_imm_eq_1), 3857 (vsplati64imm63 v2i64:$wt))), 3858 (v2i64 (!cast<MSAInst>(Insn#_D) v2i64:$ws, v2i64:$wt))>; 3859} 3860 3861defm : MSAShiftPats<shl, "SLL">; 3862defm : MSAShiftPats<srl, "SRL">; 3863defm : MSAShiftPats<sra, "SRA">; 3864defm : MSABitPats<xor, "BNEG">; 3865defm : MSABitPats<or, "BSET">; 3866 3867def : MSAPat<(and v16i8:$ws, (xor (shl vsplat_imm_eq_1, 3868 (vsplati8imm7 v16i8:$wt)), 3869 immAllOnesV)), 3870 (v16i8 (BCLR_B v16i8:$ws, v16i8:$wt))>; 3871def : MSAPat<(and v8i16:$ws, (xor (shl vsplat_imm_eq_1, 3872 (vsplati16imm15 v8i16:$wt)), 3873 immAllOnesV)), 3874 (v8i16 (BCLR_H v8i16:$ws, v8i16:$wt))>; 3875def : MSAPat<(and v4i32:$ws, (xor (shl vsplat_imm_eq_1, 3876 (vsplati32imm31 v4i32:$wt)), 3877 immAllOnesV)), 3878 (v4i32 (BCLR_W v4i32:$ws, v4i32:$wt))>; 3879def : MSAPat<(and v2i64:$ws, (xor (shl (v2i64 vsplati64_imm_eq_1), 3880 (vsplati64imm63 v2i64:$wt)), 3881 (bitconvert (v4i32 immAllOnesV)))), 3882 (v2i64 (BCLR_D v2i64:$ws, v2i64:$wt))>; 3883 3884// Vector extraction with fixed index. 3885// 3886// Extracting 32-bit values on MSA32 should always use COPY_S_W rather than 3887// COPY_U_W, even for the zero-extended case. This is because our forward 3888// compatibility strategy is to consider registers to be infinitely 3889// sign-extended so that a MIPS64 can execute MIPS32 code without getting 3890// different register values. 3891def : MSAPat<(vextract_zext_i32 (v4i32 MSA128W:$ws), immZExt2Ptr:$idx), 3892 (COPY_S_W MSA128W:$ws, immZExt2:$idx)>, ASE_MSA_NOT_MSA64; 3893def : MSAPat<(vextract_zext_i32 (v4f32 MSA128W:$ws), immZExt2Ptr:$idx), 3894 (COPY_S_W MSA128W:$ws, immZExt2:$idx)>, ASE_MSA_NOT_MSA64; 3895 3896// Extracting 64-bit values on MSA64 should always use COPY_S_D rather than 3897// COPY_U_D, even for the zero-extended case. This is because our forward 3898// compatibility strategy is to consider registers to be infinitely 3899// sign-extended so that a hypothetical MIPS128 would be able to execute MIPS64 3900// code without getting different register values. 3901def : MSAPat<(vextract_zext_i64 (v2i64 MSA128D:$ws), immZExt1Ptr:$idx), 3902 (COPY_S_D MSA128D:$ws, immZExt1:$idx)>, ASE_MSA64; 3903def : MSAPat<(vextract_zext_i64 (v2f64 MSA128D:$ws), immZExt1Ptr:$idx), 3904 (COPY_S_D MSA128D:$ws, immZExt1:$idx)>, ASE_MSA64; 3905 3906// Vector extraction with variable index 3907def : MSAPat<(i32 (vextract_sext_i8 v16i8:$ws, i32:$idx)), 3908 (SRA (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_B v16i8:$ws, 3909 i32:$idx), 3910 sub_lo)), 3911 GPR32), (i32 24))>; 3912def : MSAPat<(i32 (vextract_sext_i16 v8i16:$ws, i32:$idx)), 3913 (SRA (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_H v8i16:$ws, 3914 i32:$idx), 3915 sub_lo)), 3916 GPR32), (i32 16))>; 3917def : MSAPat<(i32 (vextract_sext_i32 v4i32:$ws, i32:$idx)), 3918 (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_W v4i32:$ws, 3919 i32:$idx), 3920 sub_lo)), 3921 GPR32)>; 3922def : MSAPat<(i64 (vextract_sext_i64 v2i64:$ws, i32:$idx)), 3923 (COPY_TO_REGCLASS (i64 (EXTRACT_SUBREG (SPLAT_D v2i64:$ws, 3924 i32:$idx), 3925 sub_64)), 3926 GPR64), [HasMSA, IsGP64bit]>; 3927 3928def : MSAPat<(i32 (vextract_zext_i8 v16i8:$ws, i32:$idx)), 3929 (SRL (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_B v16i8:$ws, 3930 i32:$idx), 3931 sub_lo)), 3932 GPR32), (i32 24))>; 3933def : MSAPat<(i32 (vextract_zext_i16 v8i16:$ws, i32:$idx)), 3934 (SRL (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_H v8i16:$ws, 3935 i32:$idx), 3936 sub_lo)), 3937 GPR32), (i32 16))>; 3938def : MSAPat<(i32 (vextract_zext_i32 v4i32:$ws, i32:$idx)), 3939 (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_W v4i32:$ws, 3940 i32:$idx), 3941 sub_lo)), 3942 GPR32)>; 3943def : MSAPat<(i64 (vextract_zext_i64 v2i64:$ws, i32:$idx)), 3944 (COPY_TO_REGCLASS (i64 (EXTRACT_SUBREG (SPLAT_D v2i64:$ws, 3945 i32:$idx), 3946 sub_64)), 3947 GPR64), [HasMSA, IsGP64bit]>; 3948 3949def : MSAPat<(f32 (vector_extract v4f32:$ws, i32:$idx)), 3950 (f32 (EXTRACT_SUBREG (SPLAT_W v4f32:$ws, 3951 i32:$idx), 3952 sub_lo))>; 3953def : MSAPat<(f64 (vector_extract v2f64:$ws, i32:$idx)), 3954 (f64 (EXTRACT_SUBREG (SPLAT_D v2f64:$ws, 3955 i32:$idx), 3956 sub_64))>; 3957 3958// Vector extraction with variable index (N64 ABI) 3959def : MSAPat< 3960 (i32 (vextract_sext_i8 v16i8:$ws, i64:$idx)), 3961 (SRA (COPY_TO_REGCLASS 3962 (i32 (EXTRACT_SUBREG 3963 (SPLAT_B v16i8:$ws, 3964 (COPY_TO_REGCLASS 3965 (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)), 3966 sub_lo)), 3967 GPR32), 3968 (i32 24))>; 3969def : MSAPat< 3970 (i32 (vextract_sext_i16 v8i16:$ws, i64:$idx)), 3971 (SRA (COPY_TO_REGCLASS 3972 (i32 (EXTRACT_SUBREG 3973 (SPLAT_H v8i16:$ws, 3974 (COPY_TO_REGCLASS 3975 (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)), 3976 sub_lo)), 3977 GPR32), 3978 (i32 16))>; 3979def : MSAPat< 3980 (i32 (vextract_sext_i32 v4i32:$ws, i64:$idx)), 3981 (COPY_TO_REGCLASS 3982 (i32 (EXTRACT_SUBREG 3983 (SPLAT_W v4i32:$ws, 3984 (COPY_TO_REGCLASS 3985 (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)), 3986 sub_lo)), 3987 GPR32)>; 3988def : MSAPat< 3989 (i64 (vextract_sext_i64 v2i64:$ws, i64:$idx)), 3990 (COPY_TO_REGCLASS 3991 (i64 (EXTRACT_SUBREG 3992 (SPLAT_D v2i64:$ws, 3993 (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)), 3994 sub_64)), 3995 GPR64), [HasMSA, IsGP64bit]>; 3996 3997def : MSAPat< 3998 (i32 (vextract_zext_i8 v16i8:$ws, i64:$idx)), 3999 (SRL (COPY_TO_REGCLASS 4000 (i32 (EXTRACT_SUBREG 4001 (SPLAT_B v16i8:$ws, 4002 (COPY_TO_REGCLASS 4003 (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)), 4004 sub_lo)), 4005 GPR32), 4006 (i32 24))>; 4007def : MSAPat< 4008 (i32 (vextract_zext_i16 v8i16:$ws, i64:$idx)), 4009 (SRL (COPY_TO_REGCLASS 4010 (i32 (EXTRACT_SUBREG 4011 (SPLAT_H v8i16:$ws, 4012 (COPY_TO_REGCLASS 4013 (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)), 4014 sub_lo)), 4015 GPR32), 4016 (i32 16))>; 4017def : MSAPat< 4018 (i32 (vextract_zext_i32 v4i32:$ws, i64:$idx)), 4019 (COPY_TO_REGCLASS 4020 (i32 (EXTRACT_SUBREG 4021 (SPLAT_W v4i32:$ws, 4022 (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)), 4023 sub_lo)), 4024 GPR32)>; 4025def : MSAPat< 4026 (i64 (vextract_zext_i64 v2i64:$ws, i64:$idx)), 4027 (COPY_TO_REGCLASS 4028 (i64 (EXTRACT_SUBREG 4029 (SPLAT_D v2i64:$ws, 4030 (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)), 4031 sub_64)), 4032 GPR64), 4033 [HasMSA, IsGP64bit]>; 4034 4035def : MSAPat< 4036 (f32 (vector_extract v4f32:$ws, i64:$idx)), 4037 (f32 (EXTRACT_SUBREG 4038 (SPLAT_W v4f32:$ws, 4039 (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)), 4040 sub_lo))>; 4041def : MSAPat< 4042 (f64 (vector_extract v2f64:$ws, i64:$idx)), 4043 (f64 (EXTRACT_SUBREG 4044 (SPLAT_D v2f64:$ws, 4045 (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)), 4046 sub_64))>; 4047 4048def : MSAPat<(vfseteq_v4f32 MSA128WOpnd:$a, MSA128WOpnd:$b), 4049 (FCEQ_W MSA128WOpnd:$a, MSA128WOpnd:$b)>; 4050def : MSAPat<(vfseteq_v2f64 MSA128DOpnd:$a, MSA128DOpnd:$b), 4051 (FCEQ_D MSA128DOpnd:$a, MSA128DOpnd:$b)>; 4052def : MSAPat<(vfsetle_v4f32 MSA128WOpnd:$a, MSA128WOpnd:$b), 4053 (FCLE_W MSA128WOpnd:$a, MSA128WOpnd:$b)>; 4054def : MSAPat<(vfsetle_v2f64 MSA128DOpnd:$a, MSA128DOpnd:$b), 4055 (FCLE_D MSA128DOpnd:$a, MSA128DOpnd:$b)>; 4056def : MSAPat<(vfsetlt_v4f32 MSA128WOpnd:$a, MSA128WOpnd:$b), 4057 (FCLT_W MSA128WOpnd:$a, MSA128WOpnd:$b)>; 4058def : MSAPat<(vfsetlt_v2f64 MSA128DOpnd:$a, MSA128DOpnd:$b), 4059 (FCLT_D MSA128DOpnd:$a, MSA128DOpnd:$b)>; 4060def : MSAPat<(vfsetne_v4f32 MSA128WOpnd:$a, MSA128WOpnd:$b), 4061 (FCNE_W MSA128WOpnd:$a, MSA128WOpnd:$b)>; 4062def : MSAPat<(vfsetne_v2f64 MSA128DOpnd:$a, MSA128DOpnd:$b), 4063 (FCNE_D MSA128DOpnd:$a, MSA128DOpnd:$b)>; 4064