MipsInstrInfo.cpp revision 360784 
1//===- MipsInstrInfo.cpp - Mips Instruction Information -------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the Mips implementation of the TargetInstrInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "MipsInstrInfo.h"
14#include "MCTargetDesc/MipsBaseInfo.h"
15#include "MCTargetDesc/MipsMCTargetDesc.h"
16#include "MipsSubtarget.h"
17#include "llvm/ADT/SmallVector.h"
18#include "llvm/CodeGen/MachineBasicBlock.h"
19#include "llvm/CodeGen/MachineFrameInfo.h"
20#include "llvm/CodeGen/MachineFunction.h"
21#include "llvm/CodeGen/MachineInstr.h"
22#include "llvm/CodeGen/MachineInstrBuilder.h"
23#include "llvm/CodeGen/MachineOperand.h"
24#include "llvm/CodeGen/TargetOpcodes.h"
25#include "llvm/CodeGen/TargetSubtargetInfo.h"
26#include "llvm/IR/DebugLoc.h"
27#include "llvm/MC/MCInstrDesc.h"
28#include "llvm/Target/TargetMachine.h"
29#include <cassert>
30
31using namespace llvm;
32
33#define GET_INSTRINFO_CTOR_DTOR
34#include "MipsGenInstrInfo.inc"
35
36// Pin the vtable to this file.
37void MipsInstrInfo::anchor() {}
38
39MipsInstrInfo::MipsInstrInfo(const MipsSubtarget &STI, unsigned UncondBr)
40    : MipsGenInstrInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP),
41      Subtarget(STI), UncondBrOpc(UncondBr) {}
42
43const MipsInstrInfo *MipsInstrInfo::create(MipsSubtarget &STI) {
44  if (STI.inMips16Mode())
45    return createMips16InstrInfo(STI);
46
47  return createMipsSEInstrInfo(STI);
48}
49
50bool MipsInstrInfo::isZeroImm(const MachineOperand &op) const {
51  return op.isImm() && op.getImm() == 0;
52}
53
54/// insertNoop - If data hazard condition is found insert the target nop
55/// instruction.
56// FIXME: This appears to be dead code.
57void MipsInstrInfo::
58insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const
59{
60  DebugLoc DL;
61  BuildMI(MBB, MI, DL, get(Mips::NOP));
62}
63
64MachineMemOperand *
65MipsInstrInfo::GetMemOperand(MachineBasicBlock &MBB, int FI,
66                             MachineMemOperand::Flags Flags) const {
67  MachineFunction &MF = *MBB.getParent();
68  MachineFrameInfo &MFI = MF.getFrameInfo();
69  unsigned Align = MFI.getObjectAlignment(FI);
70
71  return MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, FI),
72                                 Flags, MFI.getObjectSize(FI), Align);
73}
74
75//===----------------------------------------------------------------------===//
76// Branch Analysis
77//===----------------------------------------------------------------------===//
78
79void MipsInstrInfo::AnalyzeCondBr(const MachineInstr *Inst, unsigned Opc,
80                                  MachineBasicBlock *&BB,
81                                  SmallVectorImpl<MachineOperand> &Cond) const {
82  assert(getAnalyzableBrOpc(Opc) && "Not an analyzable branch");
83  int NumOp = Inst->getNumExplicitOperands();
84
85  // for both int and fp branches, the last explicit operand is the
86  // MBB.
87  BB = Inst->getOperand(NumOp-1).getMBB();
88  Cond.push_back(MachineOperand::CreateImm(Opc));
89
90  for (int i = 0; i < NumOp-1; i++)
91    Cond.push_back(Inst->getOperand(i));
92}
93
94bool MipsInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
95                                  MachineBasicBlock *&TBB,
96                                  MachineBasicBlock *&FBB,
97                                  SmallVectorImpl<MachineOperand> &Cond,
98                                  bool AllowModify) const {
99  SmallVector<MachineInstr*, 2> BranchInstrs;
100  BranchType BT = analyzeBranch(MBB, TBB, FBB, Cond, AllowModify, BranchInstrs);
101
102  return (BT == BT_None) || (BT == BT_Indirect);
103}
104
105void MipsInstrInfo::BuildCondBr(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
106                                const DebugLoc &DL,
107                                ArrayRef<MachineOperand> Cond) const {
108  unsigned Opc = Cond[0].getImm();
109  const MCInstrDesc &MCID = get(Opc);
110  MachineInstrBuilder MIB = BuildMI(&MBB, DL, MCID);
111
112  for (unsigned i = 1; i < Cond.size(); ++i) {
113    assert((Cond[i].isImm() || Cond[i].isReg()) &&
114           "Cannot copy operand for conditional branch!");
115    MIB.add(Cond[i]);
116  }
117  MIB.addMBB(TBB);
118}
119
120unsigned MipsInstrInfo::insertBranch(MachineBasicBlock &MBB,
121                                     MachineBasicBlock *TBB,
122                                     MachineBasicBlock *FBB,
123                                     ArrayRef<MachineOperand> Cond,
124                                     const DebugLoc &DL,
125                                     int *BytesAdded) const {
126  // Shouldn't be a fall through.
127  assert(TBB && "insertBranch must not be told to insert a fallthrough");
128  assert(!BytesAdded && "code size not handled");
129
130  // # of condition operands:
131  //  Unconditional branches: 0
132  //  Floating point branches: 1 (opc)
133  //  Int BranchZero: 2 (opc, reg)
134  //  Int Branch: 3 (opc, reg0, reg1)
135  assert((Cond.size() <= 3) &&
136         "# of Mips branch conditions must be <= 3!");
137
138  // Two-way Conditional branch.
139  if (FBB) {
140    BuildCondBr(MBB, TBB, DL, Cond);
141    BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(FBB);
142    return 2;
143  }
144
145  // One way branch.
146  // Unconditional branch.
147  if (Cond.empty())
148    BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(TBB);
149  else // Conditional branch.
150    BuildCondBr(MBB, TBB, DL, Cond);
151  return 1;
152}
153
154unsigned MipsInstrInfo::removeBranch(MachineBasicBlock &MBB,
155                                     int *BytesRemoved) const {
156  assert(!BytesRemoved && "code size not handled");
157
158  MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend();
159  unsigned removed = 0;
160
161  // Up to 2 branches are removed.
162  // Note that indirect branches are not removed.
163  while (I != REnd && removed < 2) {
164    // Skip past debug instructions.
165    if (I->isDebugInstr()) {
166      ++I;
167      continue;
168    }
169    if (!getAnalyzableBrOpc(I->getOpcode()))
170      break;
171    // Remove the branch.
172    I->eraseFromParent();
173    I = MBB.rbegin();
174    ++removed;
175  }
176
177  return removed;
178}
179
180/// reverseBranchCondition - Return the inverse opcode of the
181/// specified Branch instruction.
182bool MipsInstrInfo::reverseBranchCondition(
183    SmallVectorImpl<MachineOperand> &Cond) const {
184  assert( (Cond.size() && Cond.size() <= 3) &&
185          "Invalid Mips branch condition!");
186  Cond[0].setImm(getOppositeBranchOpc(Cond[0].getImm()));
187  return false;
188}
189
190MipsInstrInfo::BranchType MipsInstrInfo::analyzeBranch(
191    MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
192    SmallVectorImpl<MachineOperand> &Cond, bool AllowModify,
193    SmallVectorImpl<MachineInstr *> &BranchInstrs) const {
194  MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend();
195
196  // Skip all the debug instructions.
197  while (I != REnd && I->isDebugInstr())
198    ++I;
199
200  if (I == REnd || !isUnpredicatedTerminator(*I)) {
201    // This block ends with no branches (it just falls through to its succ).
202    // Leave TBB/FBB null.
203    TBB = FBB = nullptr;
204    return BT_NoBranch;
205  }
206
207  MachineInstr *LastInst = &*I;
208  unsigned LastOpc = LastInst->getOpcode();
209  BranchInstrs.push_back(LastInst);
210
211  // Not an analyzable branch (e.g., indirect jump).
212  if (!getAnalyzableBrOpc(LastOpc))
213    return LastInst->isIndirectBranch() ? BT_Indirect : BT_None;
214
215  // Get the second to last instruction in the block.
216  unsigned SecondLastOpc = 0;
217  MachineInstr *SecondLastInst = nullptr;
218
219  // Skip past any debug instruction to see if the second last actual
220  // is a branch.
221  ++I;
222  while (I != REnd && I->isDebugInstr())
223    ++I;
224
225  if (I != REnd) {
226    SecondLastInst = &*I;
227    SecondLastOpc = getAnalyzableBrOpc(SecondLastInst->getOpcode());
228
229    // Not an analyzable branch (must be an indirect jump).
230    if (isUnpredicatedTerminator(*SecondLastInst) && !SecondLastOpc)
231      return BT_None;
232  }
233
234  // If there is only one terminator instruction, process it.
235  if (!SecondLastOpc) {
236    // Unconditional branch.
237    if (LastInst->isUnconditionalBranch()) {
238      TBB = LastInst->getOperand(0).getMBB();
239      return BT_Uncond;
240    }
241
242    // Conditional branch
243    AnalyzeCondBr(LastInst, LastOpc, TBB, Cond);
244    return BT_Cond;
245  }
246
247  // If we reached here, there are two branches.
248  // If there are three terminators, we don't know what sort of block this is.
249  if (++I != REnd && isUnpredicatedTerminator(*I))
250    return BT_None;
251
252  BranchInstrs.insert(BranchInstrs.begin(), SecondLastInst);
253
254  // If second to last instruction is an unconditional branch,
255  // analyze it and remove the last instruction.
256  if (SecondLastInst->isUnconditionalBranch()) {
257    // Return if the last instruction cannot be removed.
258    if (!AllowModify)
259      return BT_None;
260
261    TBB = SecondLastInst->getOperand(0).getMBB();
262    LastInst->eraseFromParent();
263    BranchInstrs.pop_back();
264    return BT_Uncond;
265  }
266
267  // Conditional branch followed by an unconditional branch.
268  // The last one must be unconditional.
269  if (!LastInst->isUnconditionalBranch())
270    return BT_None;
271
272  AnalyzeCondBr(SecondLastInst, SecondLastOpc, TBB, Cond);
273  FBB = LastInst->getOperand(0).getMBB();
274
275  return BT_CondUncond;
276}
277
278bool MipsInstrInfo::isBranchOffsetInRange(unsigned BranchOpc,
279                                          int64_t BrOffset) const {
280  switch (BranchOpc) {
281  case Mips::B:
282  case Mips::BAL:
283  case Mips::BAL_BR:
284  case Mips::BAL_BR_MM:
285  case Mips::BC1F:
286  case Mips::BC1FL:
287  case Mips::BC1T:
288  case Mips::BC1TL:
289  case Mips::BEQ:     case Mips::BEQ64:
290  case Mips::BEQL:
291  case Mips::BGEZ:    case Mips::BGEZ64:
292  case Mips::BGEZL:
293  case Mips::BGEZAL:
294  case Mips::BGEZALL:
295  case Mips::BGTZ:    case Mips::BGTZ64:
296  case Mips::BGTZL:
297  case Mips::BLEZ:    case Mips::BLEZ64:
298  case Mips::BLEZL:
299  case Mips::BLTZ:    case Mips::BLTZ64:
300  case Mips::BLTZL:
301  case Mips::BLTZAL:
302  case Mips::BLTZALL:
303  case Mips::BNE:     case Mips::BNE64:
304  case Mips::BNEL:
305    return isInt<18>(BrOffset);
306
307  // microMIPSr3 branches
308  case Mips::B_MM:
309  case Mips::BC1F_MM:
310  case Mips::BC1T_MM:
311  case Mips::BEQ_MM:
312  case Mips::BGEZ_MM:
313  case Mips::BGEZAL_MM:
314  case Mips::BGTZ_MM:
315  case Mips::BLEZ_MM:
316  case Mips::BLTZ_MM:
317  case Mips::BLTZAL_MM:
318  case Mips::BNE_MM:
319  case Mips::BEQZC_MM:
320  case Mips::BNEZC_MM:
321    return isInt<17>(BrOffset);
322
323  // microMIPSR3 short branches.
324  case Mips::B16_MM:
325    return isInt<11>(BrOffset);
326
327  case Mips::BEQZ16_MM:
328  case Mips::BNEZ16_MM:
329    return isInt<8>(BrOffset);
330
331  // MIPSR6 branches.
332  case Mips::BALC:
333  case Mips::BC:
334    return isInt<28>(BrOffset);
335
336  case Mips::BC1EQZ:
337  case Mips::BC1NEZ:
338  case Mips::BC2EQZ:
339  case Mips::BC2NEZ:
340  case Mips::BEQC:   case Mips::BEQC64:
341  case Mips::BNEC:   case Mips::BNEC64:
342  case Mips::BGEC:   case Mips::BGEC64:
343  case Mips::BGEUC:  case Mips::BGEUC64:
344  case Mips::BGEZC:  case Mips::BGEZC64:
345  case Mips::BGTZC:  case Mips::BGTZC64:
346  case Mips::BLEZC:  case Mips::BLEZC64:
347  case Mips::BLTC:   case Mips::BLTC64:
348  case Mips::BLTUC:  case Mips::BLTUC64:
349  case Mips::BLTZC:  case Mips::BLTZC64:
350  case Mips::BNVC:
351  case Mips::BOVC:
352  case Mips::BGEZALC:
353  case Mips::BEQZALC:
354  case Mips::BGTZALC:
355  case Mips::BLEZALC:
356  case Mips::BLTZALC:
357  case Mips::BNEZALC:
358    return isInt<18>(BrOffset);
359
360  case Mips::BEQZC:  case Mips::BEQZC64:
361  case Mips::BNEZC:  case Mips::BNEZC64:
362    return isInt<23>(BrOffset);
363
364  // microMIPSR6 branches
365  case Mips::BC16_MMR6:
366    return isInt<11>(BrOffset);
367
368  case Mips::BEQZC16_MMR6:
369  case Mips::BNEZC16_MMR6:
370    return isInt<8>(BrOffset);
371
372  case Mips::BALC_MMR6:
373  case Mips::BC_MMR6:
374    return isInt<27>(BrOffset);
375
376  case Mips::BC1EQZC_MMR6:
377  case Mips::BC1NEZC_MMR6:
378  case Mips::BC2EQZC_MMR6:
379  case Mips::BC2NEZC_MMR6:
380  case Mips::BGEZALC_MMR6:
381  case Mips::BEQZALC_MMR6:
382  case Mips::BGTZALC_MMR6:
383  case Mips::BLEZALC_MMR6:
384  case Mips::BLTZALC_MMR6:
385  case Mips::BNEZALC_MMR6:
386  case Mips::BNVC_MMR6:
387  case Mips::BOVC_MMR6:
388    return isInt<17>(BrOffset);
389
390  case Mips::BEQC_MMR6:
391  case Mips::BNEC_MMR6:
392  case Mips::BGEC_MMR6:
393  case Mips::BGEUC_MMR6:
394  case Mips::BGEZC_MMR6:
395  case Mips::BGTZC_MMR6:
396  case Mips::BLEZC_MMR6:
397  case Mips::BLTC_MMR6:
398  case Mips::BLTUC_MMR6:
399  case Mips::BLTZC_MMR6:
400    return isInt<18>(BrOffset);
401
402  case Mips::BEQZC_MMR6:
403  case Mips::BNEZC_MMR6:
404    return isInt<23>(BrOffset);
405
406  // DSP branches.
407  case Mips::BPOSGE32:
408    return isInt<18>(BrOffset);
409  case Mips::BPOSGE32_MM:
410  case Mips::BPOSGE32C_MMR3:
411    return isInt<17>(BrOffset);
412
413  // cnMIPS branches.
414  case Mips::BBIT0:
415  case Mips::BBIT032:
416  case Mips::BBIT1:
417  case Mips::BBIT132:
418    return isInt<18>(BrOffset);
419
420  // MSA branches.
421  case Mips::BZ_B:
422  case Mips::BZ_H:
423  case Mips::BZ_W:
424  case Mips::BZ_D:
425  case Mips::BZ_V:
426  case Mips::BNZ_B:
427  case Mips::BNZ_H:
428  case Mips::BNZ_W:
429  case Mips::BNZ_D:
430  case Mips::BNZ_V:
431    return isInt<18>(BrOffset);
432  }
433
434  llvm_unreachable("Unknown branch instruction!");
435}
436
437/// Return the corresponding compact (no delay slot) form of a branch.
438unsigned MipsInstrInfo::getEquivalentCompactForm(
439    const MachineBasicBlock::iterator I) const {
440  unsigned Opcode = I->getOpcode();
441  bool canUseShortMicroMipsCTI = false;
442
443  if (Subtarget.inMicroMipsMode()) {
444    switch (Opcode) {
445    case Mips::BNE:
446    case Mips::BNE_MM:
447    case Mips::BEQ:
448    case Mips::BEQ_MM:
449    // microMIPS has NE,EQ branches that do not have delay slots provided one
450    // of the operands is zero.
451      if (I->getOperand(1).getReg() == Subtarget.getABI().GetZeroReg())
452        canUseShortMicroMipsCTI = true;
453      break;
454    // For microMIPS the PseudoReturn and PseudoIndirectBranch are always
455    // expanded to JR_MM, so they can be replaced with JRC16_MM.
456    case Mips::JR:
457    case Mips::PseudoReturn:
458    case Mips::PseudoIndirectBranch:
459      canUseShortMicroMipsCTI = true;
460      break;
461    }
462  }
463
464  // MIPSR6 forbids both operands being the zero register.
465  if (Subtarget.hasMips32r6() && (I->getNumOperands() > 1) &&
466      (I->getOperand(0).isReg() &&
467       (I->getOperand(0).getReg() == Mips::ZERO ||
468        I->getOperand(0).getReg() == Mips::ZERO_64)) &&
469      (I->getOperand(1).isReg() &&
470       (I->getOperand(1).getReg() == Mips::ZERO ||
471        I->getOperand(1).getReg() == Mips::ZERO_64)))
472    return 0;
473
474  if (Subtarget.hasMips32r6() || canUseShortMicroMipsCTI) {
475    switch (Opcode) {
476    case Mips::B:
477      return Mips::BC;
478    case Mips::BAL:
479      return Mips::BALC;
480    case Mips::BEQ:
481    case Mips::BEQ_MM:
482      if (canUseShortMicroMipsCTI)
483        return Mips::BEQZC_MM;
484      else if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
485        return 0;
486      return Mips::BEQC;
487    case Mips::BNE:
488    case Mips::BNE_MM:
489      if (canUseShortMicroMipsCTI)
490        return Mips::BNEZC_MM;
491      else if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
492        return 0;
493      return Mips::BNEC;
494    case Mips::BGE:
495      if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
496        return 0;
497      return Mips::BGEC;
498    case Mips::BGEU:
499      if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
500        return 0;
501      return Mips::BGEUC;
502    case Mips::BGEZ:
503      return Mips::BGEZC;
504    case Mips::BGTZ:
505      return Mips::BGTZC;
506    case Mips::BLEZ:
507      return Mips::BLEZC;
508    case Mips::BLT:
509      if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
510        return 0;
511      return Mips::BLTC;
512    case Mips::BLTU:
513      if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
514        return 0;
515      return Mips::BLTUC;
516    case Mips::BLTZ:
517      return Mips::BLTZC;
518    case Mips::BEQ64:
519      if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
520        return 0;
521      return Mips::BEQC64;
522    case Mips::BNE64:
523      if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
524        return 0;
525      return Mips::BNEC64;
526    case Mips::BGTZ64:
527      return Mips::BGTZC64;
528    case Mips::BGEZ64:
529      return Mips::BGEZC64;
530    case Mips::BLTZ64:
531      return Mips::BLTZC64;
532    case Mips::BLEZ64:
533      return Mips::BLEZC64;
534    // For MIPSR6, the instruction 'jic' can be used for these cases. Some
535    // tools will accept 'jrc reg' as an alias for 'jic 0, $reg'.
536    case Mips::JR:
537    case Mips::PseudoIndirectBranchR6:
538    case Mips::PseudoReturn:
539    case Mips::TAILCALLR6REG:
540      if (canUseShortMicroMipsCTI)
541        return Mips::JRC16_MM;
542      return Mips::JIC;
543    case Mips::JALRPseudo:
544      return Mips::JIALC;
545    case Mips::JR64:
546    case Mips::PseudoIndirectBranch64R6:
547    case Mips::PseudoReturn64:
548    case Mips::TAILCALL64R6REG:
549      return Mips::JIC64;
550    case Mips::JALR64Pseudo:
551      return Mips::JIALC64;
552    default:
553      return 0;
554    }
555  }
556
557  return 0;
558}
559
560/// Predicate for distingushing between control transfer instructions and all
561/// other instructions for handling forbidden slots. Consider inline assembly
562/// as unsafe as well.
563bool MipsInstrInfo::SafeInForbiddenSlot(const MachineInstr &MI) const {
564  if (MI.isInlineAsm())
565    return false;
566
567  return (MI.getDesc().TSFlags & MipsII::IsCTI) == 0;
568}
569
570/// Predicate for distingushing instructions that have forbidden slots.
571bool MipsInstrInfo::HasForbiddenSlot(const MachineInstr &MI) const {
572  return (MI.getDesc().TSFlags & MipsII::HasForbiddenSlot) != 0;
573}
574
575/// Return the number of bytes of code the specified instruction may be.
576unsigned MipsInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
577  switch (MI.getOpcode()) {
578  default:
579    return MI.getDesc().getSize();
580  case  TargetOpcode::INLINEASM:
581  case  TargetOpcode::INLINEASM_BR: {       // Inline Asm: Variable size.
582    const MachineFunction *MF = MI.getParent()->getParent();
583    const char *AsmStr = MI.getOperand(0).getSymbolName();
584    return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
585  }
586  case Mips::CONSTPOOL_ENTRY:
587    // If this machine instr is a constant pool entry, its size is recorded as
588    // operand #2.
589    return MI.getOperand(2).getImm();
590  }
591}
592
593MachineInstrBuilder
594MipsInstrInfo::genInstrWithNewOpc(unsigned NewOpc,
595                                  MachineBasicBlock::iterator I) const {
596  MachineInstrBuilder MIB;
597
598  // Certain branches have two forms: e.g beq $1, $zero, dest vs beqz $1, dest
599  // Pick the zero form of the branch for readable assembly and for greater
600  // branch distance in non-microMIPS mode.
601  // Additional MIPSR6 does not permit the use of register $zero for compact
602  // branches.
603  // FIXME: Certain atomic sequences on mips64 generate 32bit references to
604  // Mips::ZERO, which is incorrect. This test should be updated to use
605  // Subtarget.getABI().GetZeroReg() when those atomic sequences and others
606  // are fixed.
607  int ZeroOperandPosition = -1;
608  bool BranchWithZeroOperand = false;
609  if (I->isBranch() && !I->isPseudo()) {
610    auto TRI = I->getParent()->getParent()->getSubtarget().getRegisterInfo();
611    ZeroOperandPosition = I->findRegisterUseOperandIdx(Mips::ZERO, false, TRI);
612    BranchWithZeroOperand = ZeroOperandPosition != -1;
613  }
614
615  if (BranchWithZeroOperand) {
616    switch (NewOpc) {
617    case Mips::BEQC:
618      NewOpc = Mips::BEQZC;
619      break;
620    case Mips::BNEC:
621      NewOpc = Mips::BNEZC;
622      break;
623    case Mips::BGEC:
624      NewOpc = Mips::BGEZC;
625      break;
626    case Mips::BLTC:
627      NewOpc = Mips::BLTZC;
628      break;
629    case Mips::BEQC64:
630      NewOpc = Mips::BEQZC64;
631      break;
632    case Mips::BNEC64:
633      NewOpc = Mips::BNEZC64;
634      break;
635    }
636  }
637
638  MIB = BuildMI(*I->getParent(), I, I->getDebugLoc(), get(NewOpc));
639
640  // For MIPSR6 JI*C requires an immediate 0 as an operand, JIALC(64) an
641  // immediate 0 as an operand and requires the removal of it's implicit-def %ra
642  // implicit operand as copying the implicit operations of the instructio we're
643  // looking at will give us the correct flags.
644  if (NewOpc == Mips::JIC || NewOpc == Mips::JIALC || NewOpc == Mips::JIC64 ||
645      NewOpc == Mips::JIALC64) {
646
647    if (NewOpc == Mips::JIALC || NewOpc == Mips::JIALC64)
648      MIB->RemoveOperand(0);
649
650    for (unsigned J = 0, E = I->getDesc().getNumOperands(); J < E; ++J) {
651      MIB.add(I->getOperand(J));
652    }
653
654    MIB.addImm(0);
655
656    // If I has an MCSymbol operand (used by asm printer, to emit R_MIPS_JALR),
657    // add it to the new instruction.
658    for (unsigned J = I->getDesc().getNumOperands(), E = I->getNumOperands();
659         J < E; ++J) {
660      const MachineOperand &MO = I->getOperand(J);
661      if (MO.isMCSymbol() && (MO.getTargetFlags() & MipsII::MO_JALR))
662        MIB.addSym(MO.getMCSymbol(), MipsII::MO_JALR);
663    }
664
665
666  } else {
667    for (unsigned J = 0, E = I->getDesc().getNumOperands(); J < E; ++J) {
668      if (BranchWithZeroOperand && (unsigned)ZeroOperandPosition == J)
669        continue;
670
671      MIB.add(I->getOperand(J));
672    }
673  }
674
675  MIB.copyImplicitOps(*I);
676  MIB.cloneMemRefs(*I);
677  return MIB;
678}
679
680bool MipsInstrInfo::findCommutedOpIndices(const MachineInstr &MI,
681                                          unsigned &SrcOpIdx1,
682                                          unsigned &SrcOpIdx2) const {
683  assert(!MI.isBundle() &&
684         "TargetInstrInfo::findCommutedOpIndices() can't handle bundles");
685
686  const MCInstrDesc &MCID = MI.getDesc();
687  if (!MCID.isCommutable())
688    return false;
689
690  switch (MI.getOpcode()) {
691  case Mips::DPADD_U_H:
692  case Mips::DPADD_U_W:
693  case Mips::DPADD_U_D:
694  case Mips::DPADD_S_H:
695  case Mips::DPADD_S_W:
696  case Mips::DPADD_S_D:
697    // The first operand is both input and output, so it should not commute
698    if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 2, 3))
699      return false;
700
701    if (!MI.getOperand(SrcOpIdx1).isReg() || !MI.getOperand(SrcOpIdx2).isReg())
702      return false;
703    return true;
704  }
705  return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
706}
707
708// ins, ext, dext*, dins have the following constraints:
709// X <= pos      <  Y
710// X <  size     <= Y
711// X <  pos+size <= Y
712//
713// dinsm and dinsu have the following constraints:
714// X <= pos      <  Y
715// X <= size     <= Y
716// X <  pos+size <= Y
717//
718// The callee of verifyInsExtInstruction however gives the bounds of
719// dins[um] like the other (d)ins (d)ext(um) instructions, so that this
720// function doesn't have to vary it's behaviour based on the instruction
721// being checked.
722static bool verifyInsExtInstruction(const MachineInstr &MI, StringRef &ErrInfo,
723                                    const int64_t PosLow, const int64_t PosHigh,
724                                    const int64_t SizeLow,
725                                    const int64_t SizeHigh,
726                                    const int64_t BothLow,
727                                    const int64_t BothHigh) {
728  MachineOperand MOPos = MI.getOperand(2);
729  if (!MOPos.isImm()) {
730    ErrInfo = "Position is not an immediate!";
731    return false;
732  }
733  int64_t Pos = MOPos.getImm();
734  if (!((PosLow <= Pos) && (Pos < PosHigh))) {
735    ErrInfo = "Position operand is out of range!";
736    return false;
737  }
738
739  MachineOperand MOSize = MI.getOperand(3);
740  if (!MOSize.isImm()) {
741    ErrInfo = "Size operand is not an immediate!";
742    return false;
743  }
744  int64_t Size = MOSize.getImm();
745  if (!((SizeLow < Size) && (Size <= SizeHigh))) {
746    ErrInfo = "Size operand is out of range!";
747    return false;
748  }
749
750  if (!((BothLow < (Pos + Size)) && ((Pos + Size) <= BothHigh))) {
751    ErrInfo = "Position + Size is out of range!";
752    return false;
753  }
754
755  return true;
756}
757
758//  Perform target specific instruction verification.
759bool MipsInstrInfo::verifyInstruction(const MachineInstr &MI,
760                                      StringRef &ErrInfo) const {
761  // Verify that ins and ext instructions are well formed.
762  switch (MI.getOpcode()) {
763    case Mips::EXT:
764    case Mips::EXT_MM:
765    case Mips::INS:
766    case Mips::INS_MM:
767    case Mips::DINS:
768      return verifyInsExtInstruction(MI, ErrInfo, 0, 32, 0, 32, 0, 32);
769    case Mips::DINSM:
770      // The ISA spec has a subtle difference between dinsm and dextm
771      // in that it says:
772      // 2 <= size <= 64 for 'dinsm' but 'dextm' has 32 < size <= 64.
773      // To make the bounds checks similar, the range 1 < size <= 64 is checked
774      // for 'dinsm'.
775      return verifyInsExtInstruction(MI, ErrInfo, 0, 32, 1, 64, 32, 64);
776    case Mips::DINSU:
777      // The ISA spec has a subtle difference between dinsu and dextu in that
778      // the size range of dinsu is specified as 1 <= size <= 32 whereas size
779      // for dextu is 0 < size <= 32. The range checked for dinsu here is
780      // 0 < size <= 32, which is equivalent and similar to dextu.
781      return verifyInsExtInstruction(MI, ErrInfo, 32, 64, 0, 32, 32, 64);
782    case Mips::DEXT:
783      return verifyInsExtInstruction(MI, ErrInfo, 0, 32, 0, 32, 0, 63);
784    case Mips::DEXTM:
785      return verifyInsExtInstruction(MI, ErrInfo, 0, 32, 32, 64, 32, 64);
786    case Mips::DEXTU:
787      return verifyInsExtInstruction(MI, ErrInfo, 32, 64, 0, 32, 32, 64);
788    case Mips::TAILCALLREG:
789    case Mips::PseudoIndirectBranch:
790    case Mips::JR:
791    case Mips::JR64:
792    case Mips::JALR:
793    case Mips::JALR64:
794    case Mips::JALRPseudo:
795      if (!Subtarget.useIndirectJumpsHazard())
796        return true;
797
798      ErrInfo = "invalid instruction when using jump guards!";
799      return false;
800    default:
801      return true;
802  }
803
804  return true;
805}
806
807std::pair<unsigned, unsigned>
808MipsInstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {
809  return std::make_pair(TF, 0u);
810}
811
812ArrayRef<std::pair<unsigned, const char*>>
813MipsInstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
814 using namespace MipsII;
815
816 static const std::pair<unsigned, const char*> Flags[] = {
817    {MO_GOT,          "mips-got"},
818    {MO_GOT_CALL,     "mips-got-call"},
819    {MO_GPREL,        "mips-gprel"},
820    {MO_ABS_HI,       "mips-abs-hi"},
821    {MO_ABS_LO,       "mips-abs-lo"},
822    {MO_TLSGD,        "mips-tlsgd"},
823    {MO_TLSLDM,       "mips-tlsldm"},
824    {MO_DTPREL_HI,    "mips-dtprel-hi"},
825    {MO_DTPREL_LO,    "mips-dtprel-lo"},
826    {MO_GOTTPREL,     "mips-gottprel"},
827    {MO_TPREL_HI,     "mips-tprel-hi"},
828    {MO_TPREL_LO,     "mips-tprel-lo"},
829    {MO_GPOFF_HI,     "mips-gpoff-hi"},
830    {MO_GPOFF_LO,     "mips-gpoff-lo"},
831    {MO_GOT_DISP,     "mips-got-disp"},
832    {MO_GOT_PAGE,     "mips-got-page"},
833    {MO_GOT_OFST,     "mips-got-ofst"},
834    {MO_HIGHER,       "mips-higher"},
835    {MO_HIGHEST,      "mips-highest"},
836    {MO_GOT_HI16,     "mips-got-hi16"},
837    {MO_GOT_LO16,     "mips-got-lo16"},
838    {MO_CALL_HI16,    "mips-call-hi16"},
839    {MO_CALL_LO16,    "mips-call-lo16"},
840    {MO_JALR,         "mips-jalr"}
841  };
842  return makeArrayRef(Flags);
843}
844