HexagonMCCompound.cpp revision 360784
13256Sswallace//=== HexagonMCCompound.cpp - Hexagon Compound checker -------------------===// 23256Sswallace// 33256Sswallace// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 43256Sswallace// See https://llvm.org/LICENSE.txt for license information. 53256Sswallace// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 63256Sswallace// 7652Sjkh//===----------------------------------------------------------------------===// 8652Sjkh// 9652Sjkh// This file is looks at a packet and tries to form compound insns 10652Sjkh// 11652Sjkh//===----------------------------------------------------------------------===// 12652Sjkh 13652Sjkh#include "MCTargetDesc/HexagonBaseInfo.h" 14652Sjkh#include "MCTargetDesc/HexagonMCInstrInfo.h" 15652Sjkh#include "MCTargetDesc/HexagonMCShuffler.h" 16652Sjkh#include "llvm/MC/MCContext.h" 17652Sjkh#include "llvm/MC/MCInst.h" 18652Sjkh#include "llvm/Support/Debug.h" 19805Sache#include "llvm/Support/ErrorHandling.h" 20652Sjkh#include "llvm/Support/raw_ostream.h" 21652Sjkh#include <cassert> 22805Sache#include <cstdint> 23652Sjkh 24652Sjkhusing namespace llvm; 25652Sjkhusing namespace Hexagon; 26652Sjkh 27652Sjkh#define DEBUG_TYPE "hexagon-mccompound" 28652Sjkh 29652Sjkhenum OpcodeIndex { 30652Sjkh fp0_jump_nt = 0, 313256Sswallace fp0_jump_t, 32652Sjkh fp1_jump_nt, 33652Sjkh fp1_jump_t, 34652Sjkh tp0_jump_nt, 35652Sjkh tp0_jump_t, 36652Sjkh tp1_jump_nt, 371258Sswallace tp1_jump_t 38652Sjkh}; 39652Sjkh 40652Sjkhstatic const unsigned tstBitOpcode[8] = { 413256Sswallace J4_tstbit0_fp0_jump_nt, J4_tstbit0_fp0_jump_t, J4_tstbit0_fp1_jump_nt, 42652Sjkh J4_tstbit0_fp1_jump_t, J4_tstbit0_tp0_jump_nt, J4_tstbit0_tp0_jump_t, 43652Sjkh J4_tstbit0_tp1_jump_nt, J4_tstbit0_tp1_jump_t}; 443256Sswallacestatic const unsigned cmpeqBitOpcode[8] = { 451258Sswallace J4_cmpeq_fp0_jump_nt, J4_cmpeq_fp0_jump_t, J4_cmpeq_fp1_jump_nt, 46652Sjkh J4_cmpeq_fp1_jump_t, J4_cmpeq_tp0_jump_nt, J4_cmpeq_tp0_jump_t, 47652Sjkh J4_cmpeq_tp1_jump_nt, J4_cmpeq_tp1_jump_t}; 48652Sjkhstatic const unsigned cmpgtBitOpcode[8] = { 49652Sjkh J4_cmpgt_fp0_jump_nt, J4_cmpgt_fp0_jump_t, J4_cmpgt_fp1_jump_nt, 50652Sjkh J4_cmpgt_fp1_jump_t, J4_cmpgt_tp0_jump_nt, J4_cmpgt_tp0_jump_t, 51652Sjkh J4_cmpgt_tp1_jump_nt, J4_cmpgt_tp1_jump_t}; 52652Sjkhstatic const unsigned cmpgtuBitOpcode[8] = { 533256Sswallace J4_cmpgtu_fp0_jump_nt, J4_cmpgtu_fp0_jump_t, J4_cmpgtu_fp1_jump_nt, 543256Sswallace J4_cmpgtu_fp1_jump_t, J4_cmpgtu_tp0_jump_nt, J4_cmpgtu_tp0_jump_t, 553256Sswallace J4_cmpgtu_tp1_jump_nt, J4_cmpgtu_tp1_jump_t}; 563256Sswallacestatic const unsigned cmpeqiBitOpcode[8] = { 573256Sswallace J4_cmpeqi_fp0_jump_nt, J4_cmpeqi_fp0_jump_t, J4_cmpeqi_fp1_jump_nt, 583256Sswallace J4_cmpeqi_fp1_jump_t, J4_cmpeqi_tp0_jump_nt, J4_cmpeqi_tp0_jump_t, 593256Sswallace J4_cmpeqi_tp1_jump_nt, J4_cmpeqi_tp1_jump_t}; 603256Sswallacestatic const unsigned cmpgtiBitOpcode[8] = { 613256Sswallace J4_cmpgti_fp0_jump_nt, J4_cmpgti_fp0_jump_t, J4_cmpgti_fp1_jump_nt, 623256Sswallace J4_cmpgti_fp1_jump_t, J4_cmpgti_tp0_jump_nt, J4_cmpgti_tp0_jump_t, 633256Sswallace J4_cmpgti_tp1_jump_nt, J4_cmpgti_tp1_jump_t}; 64652Sjkhstatic const unsigned cmpgtuiBitOpcode[8] = { 65652Sjkh J4_cmpgtui_fp0_jump_nt, J4_cmpgtui_fp0_jump_t, J4_cmpgtui_fp1_jump_nt, 66652Sjkh J4_cmpgtui_fp1_jump_t, J4_cmpgtui_tp0_jump_nt, J4_cmpgtui_tp0_jump_t, 67652Sjkh J4_cmpgtui_tp1_jump_nt, J4_cmpgtui_tp1_jump_t}; 68652Sjkhstatic const unsigned cmpeqn1BitOpcode[8] = { 69652Sjkh J4_cmpeqn1_fp0_jump_nt, J4_cmpeqn1_fp0_jump_t, J4_cmpeqn1_fp1_jump_nt, 70652Sjkh J4_cmpeqn1_fp1_jump_t, J4_cmpeqn1_tp0_jump_nt, J4_cmpeqn1_tp0_jump_t, 71652Sjkh J4_cmpeqn1_tp1_jump_nt, J4_cmpeqn1_tp1_jump_t}; 72652Sjkhstatic const unsigned cmpgtn1BitOpcode[8] = { 73652Sjkh J4_cmpgtn1_fp0_jump_nt, J4_cmpgtn1_fp0_jump_t, J4_cmpgtn1_fp1_jump_nt, 74652Sjkh J4_cmpgtn1_fp1_jump_t, J4_cmpgtn1_tp0_jump_nt, J4_cmpgtn1_tp0_jump_t, 75652Sjkh J4_cmpgtn1_tp1_jump_nt, J4_cmpgtn1_tp1_jump_t, 76652Sjkh}; 77652Sjkh 78652Sjkh// enum HexagonII::CompoundGroup 79652Sjkhstatic unsigned getCompoundCandidateGroup(MCInst const &MI, bool IsExtended) { 801258Sswallace unsigned DstReg, SrcReg, Src1Reg, Src2Reg; 811258Sswallace 821258Sswallace switch (MI.getOpcode()) { 83652Sjkh default: 84652Sjkh return HexagonII::HCG_None; 85652Sjkh // 86652Sjkh // Compound pairs. 87652Sjkh // "p0=cmp.eq(Rs16,Rt16); if (p0.new) jump:nt #r9:2" 88652Sjkh // "Rd16=#U6 ; jump #r9:2" 89652Sjkh // "Rd16=Rs16 ; jump #r9:2" 90652Sjkh // 91652Sjkh case Hexagon::C2_cmpeq: 92652Sjkh case Hexagon::C2_cmpgt: 93652Sjkh case Hexagon::C2_cmpgtu: 94652Sjkh if (IsExtended) 95652Sjkh return HexagonII::HCG_None; 96652Sjkh DstReg = MI.getOperand(0).getReg(); 97652Sjkh Src1Reg = MI.getOperand(1).getReg(); 98652Sjkh Src2Reg = MI.getOperand(2).getReg(); 99652Sjkh if ((Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) && 100652Sjkh HexagonMCInstrInfo::isIntRegForSubInst(Src1Reg) && 101652Sjkh HexagonMCInstrInfo::isIntRegForSubInst(Src2Reg)) 102652Sjkh return HexagonII::HCG_A; 103652Sjkh break; 104652Sjkh case Hexagon::C2_cmpeqi: 105652Sjkh case Hexagon::C2_cmpgti: 106652Sjkh case Hexagon::C2_cmpgtui: 107652Sjkh if (IsExtended) 108652Sjkh return HexagonII::HCG_None; 1093256Sswallace // P0 = cmp.eq(Rs,#u2) 110652Sjkh DstReg = MI.getOperand(0).getReg(); 1113256Sswallace SrcReg = MI.getOperand(1).getReg(); 1123256Sswallace if ((Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) && 1133256Sswallace HexagonMCInstrInfo::isIntRegForSubInst(SrcReg) && 1143256Sswallace (HexagonMCInstrInfo::inRange<5>(MI, 2) || 1153256Sswallace HexagonMCInstrInfo::minConstant(MI, 2) == -1)) 1163256Sswallace return HexagonII::HCG_A; 1173256Sswallace break; 1183256Sswallace case Hexagon::A2_tfr: 1193256Sswallace if (IsExtended) 1203256Sswallace return HexagonII::HCG_None; 1213256Sswallace // Rd = Rs 1223256Sswallace DstReg = MI.getOperand(0).getReg(); 1233256Sswallace SrcReg = MI.getOperand(1).getReg(); 1243256Sswallace if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg) && 1253256Sswallace HexagonMCInstrInfo::isIntRegForSubInst(SrcReg)) 126652Sjkh return HexagonII::HCG_A; 127652Sjkh break; 128652Sjkh case Hexagon::A2_tfrsi: 129652Sjkh if (IsExtended) 130652Sjkh return HexagonII::HCG_None; 131652Sjkh // Rd = #u6 132652Sjkh DstReg = MI.getOperand(0).getReg(); 133652Sjkh if (HexagonMCInstrInfo::minConstant(MI, 1) <= 63 && 134652Sjkh HexagonMCInstrInfo::minConstant(MI, 1) >= 0 && 135652Sjkh HexagonMCInstrInfo::isIntRegForSubInst(DstReg)) 136652Sjkh return HexagonII::HCG_A; 137652Sjkh break; 138652Sjkh case Hexagon::S2_tstbit_i: 139652Sjkh if (IsExtended) 140652Sjkh return HexagonII::HCG_None; 141652Sjkh DstReg = MI.getOperand(0).getReg(); 142652Sjkh Src1Reg = MI.getOperand(1).getReg(); 143652Sjkh if ((Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) && 144652Sjkh HexagonMCInstrInfo::isIntRegForSubInst(Src1Reg) && 145652Sjkh HexagonMCInstrInfo::minConstant(MI, 2) == 0) 146652Sjkh return HexagonII::HCG_A; 147652Sjkh break; 148652Sjkh // The fact that .new form is used pretty much guarantees 149652Sjkh // that predicate register will match. Nevertheless, 150652Sjkh // there could be some false positives without additional 151652Sjkh // checking. 152652Sjkh case Hexagon::J2_jumptnew: 153652Sjkh case Hexagon::J2_jumpfnew: 154652Sjkh case Hexagon::J2_jumptnewpt: 155652Sjkh case Hexagon::J2_jumpfnewpt: 156652Sjkh Src1Reg = MI.getOperand(0).getReg(); 157652Sjkh if (Hexagon::P0 == Src1Reg || Hexagon::P1 == Src1Reg) 158652Sjkh return HexagonII::HCG_B; 159652Sjkh break; 160652Sjkh // Transfer and jump: 161652Sjkh // Rd=#U6 ; jump #r9:2 162652Sjkh // Rd=Rs ; jump #r9:2 163652Sjkh // Do not test for jump range here. 164652Sjkh case Hexagon::J2_jump: 165652Sjkh case Hexagon::RESTORE_DEALLOC_RET_JMP_V4: 166652Sjkh return HexagonII::HCG_C; 167652Sjkh break; 168652Sjkh } 169652Sjkh 170652Sjkh return HexagonII::HCG_None; 171652Sjkh} 172652Sjkh 173652Sjkh/// getCompoundOp - Return the index from 0-7 into the above opcode lists. 174652Sjkhstatic unsigned getCompoundOp(MCInst const &HMCI) { 175652Sjkh const MCOperand &Predicate = HMCI.getOperand(0); 176652Sjkh unsigned PredReg = Predicate.getReg(); 177652Sjkh 178652Sjkh assert((PredReg == Hexagon::P0) || (PredReg == Hexagon::P1) || 179652Sjkh (PredReg == Hexagon::P2) || (PredReg == Hexagon::P3)); 180652Sjkh 181652Sjkh switch (HMCI.getOpcode()) { 182652Sjkh default: 183652Sjkh llvm_unreachable("Expected match not found.\n"); 184652Sjkh break; 185652Sjkh case Hexagon::J2_jumpfnew: 186652Sjkh return (PredReg == Hexagon::P0) ? fp0_jump_nt : fp1_jump_nt; 187652Sjkh case Hexagon::J2_jumpfnewpt: 188652Sjkh return (PredReg == Hexagon::P0) ? fp0_jump_t : fp1_jump_t; 189652Sjkh case Hexagon::J2_jumptnew: 190652Sjkh return (PredReg == Hexagon::P0) ? tp0_jump_nt : tp1_jump_nt; 191652Sjkh case Hexagon::J2_jumptnewpt: 192652Sjkh return (PredReg == Hexagon::P0) ? tp0_jump_t : tp1_jump_t; 193652Sjkh } 194652Sjkh} 195652Sjkh 196652Sjkhstatic MCInst *getCompoundInsn(MCContext &Context, MCInst const &L, 197652Sjkh MCInst const &R) { 198652Sjkh MCInst *CompoundInsn = nullptr; 199652Sjkh unsigned compoundOpcode; 200652Sjkh MCOperand Rs, Rt; 201652Sjkh int64_t Value; 202652Sjkh bool Success; 203652Sjkh 204652Sjkh switch (L.getOpcode()) { 205652Sjkh default: 206652Sjkh LLVM_DEBUG(dbgs() << "Possible compound ignored\n"); 207652Sjkh return CompoundInsn; 208652Sjkh 209652Sjkh case Hexagon::A2_tfrsi: 2101258Sswallace Rt = L.getOperand(0); 211652Sjkh compoundOpcode = J4_jumpseti; 212652Sjkh CompoundInsn = new (Context) MCInst; 213652Sjkh CompoundInsn->setOpcode(compoundOpcode); 2143256Sswallace 2153256Sswallace CompoundInsn->addOperand(Rt); 2163256Sswallace CompoundInsn->addOperand(L.getOperand(1)); // Immediate 2173256Sswallace CompoundInsn->addOperand(R.getOperand(0)); // Jump target 2183256Sswallace break; 2193256Sswallace 2203256Sswallace case Hexagon::A2_tfr: 2213256Sswallace Rt = L.getOperand(0); 222652Sjkh Rs = L.getOperand(1); 223652Sjkh 224652Sjkh compoundOpcode = J4_jumpsetr; 225652Sjkh CompoundInsn = new (Context) MCInst; 226652Sjkh CompoundInsn->setOpcode(compoundOpcode); 227652Sjkh CompoundInsn->addOperand(Rt); 228652Sjkh CompoundInsn->addOperand(Rs); 229652Sjkh CompoundInsn->addOperand(R.getOperand(0)); // Jump target. 230652Sjkh 231652Sjkh break; 232652Sjkh 233652Sjkh case Hexagon::C2_cmpeq: 234652Sjkh LLVM_DEBUG(dbgs() << "CX: C2_cmpeq\n"); 235652Sjkh Rs = L.getOperand(1); 236652Sjkh Rt = L.getOperand(2); 237652Sjkh 238652Sjkh compoundOpcode = cmpeqBitOpcode[getCompoundOp(R)]; 239652Sjkh CompoundInsn = new (Context) MCInst; 240652Sjkh CompoundInsn->setOpcode(compoundOpcode); 241652Sjkh CompoundInsn->addOperand(Rs); 242652Sjkh CompoundInsn->addOperand(Rt); 243652Sjkh CompoundInsn->addOperand(R.getOperand(1)); 244652Sjkh break; 245652Sjkh 246652Sjkh case Hexagon::C2_cmpgt: 247652Sjkh LLVM_DEBUG(dbgs() << "CX: C2_cmpgt\n"); 248652Sjkh Rs = L.getOperand(1); 249652Sjkh Rt = L.getOperand(2); 250652Sjkh 251652Sjkh compoundOpcode = cmpgtBitOpcode[getCompoundOp(R)]; 252652Sjkh CompoundInsn = new (Context) MCInst; 253652Sjkh CompoundInsn->setOpcode(compoundOpcode); 254652Sjkh CompoundInsn->addOperand(Rs); 255652Sjkh CompoundInsn->addOperand(Rt); 256652Sjkh CompoundInsn->addOperand(R.getOperand(1)); 257652Sjkh break; 258652Sjkh 259652Sjkh case Hexagon::C2_cmpgtu: 260652Sjkh LLVM_DEBUG(dbgs() << "CX: C2_cmpgtu\n"); 261652Sjkh Rs = L.getOperand(1); 262652Sjkh Rt = L.getOperand(2); 263652Sjkh 264652Sjkh compoundOpcode = cmpgtuBitOpcode[getCompoundOp(R)]; 265652Sjkh CompoundInsn = new (Context) MCInst; 266652Sjkh CompoundInsn->setOpcode(compoundOpcode); 267652Sjkh CompoundInsn->addOperand(Rs); 268652Sjkh CompoundInsn->addOperand(Rt); 269652Sjkh CompoundInsn->addOperand(R.getOperand(1)); 270652Sjkh break; 271652Sjkh 272652Sjkh case Hexagon::C2_cmpeqi: 273652Sjkh LLVM_DEBUG(dbgs() << "CX: C2_cmpeqi\n"); 274652Sjkh Success = L.getOperand(2).getExpr()->evaluateAsAbsolute(Value); 275652Sjkh (void)Success; 276652Sjkh assert(Success); 277652Sjkh if (Value == -1) 278652Sjkh compoundOpcode = cmpeqn1BitOpcode[getCompoundOp(R)]; 279652Sjkh else 280652Sjkh compoundOpcode = cmpeqiBitOpcode[getCompoundOp(R)]; 281652Sjkh 282652Sjkh Rs = L.getOperand(1); 283652Sjkh CompoundInsn = new (Context) MCInst; 284652Sjkh CompoundInsn->setOpcode(compoundOpcode); 285652Sjkh CompoundInsn->addOperand(Rs); 286652Sjkh CompoundInsn->addOperand(L.getOperand(2)); 287652Sjkh CompoundInsn->addOperand(R.getOperand(1)); 288652Sjkh break; 289652Sjkh 290652Sjkh case Hexagon::C2_cmpgti: 291652Sjkh LLVM_DEBUG(dbgs() << "CX: C2_cmpgti\n"); 292652Sjkh Success = L.getOperand(2).getExpr()->evaluateAsAbsolute(Value); 293652Sjkh (void)Success; 294652Sjkh assert(Success); 295652Sjkh if (Value == -1) 296652Sjkh compoundOpcode = cmpgtn1BitOpcode[getCompoundOp(R)]; 297652Sjkh else 298652Sjkh compoundOpcode = cmpgtiBitOpcode[getCompoundOp(R)]; 299652Sjkh 300652Sjkh Rs = L.getOperand(1); 301652Sjkh CompoundInsn = new (Context) MCInst; 302652Sjkh CompoundInsn->setOpcode(compoundOpcode); 303652Sjkh CompoundInsn->addOperand(Rs); 304652Sjkh CompoundInsn->addOperand(L.getOperand(2)); 305652Sjkh CompoundInsn->addOperand(R.getOperand(1)); 306652Sjkh break; 307652Sjkh 308652Sjkh case Hexagon::C2_cmpgtui: 309652Sjkh LLVM_DEBUG(dbgs() << "CX: C2_cmpgtui\n"); 310652Sjkh Rs = L.getOperand(1); 311652Sjkh compoundOpcode = cmpgtuiBitOpcode[getCompoundOp(R)]; 312652Sjkh CompoundInsn = new (Context) MCInst; 313652Sjkh CompoundInsn->setOpcode(compoundOpcode); 314652Sjkh CompoundInsn->addOperand(Rs); 315652Sjkh CompoundInsn->addOperand(L.getOperand(2)); 316652Sjkh CompoundInsn->addOperand(R.getOperand(1)); 3173256Sswallace break; 318652Sjkh 319652Sjkh case Hexagon::S2_tstbit_i: 320652Sjkh LLVM_DEBUG(dbgs() << "CX: S2_tstbit_i\n"); 321652Sjkh Rs = L.getOperand(1); 322652Sjkh compoundOpcode = tstBitOpcode[getCompoundOp(R)]; 323652Sjkh CompoundInsn = new (Context) MCInst; 324652Sjkh CompoundInsn->setOpcode(compoundOpcode); 325652Sjkh CompoundInsn->addOperand(Rs); 326652Sjkh CompoundInsn->addOperand(R.getOperand(1)); 327652Sjkh break; 328652Sjkh } 329652Sjkh 3303256Sswallace return CompoundInsn; 331652Sjkh} 332652Sjkh 3333256Sswallace/// Non-Symmetrical. See if these two instructions are fit for compound pair. 334652Sjkhstatic bool isOrderedCompoundPair(MCInst const &MIa, bool IsExtendedA, 335652Sjkh MCInst const &MIb, bool IsExtendedB) { 336652Sjkh unsigned MIaG = getCompoundCandidateGroup(MIa, IsExtendedA); 3373256Sswallace unsigned MIbG = getCompoundCandidateGroup(MIb, IsExtendedB); 338652Sjkh // We have two candidates - check that this is the same register 339652Sjkh // we are talking about. 3403256Sswallace unsigned Opca = MIa.getOpcode(); 3413256Sswallace if (MIaG == HexagonII::HCG_A && MIbG == HexagonII::HCG_C && 3423256Sswallace (Opca == Hexagon::A2_tfr || Opca == Hexagon::A2_tfrsi)) 3433256Sswallace return true; 3443256Sswallace return ((MIaG == HexagonII::HCG_A && MIbG == HexagonII::HCG_B) && 3453256Sswallace (MIa.getOperand(0).getReg() == MIb.getOperand(0).getReg())); 3463256Sswallace} 3473256Sswallace 3483256Sswallacestatic bool lookForCompound(MCInstrInfo const &MCII, MCContext &Context, 3493256Sswallace MCInst &MCI) { 3503256Sswallace assert(HexagonMCInstrInfo::isBundle(MCI)); 3513256Sswallace bool JExtended = false; 3523256Sswallace for (MCInst::iterator J = 3533256Sswallace MCI.begin() + HexagonMCInstrInfo::bundleInstructionsOffset; 3543256Sswallace J != MCI.end(); ++J) { 3553256Sswallace MCInst const *JumpInst = J->getInst(); 3563256Sswallace if (HexagonMCInstrInfo::isImmext(*JumpInst)) { 3573256Sswallace JExtended = true; 3583256Sswallace continue; 3593256Sswallace } 3603256Sswallace if (HexagonMCInstrInfo::getType(MCII, *JumpInst) == HexagonII::TypeJ) { 3613256Sswallace // Try to pair with another insn (B)undled with jump. 3623256Sswallace bool BExtended = false; 3633256Sswallace for (MCInst::iterator B = 3643256Sswallace MCI.begin() + HexagonMCInstrInfo::bundleInstructionsOffset; 3653256Sswallace B != MCI.end(); ++B) { 3663256Sswallace MCInst const *Inst = B->getInst(); 3673256Sswallace if (JumpInst == Inst) 3683256Sswallace continue; 3693256Sswallace if (HexagonMCInstrInfo::isImmext(*Inst)) { 3703256Sswallace BExtended = true; 3713256Sswallace continue; 3723256Sswallace } 3733256Sswallace LLVM_DEBUG(dbgs() << "J,B: " << JumpInst->getOpcode() << "," 3743256Sswallace << Inst->getOpcode() << "\n"); 3753256Sswallace if (isOrderedCompoundPair(*Inst, BExtended, *JumpInst, JExtended)) { 3763256Sswallace MCInst *CompoundInsn = getCompoundInsn(Context, *Inst, *JumpInst); 3773256Sswallace if (CompoundInsn) { 3783256Sswallace LLVM_DEBUG(dbgs() << "B: " << Inst->getOpcode() << "," 3793256Sswallace << JumpInst->getOpcode() << " Compounds to " 3803256Sswallace << CompoundInsn->getOpcode() << "\n"); 3813256Sswallace J->setInst(CompoundInsn); 3823256Sswallace MCI.erase(B); 3833256Sswallace return true; 3843256Sswallace } 3853256Sswallace } 3863256Sswallace BExtended = false; 3873256Sswallace } 3883256Sswallace } 3893256Sswallace JExtended = false; 3903256Sswallace } 3913256Sswallace return false; 3923256Sswallace} 3933256Sswallace 3943256Sswallace/// tryCompound - Given a bundle check for compound insns when one 3953256Sswallace/// is found update the contents fo the bundle with the compound insn. 3963256Sswallace/// If a compound instruction is found then the bundle will have one 3973256Sswallace/// additional slot. 3983256Sswallacevoid HexagonMCInstrInfo::tryCompound(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, 3993256Sswallace MCContext &Context, MCInst &MCI) { 4003256Sswallace assert(HexagonMCInstrInfo::isBundle(MCI) && 4013256Sswallace "Non-Bundle where Bundle expected"); 4023256Sswallace 4033256Sswallace // By definition a compound must have 2 insn. 4043256Sswallace if (MCI.size() < 2) 4053256Sswallace return; 4063256Sswallace 4073256Sswallace bool StartedValid = llvm::HexagonMCShuffle(Context, false, MCII, STI, MCI); 4083256Sswallace 4093256Sswallace // Create a vector, needed to keep the order of jump instructions. 4103256Sswallace MCInst CheckList(MCI); 4113256Sswallace 4123256Sswallace // Look for compounds until none are found, only update the bundle when 4133256Sswallace // a compound is found. 4143256Sswallace while (lookForCompound(MCII, Context, CheckList)) { 4153256Sswallace // Keep the original bundle around in case the shuffle fails. 4163256Sswallace MCInst OriginalBundle(MCI); 4173256Sswallace 4183256Sswallace // Need to update the bundle. 419652Sjkh MCI = CheckList; 420652Sjkh 4213256Sswallace if (StartedValid && 4223256Sswallace !llvm::HexagonMCShuffle(Context, false, MCII, STI, MCI)) { 423652Sjkh LLVM_DEBUG(dbgs() << "Found ERROR\n"); 4241402Sache MCI = OriginalBundle; 425652Sjkh } 426652Sjkh } 4271402Sache} 4281402Sache