ARMMCInstLower.cpp revision 360784 
1//===-- ARMMCInstLower.cpp - Convert ARM MachineInstr to an MCInst --------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains code to lower ARM MachineInstrs to their corresponding
10// MCInst records.
11//
12//===----------------------------------------------------------------------===//
13
14#include "ARM.h"
15#include "ARMAsmPrinter.h"
16#include "ARMBaseInstrInfo.h"
17#include "ARMMachineFunctionInfo.h"
18#include "ARMSubtarget.h"
19#include "MCTargetDesc/ARMAddressingModes.h"
20#include "MCTargetDesc/ARMBaseInfo.h"
21#include "MCTargetDesc/ARMMCExpr.h"
22#include "llvm/ADT/APFloat.h"
23#include "llvm/CodeGen/MachineBasicBlock.h"
24#include "llvm/CodeGen/MachineInstr.h"
25#include "llvm/CodeGen/MachineOperand.h"
26#include "llvm/IR/Constants.h"
27#include "llvm/MC/MCContext.h"
28#include "llvm/MC/MCExpr.h"
29#include "llvm/MC/MCInst.h"
30#include "llvm/MC/MCInstBuilder.h"
31#include "llvm/MC/MCStreamer.h"
32#include "llvm/Support/ErrorHandling.h"
33#include <cassert>
34#include <cstdint>
35
36using namespace llvm;
37
38MCOperand ARMAsmPrinter::GetSymbolRef(const MachineOperand &MO,
39                                      const MCSymbol *Symbol) {
40  MCSymbolRefExpr::VariantKind SymbolVariant = MCSymbolRefExpr::VK_None;
41  if (MO.getTargetFlags() & ARMII::MO_SBREL)
42    SymbolVariant = MCSymbolRefExpr::VK_ARM_SBREL;
43
44  const MCExpr *Expr =
45      MCSymbolRefExpr::create(Symbol, SymbolVariant, OutContext);
46  switch (MO.getTargetFlags() & ARMII::MO_OPTION_MASK) {
47  default:
48    llvm_unreachable("Unknown target flag on symbol operand");
49  case ARMII::MO_NO_FLAG:
50    break;
51  case ARMII::MO_LO16:
52    Expr =
53        MCSymbolRefExpr::create(Symbol, SymbolVariant, OutContext);
54    Expr = ARMMCExpr::createLower16(Expr, OutContext);
55    break;
56  case ARMII::MO_HI16:
57    Expr =
58        MCSymbolRefExpr::create(Symbol, SymbolVariant, OutContext);
59    Expr = ARMMCExpr::createUpper16(Expr, OutContext);
60    break;
61  }
62
63  if (!MO.isJTI() && MO.getOffset())
64    Expr = MCBinaryExpr::createAdd(Expr,
65                                   MCConstantExpr::create(MO.getOffset(),
66                                                          OutContext),
67                                   OutContext);
68  return MCOperand::createExpr(Expr);
69
70}
71
72bool ARMAsmPrinter::lowerOperand(const MachineOperand &MO,
73                                 MCOperand &MCOp) {
74  switch (MO.getType()) {
75  default: llvm_unreachable("unknown operand type");
76  case MachineOperand::MO_Register:
77    // Ignore all implicit register operands.
78    if (MO.isImplicit())
79      return false;
80    assert(!MO.getSubReg() && "Subregs should be eliminated!");
81    MCOp = MCOperand::createReg(MO.getReg());
82    break;
83  case MachineOperand::MO_Immediate:
84    MCOp = MCOperand::createImm(MO.getImm());
85    break;
86  case MachineOperand::MO_MachineBasicBlock:
87    MCOp = MCOperand::createExpr(MCSymbolRefExpr::create(
88        MO.getMBB()->getSymbol(), OutContext));
89    break;
90  case MachineOperand::MO_GlobalAddress:
91    MCOp = GetSymbolRef(MO,
92                        GetARMGVSymbol(MO.getGlobal(), MO.getTargetFlags()));
93    break;
94  case MachineOperand::MO_ExternalSymbol:
95    MCOp = GetSymbolRef(MO,
96                        GetExternalSymbolSymbol(MO.getSymbolName()));
97    break;
98  case MachineOperand::MO_JumpTableIndex:
99    MCOp = GetSymbolRef(MO, GetJTISymbol(MO.getIndex()));
100    break;
101  case MachineOperand::MO_ConstantPoolIndex:
102    if (Subtarget->genExecuteOnly())
103      llvm_unreachable("execute-only should not generate constant pools");
104    MCOp = GetSymbolRef(MO, GetCPISymbol(MO.getIndex()));
105    break;
106  case MachineOperand::MO_BlockAddress:
107    MCOp = GetSymbolRef(MO, GetBlockAddressSymbol(MO.getBlockAddress()));
108    break;
109  case MachineOperand::MO_FPImmediate: {
110    APFloat Val = MO.getFPImm()->getValueAPF();
111    bool ignored;
112    Val.convert(APFloat::IEEEdouble(), APFloat::rmTowardZero, &ignored);
113    MCOp = MCOperand::createFPImm(Val.convertToDouble());
114    break;
115  }
116  case MachineOperand::MO_RegisterMask:
117    // Ignore call clobbers.
118    return false;
119  }
120  return true;
121}
122
123void llvm::LowerARMMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI,
124                                        ARMAsmPrinter &AP) {
125  OutMI.setOpcode(MI->getOpcode());
126
127  // In the MC layer, we keep modified immediates in their encoded form
128  bool EncodeImms = false;
129  switch (MI->getOpcode()) {
130  default: break;
131  case ARM::MOVi:
132  case ARM::MVNi:
133  case ARM::CMPri:
134  case ARM::CMNri:
135  case ARM::TSTri:
136  case ARM::TEQri:
137  case ARM::MSRi:
138  case ARM::ADCri:
139  case ARM::ADDri:
140  case ARM::ADDSri:
141  case ARM::SBCri:
142  case ARM::SUBri:
143  case ARM::SUBSri:
144  case ARM::ANDri:
145  case ARM::ORRri:
146  case ARM::EORri:
147  case ARM::BICri:
148  case ARM::RSBri:
149  case ARM::RSBSri:
150  case ARM::RSCri:
151    EncodeImms = true;
152    break;
153  }
154
155  for (const MachineOperand &MO : MI->operands()) {
156    MCOperand MCOp;
157    if (AP.lowerOperand(MO, MCOp)) {
158      if (MCOp.isImm() && EncodeImms) {
159        int32_t Enc = ARM_AM::getSOImmVal(MCOp.getImm());
160        if (Enc != -1)
161          MCOp.setImm(Enc);
162      }
163      OutMI.addOperand(MCOp);
164    }
165  }
166}
167
168void ARMAsmPrinter::EmitSled(const MachineInstr &MI, SledKind Kind)
169{
170  if (MI.getParent()->getParent()->getInfo<ARMFunctionInfo>()
171    ->isThumbFunction())
172  {
173    MI.emitError("An attempt to perform XRay instrumentation for a"
174      " Thumb function (not supported). Detected when emitting a sled.");
175    return;
176  }
177  static const int8_t NoopsInSledCount = 6;
178  // We want to emit the following pattern:
179  //
180  // .Lxray_sled_N:
181  //   ALIGN
182  //   B #20
183  //   ; 6 NOP instructions (24 bytes)
184  // .tmpN
185  //
186  // We need the 24 bytes (6 instructions) because at runtime, we'd be patching
187  // over the full 28 bytes (7 instructions) with the following pattern:
188  //
189  //   PUSH{ r0, lr }
190  //   MOVW r0, #<lower 16 bits of function ID>
191  //   MOVT r0, #<higher 16 bits of function ID>
192  //   MOVW ip, #<lower 16 bits of address of __xray_FunctionEntry/Exit>
193  //   MOVT ip, #<higher 16 bits of address of __xray_FunctionEntry/Exit>
194  //   BLX ip
195  //   POP{ r0, lr }
196  //
197  OutStreamer->EmitCodeAlignment(4);
198  auto CurSled = OutContext.createTempSymbol("xray_sled_", true);
199  OutStreamer->EmitLabel(CurSled);
200  auto Target = OutContext.createTempSymbol();
201
202  // Emit "B #20" instruction, which jumps over the next 24 bytes (because
203  // register pc is 8 bytes ahead of the jump instruction by the moment CPU
204  // is executing it).
205  // By analogy to ARMAsmPrinter::emitPseudoExpansionLowering() |case ARM::B|.
206  // It is not clear why |addReg(0)| is needed (the last operand).
207  EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::Bcc).addImm(20)
208    .addImm(ARMCC::AL).addReg(0));
209
210  emitNops(NoopsInSledCount);
211
212  OutStreamer->EmitLabel(Target);
213  recordSled(CurSled, MI, Kind);
214}
215
216void ARMAsmPrinter::LowerPATCHABLE_FUNCTION_ENTER(const MachineInstr &MI)
217{
218  EmitSled(MI, SledKind::FUNCTION_ENTER);
219}
220
221void ARMAsmPrinter::LowerPATCHABLE_FUNCTION_EXIT(const MachineInstr &MI)
222{
223  EmitSled(MI, SledKind::FUNCTION_EXIT);
224}
225
226void ARMAsmPrinter::LowerPATCHABLE_TAIL_CALL(const MachineInstr &MI)
227{
228  EmitSled(MI, SledKind::TAIL_CALL);
229}
230