ARMExpandPseudoInsts.cpp revision 360784
1//===-- ARMExpandPseudoInsts.cpp - Expand pseudo instructions -------------===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file contains a pass that expands pseudo instructions into target 10// instructions to allow proper scheduling, if-conversion, and other late 11// optimizations. This pass should be run after register allocation but before 12// the post-regalloc scheduling pass. 13// 14//===----------------------------------------------------------------------===// 15 16#include "ARM.h" 17#include "ARMBaseInstrInfo.h" 18#include "ARMBaseRegisterInfo.h" 19#include "ARMConstantPoolValue.h" 20#include "ARMMachineFunctionInfo.h" 21#include "ARMSubtarget.h" 22#include "MCTargetDesc/ARMAddressingModes.h" 23#include "llvm/CodeGen/LivePhysRegs.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/CodeGen/MachineFunctionPass.h" 26#include "llvm/Support/Debug.h" 27 28using namespace llvm; 29 30#define DEBUG_TYPE "arm-pseudo" 31 32static cl::opt<bool> 33VerifyARMPseudo("verify-arm-pseudo-expand", cl::Hidden, 34 cl::desc("Verify machine code after expanding ARM pseudos")); 35 36#define ARM_EXPAND_PSEUDO_NAME "ARM pseudo instruction expansion pass" 37 38namespace { 39 class ARMExpandPseudo : public MachineFunctionPass { 40 public: 41 static char ID; 42 ARMExpandPseudo() : MachineFunctionPass(ID) {} 43 44 const ARMBaseInstrInfo *TII; 45 const TargetRegisterInfo *TRI; 46 const ARMSubtarget *STI; 47 ARMFunctionInfo *AFI; 48 49 bool runOnMachineFunction(MachineFunction &Fn) override; 50 51 MachineFunctionProperties getRequiredProperties() const override { 52 return MachineFunctionProperties().set( 53 MachineFunctionProperties::Property::NoVRegs); 54 } 55 56 StringRef getPassName() const override { 57 return ARM_EXPAND_PSEUDO_NAME; 58 } 59 60 private: 61 void TransferImpOps(MachineInstr &OldMI, 62 MachineInstrBuilder &UseMI, MachineInstrBuilder &DefMI); 63 bool ExpandMI(MachineBasicBlock &MBB, 64 MachineBasicBlock::iterator MBBI, 65 MachineBasicBlock::iterator &NextMBBI); 66 bool ExpandMBB(MachineBasicBlock &MBB); 67 void ExpandVLD(MachineBasicBlock::iterator &MBBI); 68 void ExpandVST(MachineBasicBlock::iterator &MBBI); 69 void ExpandLaneOp(MachineBasicBlock::iterator &MBBI); 70 void ExpandVTBL(MachineBasicBlock::iterator &MBBI, 71 unsigned Opc, bool IsExt); 72 void ExpandMOV32BitImm(MachineBasicBlock &MBB, 73 MachineBasicBlock::iterator &MBBI); 74 bool ExpandCMP_SWAP(MachineBasicBlock &MBB, 75 MachineBasicBlock::iterator MBBI, unsigned LdrexOp, 76 unsigned StrexOp, unsigned UxtOp, 77 MachineBasicBlock::iterator &NextMBBI); 78 79 bool ExpandCMP_SWAP_64(MachineBasicBlock &MBB, 80 MachineBasicBlock::iterator MBBI, 81 MachineBasicBlock::iterator &NextMBBI); 82 }; 83 char ARMExpandPseudo::ID = 0; 84} 85 86INITIALIZE_PASS(ARMExpandPseudo, DEBUG_TYPE, ARM_EXPAND_PSEUDO_NAME, false, 87 false) 88 89/// TransferImpOps - Transfer implicit operands on the pseudo instruction to 90/// the instructions created from the expansion. 91void ARMExpandPseudo::TransferImpOps(MachineInstr &OldMI, 92 MachineInstrBuilder &UseMI, 93 MachineInstrBuilder &DefMI) { 94 const MCInstrDesc &Desc = OldMI.getDesc(); 95 for (unsigned i = Desc.getNumOperands(), e = OldMI.getNumOperands(); 96 i != e; ++i) { 97 const MachineOperand &MO = OldMI.getOperand(i); 98 assert(MO.isReg() && MO.getReg()); 99 if (MO.isUse()) 100 UseMI.add(MO); 101 else 102 DefMI.add(MO); 103 } 104} 105 106namespace { 107 // Constants for register spacing in NEON load/store instructions. 108 // For quad-register load-lane and store-lane pseudo instructors, the 109 // spacing is initially assumed to be EvenDblSpc, and that is changed to 110 // OddDblSpc depending on the lane number operand. 111 enum NEONRegSpacing { 112 SingleSpc, 113 SingleLowSpc , // Single spacing, low registers, three and four vectors. 114 SingleHighQSpc, // Single spacing, high registers, four vectors. 115 SingleHighTSpc, // Single spacing, high registers, three vectors. 116 EvenDblSpc, 117 OddDblSpc 118 }; 119 120 // Entries for NEON load/store information table. The table is sorted by 121 // PseudoOpc for fast binary-search lookups. 122 struct NEONLdStTableEntry { 123 uint16_t PseudoOpc; 124 uint16_t RealOpc; 125 bool IsLoad; 126 bool isUpdating; 127 bool hasWritebackOperand; 128 uint8_t RegSpacing; // One of type NEONRegSpacing 129 uint8_t NumRegs; // D registers loaded or stored 130 uint8_t RegElts; // elements per D register; used for lane ops 131 // FIXME: Temporary flag to denote whether the real instruction takes 132 // a single register (like the encoding) or all of the registers in 133 // the list (like the asm syntax and the isel DAG). When all definitions 134 // are converted to take only the single encoded register, this will 135 // go away. 136 bool copyAllListRegs; 137 138 // Comparison methods for binary search of the table. 139 bool operator<(const NEONLdStTableEntry &TE) const { 140 return PseudoOpc < TE.PseudoOpc; 141 } 142 friend bool operator<(const NEONLdStTableEntry &TE, unsigned PseudoOpc) { 143 return TE.PseudoOpc < PseudoOpc; 144 } 145 friend bool LLVM_ATTRIBUTE_UNUSED operator<(unsigned PseudoOpc, 146 const NEONLdStTableEntry &TE) { 147 return PseudoOpc < TE.PseudoOpc; 148 } 149 }; 150} 151 152static const NEONLdStTableEntry NEONLdStTable[] = { 153{ ARM::VLD1LNq16Pseudo, ARM::VLD1LNd16, true, false, false, EvenDblSpc, 1, 4 ,true}, 154{ ARM::VLD1LNq16Pseudo_UPD, ARM::VLD1LNd16_UPD, true, true, true, EvenDblSpc, 1, 4 ,true}, 155{ ARM::VLD1LNq32Pseudo, ARM::VLD1LNd32, true, false, false, EvenDblSpc, 1, 2 ,true}, 156{ ARM::VLD1LNq32Pseudo_UPD, ARM::VLD1LNd32_UPD, true, true, true, EvenDblSpc, 1, 2 ,true}, 157{ ARM::VLD1LNq8Pseudo, ARM::VLD1LNd8, true, false, false, EvenDblSpc, 1, 8 ,true}, 158{ ARM::VLD1LNq8Pseudo_UPD, ARM::VLD1LNd8_UPD, true, true, true, EvenDblSpc, 1, 8 ,true}, 159 160{ ARM::VLD1d16QPseudo, ARM::VLD1d16Q, true, false, false, SingleSpc, 4, 4 ,false}, 161{ ARM::VLD1d16TPseudo, ARM::VLD1d16T, true, false, false, SingleSpc, 3, 4 ,false}, 162{ ARM::VLD1d32QPseudo, ARM::VLD1d32Q, true, false, false, SingleSpc, 4, 2 ,false}, 163{ ARM::VLD1d32TPseudo, ARM::VLD1d32T, true, false, false, SingleSpc, 3, 2 ,false}, 164{ ARM::VLD1d64QPseudo, ARM::VLD1d64Q, true, false, false, SingleSpc, 4, 1 ,false}, 165{ ARM::VLD1d64QPseudoWB_fixed, ARM::VLD1d64Qwb_fixed, true, true, false, SingleSpc, 4, 1 ,false}, 166{ ARM::VLD1d64QPseudoWB_register, ARM::VLD1d64Qwb_register, true, true, true, SingleSpc, 4, 1 ,false}, 167{ ARM::VLD1d64TPseudo, ARM::VLD1d64T, true, false, false, SingleSpc, 3, 1 ,false}, 168{ ARM::VLD1d64TPseudoWB_fixed, ARM::VLD1d64Twb_fixed, true, true, false, SingleSpc, 3, 1 ,false}, 169{ ARM::VLD1d64TPseudoWB_register, ARM::VLD1d64Twb_register, true, true, true, SingleSpc, 3, 1 ,false}, 170{ ARM::VLD1d8QPseudo, ARM::VLD1d8Q, true, false, false, SingleSpc, 4, 8 ,false}, 171{ ARM::VLD1d8TPseudo, ARM::VLD1d8T, true, false, false, SingleSpc, 3, 8 ,false}, 172{ ARM::VLD1q16HighQPseudo, ARM::VLD1d16Q, true, false, false, SingleHighQSpc, 4, 4 ,false}, 173{ ARM::VLD1q16HighTPseudo, ARM::VLD1d16T, true, false, false, SingleHighTSpc, 3, 4 ,false}, 174{ ARM::VLD1q16LowQPseudo_UPD, ARM::VLD1d16Qwb_fixed, true, true, true, SingleLowSpc, 4, 4 ,false}, 175{ ARM::VLD1q16LowTPseudo_UPD, ARM::VLD1d16Twb_fixed, true, true, true, SingleLowSpc, 3, 4 ,false}, 176{ ARM::VLD1q32HighQPseudo, ARM::VLD1d32Q, true, false, false, SingleHighQSpc, 4, 2 ,false}, 177{ ARM::VLD1q32HighTPseudo, ARM::VLD1d32T, true, false, false, SingleHighTSpc, 3, 2 ,false}, 178{ ARM::VLD1q32LowQPseudo_UPD, ARM::VLD1d32Qwb_fixed, true, true, true, SingleLowSpc, 4, 2 ,false}, 179{ ARM::VLD1q32LowTPseudo_UPD, ARM::VLD1d32Twb_fixed, true, true, true, SingleLowSpc, 3, 2 ,false}, 180{ ARM::VLD1q64HighQPseudo, ARM::VLD1d64Q, true, false, false, SingleHighQSpc, 4, 1 ,false}, 181{ ARM::VLD1q64HighTPseudo, ARM::VLD1d64T, true, false, false, SingleHighTSpc, 3, 1 ,false}, 182{ ARM::VLD1q64LowQPseudo_UPD, ARM::VLD1d64Qwb_fixed, true, true, true, SingleLowSpc, 4, 1 ,false}, 183{ ARM::VLD1q64LowTPseudo_UPD, ARM::VLD1d64Twb_fixed, true, true, true, SingleLowSpc, 3, 1 ,false}, 184{ ARM::VLD1q8HighQPseudo, ARM::VLD1d8Q, true, false, false, SingleHighQSpc, 4, 8 ,false}, 185{ ARM::VLD1q8HighTPseudo, ARM::VLD1d8T, true, false, false, SingleHighTSpc, 3, 8 ,false}, 186{ ARM::VLD1q8LowQPseudo_UPD, ARM::VLD1d8Qwb_fixed, true, true, true, SingleLowSpc, 4, 8 ,false}, 187{ ARM::VLD1q8LowTPseudo_UPD, ARM::VLD1d8Twb_fixed, true, true, true, SingleLowSpc, 3, 8 ,false}, 188 189{ ARM::VLD2DUPq16EvenPseudo, ARM::VLD2DUPd16x2, true, false, false, EvenDblSpc, 2, 4 ,false}, 190{ ARM::VLD2DUPq16OddPseudo, ARM::VLD2DUPd16x2, true, false, false, OddDblSpc, 2, 4 ,false}, 191{ ARM::VLD2DUPq32EvenPseudo, ARM::VLD2DUPd32x2, true, false, false, EvenDblSpc, 2, 2 ,false}, 192{ ARM::VLD2DUPq32OddPseudo, ARM::VLD2DUPd32x2, true, false, false, OddDblSpc, 2, 2 ,false}, 193{ ARM::VLD2DUPq8EvenPseudo, ARM::VLD2DUPd8x2, true, false, false, EvenDblSpc, 2, 8 ,false}, 194{ ARM::VLD2DUPq8OddPseudo, ARM::VLD2DUPd8x2, true, false, false, OddDblSpc, 2, 8 ,false}, 195 196{ ARM::VLD2LNd16Pseudo, ARM::VLD2LNd16, true, false, false, SingleSpc, 2, 4 ,true}, 197{ ARM::VLD2LNd16Pseudo_UPD, ARM::VLD2LNd16_UPD, true, true, true, SingleSpc, 2, 4 ,true}, 198{ ARM::VLD2LNd32Pseudo, ARM::VLD2LNd32, true, false, false, SingleSpc, 2, 2 ,true}, 199{ ARM::VLD2LNd32Pseudo_UPD, ARM::VLD2LNd32_UPD, true, true, true, SingleSpc, 2, 2 ,true}, 200{ ARM::VLD2LNd8Pseudo, ARM::VLD2LNd8, true, false, false, SingleSpc, 2, 8 ,true}, 201{ ARM::VLD2LNd8Pseudo_UPD, ARM::VLD2LNd8_UPD, true, true, true, SingleSpc, 2, 8 ,true}, 202{ ARM::VLD2LNq16Pseudo, ARM::VLD2LNq16, true, false, false, EvenDblSpc, 2, 4 ,true}, 203{ ARM::VLD2LNq16Pseudo_UPD, ARM::VLD2LNq16_UPD, true, true, true, EvenDblSpc, 2, 4 ,true}, 204{ ARM::VLD2LNq32Pseudo, ARM::VLD2LNq32, true, false, false, EvenDblSpc, 2, 2 ,true}, 205{ ARM::VLD2LNq32Pseudo_UPD, ARM::VLD2LNq32_UPD, true, true, true, EvenDblSpc, 2, 2 ,true}, 206 207{ ARM::VLD2q16Pseudo, ARM::VLD2q16, true, false, false, SingleSpc, 4, 4 ,false}, 208{ ARM::VLD2q16PseudoWB_fixed, ARM::VLD2q16wb_fixed, true, true, false, SingleSpc, 4, 4 ,false}, 209{ ARM::VLD2q16PseudoWB_register, ARM::VLD2q16wb_register, true, true, true, SingleSpc, 4, 4 ,false}, 210{ ARM::VLD2q32Pseudo, ARM::VLD2q32, true, false, false, SingleSpc, 4, 2 ,false}, 211{ ARM::VLD2q32PseudoWB_fixed, ARM::VLD2q32wb_fixed, true, true, false, SingleSpc, 4, 2 ,false}, 212{ ARM::VLD2q32PseudoWB_register, ARM::VLD2q32wb_register, true, true, true, SingleSpc, 4, 2 ,false}, 213{ ARM::VLD2q8Pseudo, ARM::VLD2q8, true, false, false, SingleSpc, 4, 8 ,false}, 214{ ARM::VLD2q8PseudoWB_fixed, ARM::VLD2q8wb_fixed, true, true, false, SingleSpc, 4, 8 ,false}, 215{ ARM::VLD2q8PseudoWB_register, ARM::VLD2q8wb_register, true, true, true, SingleSpc, 4, 8 ,false}, 216 217{ ARM::VLD3DUPd16Pseudo, ARM::VLD3DUPd16, true, false, false, SingleSpc, 3, 4,true}, 218{ ARM::VLD3DUPd16Pseudo_UPD, ARM::VLD3DUPd16_UPD, true, true, true, SingleSpc, 3, 4,true}, 219{ ARM::VLD3DUPd32Pseudo, ARM::VLD3DUPd32, true, false, false, SingleSpc, 3, 2,true}, 220{ ARM::VLD3DUPd32Pseudo_UPD, ARM::VLD3DUPd32_UPD, true, true, true, SingleSpc, 3, 2,true}, 221{ ARM::VLD3DUPd8Pseudo, ARM::VLD3DUPd8, true, false, false, SingleSpc, 3, 8,true}, 222{ ARM::VLD3DUPd8Pseudo_UPD, ARM::VLD3DUPd8_UPD, true, true, true, SingleSpc, 3, 8,true}, 223{ ARM::VLD3DUPq16EvenPseudo, ARM::VLD3DUPq16, true, false, false, EvenDblSpc, 3, 4 ,true}, 224{ ARM::VLD3DUPq16OddPseudo, ARM::VLD3DUPq16, true, false, false, OddDblSpc, 3, 4 ,true}, 225{ ARM::VLD3DUPq32EvenPseudo, ARM::VLD3DUPq32, true, false, false, EvenDblSpc, 3, 2 ,true}, 226{ ARM::VLD3DUPq32OddPseudo, ARM::VLD3DUPq32, true, false, false, OddDblSpc, 3, 2 ,true}, 227{ ARM::VLD3DUPq8EvenPseudo, ARM::VLD3DUPq8, true, false, false, EvenDblSpc, 3, 8 ,true}, 228{ ARM::VLD3DUPq8OddPseudo, ARM::VLD3DUPq8, true, false, false, OddDblSpc, 3, 8 ,true}, 229 230{ ARM::VLD3LNd16Pseudo, ARM::VLD3LNd16, true, false, false, SingleSpc, 3, 4 ,true}, 231{ ARM::VLD3LNd16Pseudo_UPD, ARM::VLD3LNd16_UPD, true, true, true, SingleSpc, 3, 4 ,true}, 232{ ARM::VLD3LNd32Pseudo, ARM::VLD3LNd32, true, false, false, SingleSpc, 3, 2 ,true}, 233{ ARM::VLD3LNd32Pseudo_UPD, ARM::VLD3LNd32_UPD, true, true, true, SingleSpc, 3, 2 ,true}, 234{ ARM::VLD3LNd8Pseudo, ARM::VLD3LNd8, true, false, false, SingleSpc, 3, 8 ,true}, 235{ ARM::VLD3LNd8Pseudo_UPD, ARM::VLD3LNd8_UPD, true, true, true, SingleSpc, 3, 8 ,true}, 236{ ARM::VLD3LNq16Pseudo, ARM::VLD3LNq16, true, false, false, EvenDblSpc, 3, 4 ,true}, 237{ ARM::VLD3LNq16Pseudo_UPD, ARM::VLD3LNq16_UPD, true, true, true, EvenDblSpc, 3, 4 ,true}, 238{ ARM::VLD3LNq32Pseudo, ARM::VLD3LNq32, true, false, false, EvenDblSpc, 3, 2 ,true}, 239{ ARM::VLD3LNq32Pseudo_UPD, ARM::VLD3LNq32_UPD, true, true, true, EvenDblSpc, 3, 2 ,true}, 240 241{ ARM::VLD3d16Pseudo, ARM::VLD3d16, true, false, false, SingleSpc, 3, 4 ,true}, 242{ ARM::VLD3d16Pseudo_UPD, ARM::VLD3d16_UPD, true, true, true, SingleSpc, 3, 4 ,true}, 243{ ARM::VLD3d32Pseudo, ARM::VLD3d32, true, false, false, SingleSpc, 3, 2 ,true}, 244{ ARM::VLD3d32Pseudo_UPD, ARM::VLD3d32_UPD, true, true, true, SingleSpc, 3, 2 ,true}, 245{ ARM::VLD3d8Pseudo, ARM::VLD3d8, true, false, false, SingleSpc, 3, 8 ,true}, 246{ ARM::VLD3d8Pseudo_UPD, ARM::VLD3d8_UPD, true, true, true, SingleSpc, 3, 8 ,true}, 247 248{ ARM::VLD3q16Pseudo_UPD, ARM::VLD3q16_UPD, true, true, true, EvenDblSpc, 3, 4 ,true}, 249{ ARM::VLD3q16oddPseudo, ARM::VLD3q16, true, false, false, OddDblSpc, 3, 4 ,true}, 250{ ARM::VLD3q16oddPseudo_UPD, ARM::VLD3q16_UPD, true, true, true, OddDblSpc, 3, 4 ,true}, 251{ ARM::VLD3q32Pseudo_UPD, ARM::VLD3q32_UPD, true, true, true, EvenDblSpc, 3, 2 ,true}, 252{ ARM::VLD3q32oddPseudo, ARM::VLD3q32, true, false, false, OddDblSpc, 3, 2 ,true}, 253{ ARM::VLD3q32oddPseudo_UPD, ARM::VLD3q32_UPD, true, true, true, OddDblSpc, 3, 2 ,true}, 254{ ARM::VLD3q8Pseudo_UPD, ARM::VLD3q8_UPD, true, true, true, EvenDblSpc, 3, 8 ,true}, 255{ ARM::VLD3q8oddPseudo, ARM::VLD3q8, true, false, false, OddDblSpc, 3, 8 ,true}, 256{ ARM::VLD3q8oddPseudo_UPD, ARM::VLD3q8_UPD, true, true, true, OddDblSpc, 3, 8 ,true}, 257 258{ ARM::VLD4DUPd16Pseudo, ARM::VLD4DUPd16, true, false, false, SingleSpc, 4, 4,true}, 259{ ARM::VLD4DUPd16Pseudo_UPD, ARM::VLD4DUPd16_UPD, true, true, true, SingleSpc, 4, 4,true}, 260{ ARM::VLD4DUPd32Pseudo, ARM::VLD4DUPd32, true, false, false, SingleSpc, 4, 2,true}, 261{ ARM::VLD4DUPd32Pseudo_UPD, ARM::VLD4DUPd32_UPD, true, true, true, SingleSpc, 4, 2,true}, 262{ ARM::VLD4DUPd8Pseudo, ARM::VLD4DUPd8, true, false, false, SingleSpc, 4, 8,true}, 263{ ARM::VLD4DUPd8Pseudo_UPD, ARM::VLD4DUPd8_UPD, true, true, true, SingleSpc, 4, 8,true}, 264{ ARM::VLD4DUPq16EvenPseudo, ARM::VLD4DUPq16, true, false, false, EvenDblSpc, 4, 4 ,true}, 265{ ARM::VLD4DUPq16OddPseudo, ARM::VLD4DUPq16, true, false, false, OddDblSpc, 4, 4 ,true}, 266{ ARM::VLD4DUPq32EvenPseudo, ARM::VLD4DUPq32, true, false, false, EvenDblSpc, 4, 2 ,true}, 267{ ARM::VLD4DUPq32OddPseudo, ARM::VLD4DUPq32, true, false, false, OddDblSpc, 4, 2 ,true}, 268{ ARM::VLD4DUPq8EvenPseudo, ARM::VLD4DUPq8, true, false, false, EvenDblSpc, 4, 8 ,true}, 269{ ARM::VLD4DUPq8OddPseudo, ARM::VLD4DUPq8, true, false, false, OddDblSpc, 4, 8 ,true}, 270 271{ ARM::VLD4LNd16Pseudo, ARM::VLD4LNd16, true, false, false, SingleSpc, 4, 4 ,true}, 272{ ARM::VLD4LNd16Pseudo_UPD, ARM::VLD4LNd16_UPD, true, true, true, SingleSpc, 4, 4 ,true}, 273{ ARM::VLD4LNd32Pseudo, ARM::VLD4LNd32, true, false, false, SingleSpc, 4, 2 ,true}, 274{ ARM::VLD4LNd32Pseudo_UPD, ARM::VLD4LNd32_UPD, true, true, true, SingleSpc, 4, 2 ,true}, 275{ ARM::VLD4LNd8Pseudo, ARM::VLD4LNd8, true, false, false, SingleSpc, 4, 8 ,true}, 276{ ARM::VLD4LNd8Pseudo_UPD, ARM::VLD4LNd8_UPD, true, true, true, SingleSpc, 4, 8 ,true}, 277{ ARM::VLD4LNq16Pseudo, ARM::VLD4LNq16, true, false, false, EvenDblSpc, 4, 4 ,true}, 278{ ARM::VLD4LNq16Pseudo_UPD, ARM::VLD4LNq16_UPD, true, true, true, EvenDblSpc, 4, 4 ,true}, 279{ ARM::VLD4LNq32Pseudo, ARM::VLD4LNq32, true, false, false, EvenDblSpc, 4, 2 ,true}, 280{ ARM::VLD4LNq32Pseudo_UPD, ARM::VLD4LNq32_UPD, true, true, true, EvenDblSpc, 4, 2 ,true}, 281 282{ ARM::VLD4d16Pseudo, ARM::VLD4d16, true, false, false, SingleSpc, 4, 4 ,true}, 283{ ARM::VLD4d16Pseudo_UPD, ARM::VLD4d16_UPD, true, true, true, SingleSpc, 4, 4 ,true}, 284{ ARM::VLD4d32Pseudo, ARM::VLD4d32, true, false, false, SingleSpc, 4, 2 ,true}, 285{ ARM::VLD4d32Pseudo_UPD, ARM::VLD4d32_UPD, true, true, true, SingleSpc, 4, 2 ,true}, 286{ ARM::VLD4d8Pseudo, ARM::VLD4d8, true, false, false, SingleSpc, 4, 8 ,true}, 287{ ARM::VLD4d8Pseudo_UPD, ARM::VLD4d8_UPD, true, true, true, SingleSpc, 4, 8 ,true}, 288 289{ ARM::VLD4q16Pseudo_UPD, ARM::VLD4q16_UPD, true, true, true, EvenDblSpc, 4, 4 ,true}, 290{ ARM::VLD4q16oddPseudo, ARM::VLD4q16, true, false, false, OddDblSpc, 4, 4 ,true}, 291{ ARM::VLD4q16oddPseudo_UPD, ARM::VLD4q16_UPD, true, true, true, OddDblSpc, 4, 4 ,true}, 292{ ARM::VLD4q32Pseudo_UPD, ARM::VLD4q32_UPD, true, true, true, EvenDblSpc, 4, 2 ,true}, 293{ ARM::VLD4q32oddPseudo, ARM::VLD4q32, true, false, false, OddDblSpc, 4, 2 ,true}, 294{ ARM::VLD4q32oddPseudo_UPD, ARM::VLD4q32_UPD, true, true, true, OddDblSpc, 4, 2 ,true}, 295{ ARM::VLD4q8Pseudo_UPD, ARM::VLD4q8_UPD, true, true, true, EvenDblSpc, 4, 8 ,true}, 296{ ARM::VLD4q8oddPseudo, ARM::VLD4q8, true, false, false, OddDblSpc, 4, 8 ,true}, 297{ ARM::VLD4q8oddPseudo_UPD, ARM::VLD4q8_UPD, true, true, true, OddDblSpc, 4, 8 ,true}, 298 299{ ARM::VST1LNq16Pseudo, ARM::VST1LNd16, false, false, false, EvenDblSpc, 1, 4 ,true}, 300{ ARM::VST1LNq16Pseudo_UPD, ARM::VST1LNd16_UPD, false, true, true, EvenDblSpc, 1, 4 ,true}, 301{ ARM::VST1LNq32Pseudo, ARM::VST1LNd32, false, false, false, EvenDblSpc, 1, 2 ,true}, 302{ ARM::VST1LNq32Pseudo_UPD, ARM::VST1LNd32_UPD, false, true, true, EvenDblSpc, 1, 2 ,true}, 303{ ARM::VST1LNq8Pseudo, ARM::VST1LNd8, false, false, false, EvenDblSpc, 1, 8 ,true}, 304{ ARM::VST1LNq8Pseudo_UPD, ARM::VST1LNd8_UPD, false, true, true, EvenDblSpc, 1, 8 ,true}, 305 306{ ARM::VST1d16QPseudo, ARM::VST1d16Q, false, false, false, SingleSpc, 4, 4 ,false}, 307{ ARM::VST1d16TPseudo, ARM::VST1d16T, false, false, false, SingleSpc, 3, 4 ,false}, 308{ ARM::VST1d32QPseudo, ARM::VST1d32Q, false, false, false, SingleSpc, 4, 2 ,false}, 309{ ARM::VST1d32TPseudo, ARM::VST1d32T, false, false, false, SingleSpc, 3, 2 ,false}, 310{ ARM::VST1d64QPseudo, ARM::VST1d64Q, false, false, false, SingleSpc, 4, 1 ,false}, 311{ ARM::VST1d64QPseudoWB_fixed, ARM::VST1d64Qwb_fixed, false, true, false, SingleSpc, 4, 1 ,false}, 312{ ARM::VST1d64QPseudoWB_register, ARM::VST1d64Qwb_register, false, true, true, SingleSpc, 4, 1 ,false}, 313{ ARM::VST1d64TPseudo, ARM::VST1d64T, false, false, false, SingleSpc, 3, 1 ,false}, 314{ ARM::VST1d64TPseudoWB_fixed, ARM::VST1d64Twb_fixed, false, true, false, SingleSpc, 3, 1 ,false}, 315{ ARM::VST1d64TPseudoWB_register, ARM::VST1d64Twb_register, false, true, true, SingleSpc, 3, 1 ,false}, 316{ ARM::VST1d8QPseudo, ARM::VST1d8Q, false, false, false, SingleSpc, 4, 8 ,false}, 317{ ARM::VST1d8TPseudo, ARM::VST1d8T, false, false, false, SingleSpc, 3, 8 ,false}, 318{ ARM::VST1q16HighQPseudo, ARM::VST1d16Q, false, false, false, SingleHighQSpc, 4, 4 ,false}, 319{ ARM::VST1q16HighTPseudo, ARM::VST1d16T, false, false, false, SingleHighTSpc, 3, 4 ,false}, 320{ ARM::VST1q16LowQPseudo_UPD, ARM::VST1d16Qwb_fixed, false, true, true, SingleLowSpc, 4, 4 ,false}, 321{ ARM::VST1q16LowTPseudo_UPD, ARM::VST1d16Twb_fixed, false, true, true, SingleLowSpc, 3, 4 ,false}, 322{ ARM::VST1q32HighQPseudo, ARM::VST1d32Q, false, false, false, SingleHighQSpc, 4, 2 ,false}, 323{ ARM::VST1q32HighTPseudo, ARM::VST1d32T, false, false, false, SingleHighTSpc, 3, 2 ,false}, 324{ ARM::VST1q32LowQPseudo_UPD, ARM::VST1d32Qwb_fixed, false, true, true, SingleLowSpc, 4, 2 ,false}, 325{ ARM::VST1q32LowTPseudo_UPD, ARM::VST1d32Twb_fixed, false, true, true, SingleLowSpc, 3, 2 ,false}, 326{ ARM::VST1q64HighQPseudo, ARM::VST1d64Q, false, false, false, SingleHighQSpc, 4, 1 ,false}, 327{ ARM::VST1q64HighTPseudo, ARM::VST1d64T, false, false, false, SingleHighTSpc, 3, 1 ,false}, 328{ ARM::VST1q64LowQPseudo_UPD, ARM::VST1d64Qwb_fixed, false, true, true, SingleLowSpc, 4, 1 ,false}, 329{ ARM::VST1q64LowTPseudo_UPD, ARM::VST1d64Twb_fixed, false, true, true, SingleLowSpc, 3, 1 ,false}, 330{ ARM::VST1q8HighQPseudo, ARM::VST1d8Q, false, false, false, SingleHighQSpc, 4, 8 ,false}, 331{ ARM::VST1q8HighTPseudo, ARM::VST1d8T, false, false, false, SingleHighTSpc, 3, 8 ,false}, 332{ ARM::VST1q8LowQPseudo_UPD, ARM::VST1d8Qwb_fixed, false, true, true, SingleLowSpc, 4, 8 ,false}, 333{ ARM::VST1q8LowTPseudo_UPD, ARM::VST1d8Twb_fixed, false, true, true, SingleLowSpc, 3, 8 ,false}, 334 335{ ARM::VST2LNd16Pseudo, ARM::VST2LNd16, false, false, false, SingleSpc, 2, 4 ,true}, 336{ ARM::VST2LNd16Pseudo_UPD, ARM::VST2LNd16_UPD, false, true, true, SingleSpc, 2, 4 ,true}, 337{ ARM::VST2LNd32Pseudo, ARM::VST2LNd32, false, false, false, SingleSpc, 2, 2 ,true}, 338{ ARM::VST2LNd32Pseudo_UPD, ARM::VST2LNd32_UPD, false, true, true, SingleSpc, 2, 2 ,true}, 339{ ARM::VST2LNd8Pseudo, ARM::VST2LNd8, false, false, false, SingleSpc, 2, 8 ,true}, 340{ ARM::VST2LNd8Pseudo_UPD, ARM::VST2LNd8_UPD, false, true, true, SingleSpc, 2, 8 ,true}, 341{ ARM::VST2LNq16Pseudo, ARM::VST2LNq16, false, false, false, EvenDblSpc, 2, 4,true}, 342{ ARM::VST2LNq16Pseudo_UPD, ARM::VST2LNq16_UPD, false, true, true, EvenDblSpc, 2, 4,true}, 343{ ARM::VST2LNq32Pseudo, ARM::VST2LNq32, false, false, false, EvenDblSpc, 2, 2,true}, 344{ ARM::VST2LNq32Pseudo_UPD, ARM::VST2LNq32_UPD, false, true, true, EvenDblSpc, 2, 2,true}, 345 346{ ARM::VST2q16Pseudo, ARM::VST2q16, false, false, false, SingleSpc, 4, 4 ,false}, 347{ ARM::VST2q16PseudoWB_fixed, ARM::VST2q16wb_fixed, false, true, false, SingleSpc, 4, 4 ,false}, 348{ ARM::VST2q16PseudoWB_register, ARM::VST2q16wb_register, false, true, true, SingleSpc, 4, 4 ,false}, 349{ ARM::VST2q32Pseudo, ARM::VST2q32, false, false, false, SingleSpc, 4, 2 ,false}, 350{ ARM::VST2q32PseudoWB_fixed, ARM::VST2q32wb_fixed, false, true, false, SingleSpc, 4, 2 ,false}, 351{ ARM::VST2q32PseudoWB_register, ARM::VST2q32wb_register, false, true, true, SingleSpc, 4, 2 ,false}, 352{ ARM::VST2q8Pseudo, ARM::VST2q8, false, false, false, SingleSpc, 4, 8 ,false}, 353{ ARM::VST2q8PseudoWB_fixed, ARM::VST2q8wb_fixed, false, true, false, SingleSpc, 4, 8 ,false}, 354{ ARM::VST2q8PseudoWB_register, ARM::VST2q8wb_register, false, true, true, SingleSpc, 4, 8 ,false}, 355 356{ ARM::VST3LNd16Pseudo, ARM::VST3LNd16, false, false, false, SingleSpc, 3, 4 ,true}, 357{ ARM::VST3LNd16Pseudo_UPD, ARM::VST3LNd16_UPD, false, true, true, SingleSpc, 3, 4 ,true}, 358{ ARM::VST3LNd32Pseudo, ARM::VST3LNd32, false, false, false, SingleSpc, 3, 2 ,true}, 359{ ARM::VST3LNd32Pseudo_UPD, ARM::VST3LNd32_UPD, false, true, true, SingleSpc, 3, 2 ,true}, 360{ ARM::VST3LNd8Pseudo, ARM::VST3LNd8, false, false, false, SingleSpc, 3, 8 ,true}, 361{ ARM::VST3LNd8Pseudo_UPD, ARM::VST3LNd8_UPD, false, true, true, SingleSpc, 3, 8 ,true}, 362{ ARM::VST3LNq16Pseudo, ARM::VST3LNq16, false, false, false, EvenDblSpc, 3, 4,true}, 363{ ARM::VST3LNq16Pseudo_UPD, ARM::VST3LNq16_UPD, false, true, true, EvenDblSpc, 3, 4,true}, 364{ ARM::VST3LNq32Pseudo, ARM::VST3LNq32, false, false, false, EvenDblSpc, 3, 2,true}, 365{ ARM::VST3LNq32Pseudo_UPD, ARM::VST3LNq32_UPD, false, true, true, EvenDblSpc, 3, 2,true}, 366 367{ ARM::VST3d16Pseudo, ARM::VST3d16, false, false, false, SingleSpc, 3, 4 ,true}, 368{ ARM::VST3d16Pseudo_UPD, ARM::VST3d16_UPD, false, true, true, SingleSpc, 3, 4 ,true}, 369{ ARM::VST3d32Pseudo, ARM::VST3d32, false, false, false, SingleSpc, 3, 2 ,true}, 370{ ARM::VST3d32Pseudo_UPD, ARM::VST3d32_UPD, false, true, true, SingleSpc, 3, 2 ,true}, 371{ ARM::VST3d8Pseudo, ARM::VST3d8, false, false, false, SingleSpc, 3, 8 ,true}, 372{ ARM::VST3d8Pseudo_UPD, ARM::VST3d8_UPD, false, true, true, SingleSpc, 3, 8 ,true}, 373 374{ ARM::VST3q16Pseudo_UPD, ARM::VST3q16_UPD, false, true, true, EvenDblSpc, 3, 4 ,true}, 375{ ARM::VST3q16oddPseudo, ARM::VST3q16, false, false, false, OddDblSpc, 3, 4 ,true}, 376{ ARM::VST3q16oddPseudo_UPD, ARM::VST3q16_UPD, false, true, true, OddDblSpc, 3, 4 ,true}, 377{ ARM::VST3q32Pseudo_UPD, ARM::VST3q32_UPD, false, true, true, EvenDblSpc, 3, 2 ,true}, 378{ ARM::VST3q32oddPseudo, ARM::VST3q32, false, false, false, OddDblSpc, 3, 2 ,true}, 379{ ARM::VST3q32oddPseudo_UPD, ARM::VST3q32_UPD, false, true, true, OddDblSpc, 3, 2 ,true}, 380{ ARM::VST3q8Pseudo_UPD, ARM::VST3q8_UPD, false, true, true, EvenDblSpc, 3, 8 ,true}, 381{ ARM::VST3q8oddPseudo, ARM::VST3q8, false, false, false, OddDblSpc, 3, 8 ,true}, 382{ ARM::VST3q8oddPseudo_UPD, ARM::VST3q8_UPD, false, true, true, OddDblSpc, 3, 8 ,true}, 383 384{ ARM::VST4LNd16Pseudo, ARM::VST4LNd16, false, false, false, SingleSpc, 4, 4 ,true}, 385{ ARM::VST4LNd16Pseudo_UPD, ARM::VST4LNd16_UPD, false, true, true, SingleSpc, 4, 4 ,true}, 386{ ARM::VST4LNd32Pseudo, ARM::VST4LNd32, false, false, false, SingleSpc, 4, 2 ,true}, 387{ ARM::VST4LNd32Pseudo_UPD, ARM::VST4LNd32_UPD, false, true, true, SingleSpc, 4, 2 ,true}, 388{ ARM::VST4LNd8Pseudo, ARM::VST4LNd8, false, false, false, SingleSpc, 4, 8 ,true}, 389{ ARM::VST4LNd8Pseudo_UPD, ARM::VST4LNd8_UPD, false, true, true, SingleSpc, 4, 8 ,true}, 390{ ARM::VST4LNq16Pseudo, ARM::VST4LNq16, false, false, false, EvenDblSpc, 4, 4,true}, 391{ ARM::VST4LNq16Pseudo_UPD, ARM::VST4LNq16_UPD, false, true, true, EvenDblSpc, 4, 4,true}, 392{ ARM::VST4LNq32Pseudo, ARM::VST4LNq32, false, false, false, EvenDblSpc, 4, 2,true}, 393{ ARM::VST4LNq32Pseudo_UPD, ARM::VST4LNq32_UPD, false, true, true, EvenDblSpc, 4, 2,true}, 394 395{ ARM::VST4d16Pseudo, ARM::VST4d16, false, false, false, SingleSpc, 4, 4 ,true}, 396{ ARM::VST4d16Pseudo_UPD, ARM::VST4d16_UPD, false, true, true, SingleSpc, 4, 4 ,true}, 397{ ARM::VST4d32Pseudo, ARM::VST4d32, false, false, false, SingleSpc, 4, 2 ,true}, 398{ ARM::VST4d32Pseudo_UPD, ARM::VST4d32_UPD, false, true, true, SingleSpc, 4, 2 ,true}, 399{ ARM::VST4d8Pseudo, ARM::VST4d8, false, false, false, SingleSpc, 4, 8 ,true}, 400{ ARM::VST4d8Pseudo_UPD, ARM::VST4d8_UPD, false, true, true, SingleSpc, 4, 8 ,true}, 401 402{ ARM::VST4q16Pseudo_UPD, ARM::VST4q16_UPD, false, true, true, EvenDblSpc, 4, 4 ,true}, 403{ ARM::VST4q16oddPseudo, ARM::VST4q16, false, false, false, OddDblSpc, 4, 4 ,true}, 404{ ARM::VST4q16oddPseudo_UPD, ARM::VST4q16_UPD, false, true, true, OddDblSpc, 4, 4 ,true}, 405{ ARM::VST4q32Pseudo_UPD, ARM::VST4q32_UPD, false, true, true, EvenDblSpc, 4, 2 ,true}, 406{ ARM::VST4q32oddPseudo, ARM::VST4q32, false, false, false, OddDblSpc, 4, 2 ,true}, 407{ ARM::VST4q32oddPseudo_UPD, ARM::VST4q32_UPD, false, true, true, OddDblSpc, 4, 2 ,true}, 408{ ARM::VST4q8Pseudo_UPD, ARM::VST4q8_UPD, false, true, true, EvenDblSpc, 4, 8 ,true}, 409{ ARM::VST4q8oddPseudo, ARM::VST4q8, false, false, false, OddDblSpc, 4, 8 ,true}, 410{ ARM::VST4q8oddPseudo_UPD, ARM::VST4q8_UPD, false, true, true, OddDblSpc, 4, 8 ,true} 411}; 412 413/// LookupNEONLdSt - Search the NEONLdStTable for information about a NEON 414/// load or store pseudo instruction. 415static const NEONLdStTableEntry *LookupNEONLdSt(unsigned Opcode) { 416#ifndef NDEBUG 417 // Make sure the table is sorted. 418 static std::atomic<bool> TableChecked(false); 419 if (!TableChecked.load(std::memory_order_relaxed)) { 420 assert(std::is_sorted(std::begin(NEONLdStTable), std::end(NEONLdStTable)) && 421 "NEONLdStTable is not sorted!"); 422 TableChecked.store(true, std::memory_order_relaxed); 423 } 424#endif 425 426 auto I = llvm::lower_bound(NEONLdStTable, Opcode); 427 if (I != std::end(NEONLdStTable) && I->PseudoOpc == Opcode) 428 return I; 429 return nullptr; 430} 431 432/// GetDSubRegs - Get 4 D subregisters of a Q, QQ, or QQQQ register, 433/// corresponding to the specified register spacing. Not all of the results 434/// are necessarily valid, e.g., a Q register only has 2 D subregisters. 435static void GetDSubRegs(unsigned Reg, NEONRegSpacing RegSpc, 436 const TargetRegisterInfo *TRI, unsigned &D0, 437 unsigned &D1, unsigned &D2, unsigned &D3) { 438 if (RegSpc == SingleSpc || RegSpc == SingleLowSpc) { 439 D0 = TRI->getSubReg(Reg, ARM::dsub_0); 440 D1 = TRI->getSubReg(Reg, ARM::dsub_1); 441 D2 = TRI->getSubReg(Reg, ARM::dsub_2); 442 D3 = TRI->getSubReg(Reg, ARM::dsub_3); 443 } else if (RegSpc == SingleHighQSpc) { 444 D0 = TRI->getSubReg(Reg, ARM::dsub_4); 445 D1 = TRI->getSubReg(Reg, ARM::dsub_5); 446 D2 = TRI->getSubReg(Reg, ARM::dsub_6); 447 D3 = TRI->getSubReg(Reg, ARM::dsub_7); 448 } else if (RegSpc == SingleHighTSpc) { 449 D0 = TRI->getSubReg(Reg, ARM::dsub_3); 450 D1 = TRI->getSubReg(Reg, ARM::dsub_4); 451 D2 = TRI->getSubReg(Reg, ARM::dsub_5); 452 D3 = TRI->getSubReg(Reg, ARM::dsub_6); 453 } else if (RegSpc == EvenDblSpc) { 454 D0 = TRI->getSubReg(Reg, ARM::dsub_0); 455 D1 = TRI->getSubReg(Reg, ARM::dsub_2); 456 D2 = TRI->getSubReg(Reg, ARM::dsub_4); 457 D3 = TRI->getSubReg(Reg, ARM::dsub_6); 458 } else { 459 assert(RegSpc == OddDblSpc && "unknown register spacing"); 460 D0 = TRI->getSubReg(Reg, ARM::dsub_1); 461 D1 = TRI->getSubReg(Reg, ARM::dsub_3); 462 D2 = TRI->getSubReg(Reg, ARM::dsub_5); 463 D3 = TRI->getSubReg(Reg, ARM::dsub_7); 464 } 465} 466 467/// ExpandVLD - Translate VLD pseudo instructions with Q, QQ or QQQQ register 468/// operands to real VLD instructions with D register operands. 469void ARMExpandPseudo::ExpandVLD(MachineBasicBlock::iterator &MBBI) { 470 MachineInstr &MI = *MBBI; 471 MachineBasicBlock &MBB = *MI.getParent(); 472 LLVM_DEBUG(dbgs() << "Expanding: "; MI.dump()); 473 474 const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode()); 475 assert(TableEntry && TableEntry->IsLoad && "NEONLdStTable lookup failed"); 476 NEONRegSpacing RegSpc = (NEONRegSpacing)TableEntry->RegSpacing; 477 unsigned NumRegs = TableEntry->NumRegs; 478 479 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), 480 TII->get(TableEntry->RealOpc)); 481 unsigned OpIdx = 0; 482 483 bool DstIsDead = MI.getOperand(OpIdx).isDead(); 484 Register DstReg = MI.getOperand(OpIdx++).getReg(); 485 if(TableEntry->RealOpc == ARM::VLD2DUPd8x2 || 486 TableEntry->RealOpc == ARM::VLD2DUPd16x2 || 487 TableEntry->RealOpc == ARM::VLD2DUPd32x2) { 488 unsigned SubRegIndex; 489 if (RegSpc == EvenDblSpc) { 490 SubRegIndex = ARM::dsub_0; 491 } else { 492 assert(RegSpc == OddDblSpc && "Unexpected spacing!"); 493 SubRegIndex = ARM::dsub_1; 494 } 495 Register SubReg = TRI->getSubReg(DstReg, SubRegIndex); 496 unsigned DstRegPair = TRI->getMatchingSuperReg(SubReg, ARM::dsub_0, 497 &ARM::DPairSpcRegClass); 498 MIB.addReg(DstRegPair, RegState::Define | getDeadRegState(DstIsDead)); 499 } else { 500 unsigned D0, D1, D2, D3; 501 GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3); 502 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)); 503 if (NumRegs > 1 && TableEntry->copyAllListRegs) 504 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); 505 if (NumRegs > 2 && TableEntry->copyAllListRegs) 506 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead)); 507 if (NumRegs > 3 && TableEntry->copyAllListRegs) 508 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead)); 509 } 510 511 if (TableEntry->isUpdating) 512 MIB.add(MI.getOperand(OpIdx++)); 513 514 // Copy the addrmode6 operands. 515 MIB.add(MI.getOperand(OpIdx++)); 516 MIB.add(MI.getOperand(OpIdx++)); 517 518 // Copy the am6offset operand. 519 if (TableEntry->hasWritebackOperand) { 520 // TODO: The writing-back pseudo instructions we translate here are all 521 // defined to take am6offset nodes that are capable to represent both fixed 522 // and register forms. Some real instructions, however, do not rely on 523 // am6offset and have separate definitions for such forms. When this is the 524 // case, fixed forms do not take any offset nodes, so here we skip them for 525 // such instructions. Once all real and pseudo writing-back instructions are 526 // rewritten without use of am6offset nodes, this code will go away. 527 const MachineOperand &AM6Offset = MI.getOperand(OpIdx++); 528 if (TableEntry->RealOpc == ARM::VLD1d8Qwb_fixed || 529 TableEntry->RealOpc == ARM::VLD1d16Qwb_fixed || 530 TableEntry->RealOpc == ARM::VLD1d32Qwb_fixed || 531 TableEntry->RealOpc == ARM::VLD1d64Qwb_fixed || 532 TableEntry->RealOpc == ARM::VLD1d8Twb_fixed || 533 TableEntry->RealOpc == ARM::VLD1d16Twb_fixed || 534 TableEntry->RealOpc == ARM::VLD1d32Twb_fixed || 535 TableEntry->RealOpc == ARM::VLD1d64Twb_fixed) { 536 assert(AM6Offset.getReg() == 0 && 537 "A fixed writing-back pseudo instruction provides an offset " 538 "register!"); 539 } else { 540 MIB.add(AM6Offset); 541 } 542 } 543 544 // For an instruction writing double-spaced subregs, the pseudo instruction 545 // has an extra operand that is a use of the super-register. Record the 546 // operand index and skip over it. 547 unsigned SrcOpIdx = 0; 548 if(TableEntry->RealOpc != ARM::VLD2DUPd8x2 && 549 TableEntry->RealOpc != ARM::VLD2DUPd16x2 && 550 TableEntry->RealOpc != ARM::VLD2DUPd32x2) { 551 if (RegSpc == EvenDblSpc || RegSpc == OddDblSpc || 552 RegSpc == SingleLowSpc || RegSpc == SingleHighQSpc || 553 RegSpc == SingleHighTSpc) 554 SrcOpIdx = OpIdx++; 555 } 556 557 // Copy the predicate operands. 558 MIB.add(MI.getOperand(OpIdx++)); 559 MIB.add(MI.getOperand(OpIdx++)); 560 561 // Copy the super-register source operand used for double-spaced subregs over 562 // to the new instruction as an implicit operand. 563 if (SrcOpIdx != 0) { 564 MachineOperand MO = MI.getOperand(SrcOpIdx); 565 MO.setImplicit(true); 566 MIB.add(MO); 567 } 568 // Add an implicit def for the super-register. 569 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); 570 TransferImpOps(MI, MIB, MIB); 571 572 // Transfer memoperands. 573 MIB.cloneMemRefs(MI); 574 MI.eraseFromParent(); 575 LLVM_DEBUG(dbgs() << "To: "; MIB.getInstr()->dump();); 576} 577 578/// ExpandVST - Translate VST pseudo instructions with Q, QQ or QQQQ register 579/// operands to real VST instructions with D register operands. 580void ARMExpandPseudo::ExpandVST(MachineBasicBlock::iterator &MBBI) { 581 MachineInstr &MI = *MBBI; 582 MachineBasicBlock &MBB = *MI.getParent(); 583 LLVM_DEBUG(dbgs() << "Expanding: "; MI.dump()); 584 585 const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode()); 586 assert(TableEntry && !TableEntry->IsLoad && "NEONLdStTable lookup failed"); 587 NEONRegSpacing RegSpc = (NEONRegSpacing)TableEntry->RegSpacing; 588 unsigned NumRegs = TableEntry->NumRegs; 589 590 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), 591 TII->get(TableEntry->RealOpc)); 592 unsigned OpIdx = 0; 593 if (TableEntry->isUpdating) 594 MIB.add(MI.getOperand(OpIdx++)); 595 596 // Copy the addrmode6 operands. 597 MIB.add(MI.getOperand(OpIdx++)); 598 MIB.add(MI.getOperand(OpIdx++)); 599 600 if (TableEntry->hasWritebackOperand) { 601 // TODO: The writing-back pseudo instructions we translate here are all 602 // defined to take am6offset nodes that are capable to represent both fixed 603 // and register forms. Some real instructions, however, do not rely on 604 // am6offset and have separate definitions for such forms. When this is the 605 // case, fixed forms do not take any offset nodes, so here we skip them for 606 // such instructions. Once all real and pseudo writing-back instructions are 607 // rewritten without use of am6offset nodes, this code will go away. 608 const MachineOperand &AM6Offset = MI.getOperand(OpIdx++); 609 if (TableEntry->RealOpc == ARM::VST1d8Qwb_fixed || 610 TableEntry->RealOpc == ARM::VST1d16Qwb_fixed || 611 TableEntry->RealOpc == ARM::VST1d32Qwb_fixed || 612 TableEntry->RealOpc == ARM::VST1d64Qwb_fixed || 613 TableEntry->RealOpc == ARM::VST1d8Twb_fixed || 614 TableEntry->RealOpc == ARM::VST1d16Twb_fixed || 615 TableEntry->RealOpc == ARM::VST1d32Twb_fixed || 616 TableEntry->RealOpc == ARM::VST1d64Twb_fixed) { 617 assert(AM6Offset.getReg() == 0 && 618 "A fixed writing-back pseudo instruction provides an offset " 619 "register!"); 620 } else { 621 MIB.add(AM6Offset); 622 } 623 } 624 625 bool SrcIsKill = MI.getOperand(OpIdx).isKill(); 626 bool SrcIsUndef = MI.getOperand(OpIdx).isUndef(); 627 Register SrcReg = MI.getOperand(OpIdx++).getReg(); 628 unsigned D0, D1, D2, D3; 629 GetDSubRegs(SrcReg, RegSpc, TRI, D0, D1, D2, D3); 630 MIB.addReg(D0, getUndefRegState(SrcIsUndef)); 631 if (NumRegs > 1 && TableEntry->copyAllListRegs) 632 MIB.addReg(D1, getUndefRegState(SrcIsUndef)); 633 if (NumRegs > 2 && TableEntry->copyAllListRegs) 634 MIB.addReg(D2, getUndefRegState(SrcIsUndef)); 635 if (NumRegs > 3 && TableEntry->copyAllListRegs) 636 MIB.addReg(D3, getUndefRegState(SrcIsUndef)); 637 638 // Copy the predicate operands. 639 MIB.add(MI.getOperand(OpIdx++)); 640 MIB.add(MI.getOperand(OpIdx++)); 641 642 if (SrcIsKill && !SrcIsUndef) // Add an implicit kill for the super-reg. 643 MIB->addRegisterKilled(SrcReg, TRI, true); 644 else if (!SrcIsUndef) 645 MIB.addReg(SrcReg, RegState::Implicit); // Add implicit uses for src reg. 646 TransferImpOps(MI, MIB, MIB); 647 648 // Transfer memoperands. 649 MIB.cloneMemRefs(MI); 650 MI.eraseFromParent(); 651 LLVM_DEBUG(dbgs() << "To: "; MIB.getInstr()->dump();); 652} 653 654/// ExpandLaneOp - Translate VLD*LN and VST*LN instructions with Q, QQ or QQQQ 655/// register operands to real instructions with D register operands. 656void ARMExpandPseudo::ExpandLaneOp(MachineBasicBlock::iterator &MBBI) { 657 MachineInstr &MI = *MBBI; 658 MachineBasicBlock &MBB = *MI.getParent(); 659 LLVM_DEBUG(dbgs() << "Expanding: "; MI.dump()); 660 661 const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode()); 662 assert(TableEntry && "NEONLdStTable lookup failed"); 663 NEONRegSpacing RegSpc = (NEONRegSpacing)TableEntry->RegSpacing; 664 unsigned NumRegs = TableEntry->NumRegs; 665 unsigned RegElts = TableEntry->RegElts; 666 667 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), 668 TII->get(TableEntry->RealOpc)); 669 unsigned OpIdx = 0; 670 // The lane operand is always the 3rd from last operand, before the 2 671 // predicate operands. 672 unsigned Lane = MI.getOperand(MI.getDesc().getNumOperands() - 3).getImm(); 673 674 // Adjust the lane and spacing as needed for Q registers. 675 assert(RegSpc != OddDblSpc && "unexpected register spacing for VLD/VST-lane"); 676 if (RegSpc == EvenDblSpc && Lane >= RegElts) { 677 RegSpc = OddDblSpc; 678 Lane -= RegElts; 679 } 680 assert(Lane < RegElts && "out of range lane for VLD/VST-lane"); 681 682 unsigned D0 = 0, D1 = 0, D2 = 0, D3 = 0; 683 unsigned DstReg = 0; 684 bool DstIsDead = false; 685 if (TableEntry->IsLoad) { 686 DstIsDead = MI.getOperand(OpIdx).isDead(); 687 DstReg = MI.getOperand(OpIdx++).getReg(); 688 GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3); 689 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)); 690 if (NumRegs > 1) 691 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); 692 if (NumRegs > 2) 693 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead)); 694 if (NumRegs > 3) 695 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead)); 696 } 697 698 if (TableEntry->isUpdating) 699 MIB.add(MI.getOperand(OpIdx++)); 700 701 // Copy the addrmode6 operands. 702 MIB.add(MI.getOperand(OpIdx++)); 703 MIB.add(MI.getOperand(OpIdx++)); 704 // Copy the am6offset operand. 705 if (TableEntry->hasWritebackOperand) 706 MIB.add(MI.getOperand(OpIdx++)); 707 708 // Grab the super-register source. 709 MachineOperand MO = MI.getOperand(OpIdx++); 710 if (!TableEntry->IsLoad) 711 GetDSubRegs(MO.getReg(), RegSpc, TRI, D0, D1, D2, D3); 712 713 // Add the subregs as sources of the new instruction. 714 unsigned SrcFlags = (getUndefRegState(MO.isUndef()) | 715 getKillRegState(MO.isKill())); 716 MIB.addReg(D0, SrcFlags); 717 if (NumRegs > 1) 718 MIB.addReg(D1, SrcFlags); 719 if (NumRegs > 2) 720 MIB.addReg(D2, SrcFlags); 721 if (NumRegs > 3) 722 MIB.addReg(D3, SrcFlags); 723 724 // Add the lane number operand. 725 MIB.addImm(Lane); 726 OpIdx += 1; 727 728 // Copy the predicate operands. 729 MIB.add(MI.getOperand(OpIdx++)); 730 MIB.add(MI.getOperand(OpIdx++)); 731 732 // Copy the super-register source to be an implicit source. 733 MO.setImplicit(true); 734 MIB.add(MO); 735 if (TableEntry->IsLoad) 736 // Add an implicit def for the super-register. 737 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); 738 TransferImpOps(MI, MIB, MIB); 739 // Transfer memoperands. 740 MIB.cloneMemRefs(MI); 741 MI.eraseFromParent(); 742} 743 744/// ExpandVTBL - Translate VTBL and VTBX pseudo instructions with Q or QQ 745/// register operands to real instructions with D register operands. 746void ARMExpandPseudo::ExpandVTBL(MachineBasicBlock::iterator &MBBI, 747 unsigned Opc, bool IsExt) { 748 MachineInstr &MI = *MBBI; 749 MachineBasicBlock &MBB = *MI.getParent(); 750 LLVM_DEBUG(dbgs() << "Expanding: "; MI.dump()); 751 752 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc)); 753 unsigned OpIdx = 0; 754 755 // Transfer the destination register operand. 756 MIB.add(MI.getOperand(OpIdx++)); 757 if (IsExt) { 758 MachineOperand VdSrc(MI.getOperand(OpIdx++)); 759 MIB.add(VdSrc); 760 } 761 762 bool SrcIsKill = MI.getOperand(OpIdx).isKill(); 763 Register SrcReg = MI.getOperand(OpIdx++).getReg(); 764 unsigned D0, D1, D2, D3; 765 GetDSubRegs(SrcReg, SingleSpc, TRI, D0, D1, D2, D3); 766 MIB.addReg(D0); 767 768 // Copy the other source register operand. 769 MachineOperand VmSrc(MI.getOperand(OpIdx++)); 770 MIB.add(VmSrc); 771 772 // Copy the predicate operands. 773 MIB.add(MI.getOperand(OpIdx++)); 774 MIB.add(MI.getOperand(OpIdx++)); 775 776 // Add an implicit kill and use for the super-reg. 777 MIB.addReg(SrcReg, RegState::Implicit | getKillRegState(SrcIsKill)); 778 TransferImpOps(MI, MIB, MIB); 779 MI.eraseFromParent(); 780 LLVM_DEBUG(dbgs() << "To: "; MIB.getInstr()->dump();); 781} 782 783static bool IsAnAddressOperand(const MachineOperand &MO) { 784 // This check is overly conservative. Unless we are certain that the machine 785 // operand is not a symbol reference, we return that it is a symbol reference. 786 // This is important as the load pair may not be split up Windows. 787 switch (MO.getType()) { 788 case MachineOperand::MO_Register: 789 case MachineOperand::MO_Immediate: 790 case MachineOperand::MO_CImmediate: 791 case MachineOperand::MO_FPImmediate: 792 case MachineOperand::MO_ShuffleMask: 793 return false; 794 case MachineOperand::MO_MachineBasicBlock: 795 return true; 796 case MachineOperand::MO_FrameIndex: 797 return false; 798 case MachineOperand::MO_ConstantPoolIndex: 799 case MachineOperand::MO_TargetIndex: 800 case MachineOperand::MO_JumpTableIndex: 801 case MachineOperand::MO_ExternalSymbol: 802 case MachineOperand::MO_GlobalAddress: 803 case MachineOperand::MO_BlockAddress: 804 return true; 805 case MachineOperand::MO_RegisterMask: 806 case MachineOperand::MO_RegisterLiveOut: 807 return false; 808 case MachineOperand::MO_Metadata: 809 case MachineOperand::MO_MCSymbol: 810 return true; 811 case MachineOperand::MO_CFIIndex: 812 return false; 813 case MachineOperand::MO_IntrinsicID: 814 case MachineOperand::MO_Predicate: 815 llvm_unreachable("should not exist post-isel"); 816 } 817 llvm_unreachable("unhandled machine operand type"); 818} 819 820static MachineOperand makeImplicit(const MachineOperand &MO) { 821 MachineOperand NewMO = MO; 822 NewMO.setImplicit(); 823 return NewMO; 824} 825 826void ARMExpandPseudo::ExpandMOV32BitImm(MachineBasicBlock &MBB, 827 MachineBasicBlock::iterator &MBBI) { 828 MachineInstr &MI = *MBBI; 829 unsigned Opcode = MI.getOpcode(); 830 unsigned PredReg = 0; 831 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg); 832 Register DstReg = MI.getOperand(0).getReg(); 833 bool DstIsDead = MI.getOperand(0).isDead(); 834 bool isCC = Opcode == ARM::MOVCCi32imm || Opcode == ARM::t2MOVCCi32imm; 835 const MachineOperand &MO = MI.getOperand(isCC ? 2 : 1); 836 bool RequiresBundling = STI->isTargetWindows() && IsAnAddressOperand(MO); 837 MachineInstrBuilder LO16, HI16; 838 LLVM_DEBUG(dbgs() << "Expanding: "; MI.dump()); 839 840 if (!STI->hasV6T2Ops() && 841 (Opcode == ARM::MOVi32imm || Opcode == ARM::MOVCCi32imm)) { 842 // FIXME Windows CE supports older ARM CPUs 843 assert(!STI->isTargetWindows() && "Windows on ARM requires ARMv7+"); 844 845 // Expand into a movi + orr. 846 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVi), DstReg); 847 HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::ORRri)) 848 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) 849 .addReg(DstReg); 850 851 assert (MO.isImm() && "MOVi32imm w/ non-immediate source operand!"); 852 unsigned ImmVal = (unsigned)MO.getImm(); 853 unsigned SOImmValV1 = ARM_AM::getSOImmTwoPartFirst(ImmVal); 854 unsigned SOImmValV2 = ARM_AM::getSOImmTwoPartSecond(ImmVal); 855 LO16 = LO16.addImm(SOImmValV1); 856 HI16 = HI16.addImm(SOImmValV2); 857 LO16.cloneMemRefs(MI); 858 HI16.cloneMemRefs(MI); 859 LO16.addImm(Pred).addReg(PredReg).add(condCodeOp()); 860 HI16.addImm(Pred).addReg(PredReg).add(condCodeOp()); 861 if (isCC) 862 LO16.add(makeImplicit(MI.getOperand(1))); 863 TransferImpOps(MI, LO16, HI16); 864 MI.eraseFromParent(); 865 return; 866 } 867 868 unsigned LO16Opc = 0; 869 unsigned HI16Opc = 0; 870 if (Opcode == ARM::t2MOVi32imm || Opcode == ARM::t2MOVCCi32imm) { 871 LO16Opc = ARM::t2MOVi16; 872 HI16Opc = ARM::t2MOVTi16; 873 } else { 874 LO16Opc = ARM::MOVi16; 875 HI16Opc = ARM::MOVTi16; 876 } 877 878 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(LO16Opc), DstReg); 879 HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(HI16Opc)) 880 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) 881 .addReg(DstReg); 882 883 switch (MO.getType()) { 884 case MachineOperand::MO_Immediate: { 885 unsigned Imm = MO.getImm(); 886 unsigned Lo16 = Imm & 0xffff; 887 unsigned Hi16 = (Imm >> 16) & 0xffff; 888 LO16 = LO16.addImm(Lo16); 889 HI16 = HI16.addImm(Hi16); 890 break; 891 } 892 case MachineOperand::MO_ExternalSymbol: { 893 const char *ES = MO.getSymbolName(); 894 unsigned TF = MO.getTargetFlags(); 895 LO16 = LO16.addExternalSymbol(ES, TF | ARMII::MO_LO16); 896 HI16 = HI16.addExternalSymbol(ES, TF | ARMII::MO_HI16); 897 break; 898 } 899 default: { 900 const GlobalValue *GV = MO.getGlobal(); 901 unsigned TF = MO.getTargetFlags(); 902 LO16 = LO16.addGlobalAddress(GV, MO.getOffset(), TF | ARMII::MO_LO16); 903 HI16 = HI16.addGlobalAddress(GV, MO.getOffset(), TF | ARMII::MO_HI16); 904 break; 905 } 906 } 907 908 LO16.cloneMemRefs(MI); 909 HI16.cloneMemRefs(MI); 910 LO16.addImm(Pred).addReg(PredReg); 911 HI16.addImm(Pred).addReg(PredReg); 912 913 if (RequiresBundling) 914 finalizeBundle(MBB, LO16->getIterator(), MBBI->getIterator()); 915 916 if (isCC) 917 LO16.add(makeImplicit(MI.getOperand(1))); 918 TransferImpOps(MI, LO16, HI16); 919 MI.eraseFromParent(); 920 LLVM_DEBUG(dbgs() << "To: "; LO16.getInstr()->dump();); 921 LLVM_DEBUG(dbgs() << "And: "; HI16.getInstr()->dump();); 922} 923 924/// Expand a CMP_SWAP pseudo-inst to an ldrex/strex loop as simply as 925/// possible. This only gets used at -O0 so we don't care about efficiency of 926/// the generated code. 927bool ARMExpandPseudo::ExpandCMP_SWAP(MachineBasicBlock &MBB, 928 MachineBasicBlock::iterator MBBI, 929 unsigned LdrexOp, unsigned StrexOp, 930 unsigned UxtOp, 931 MachineBasicBlock::iterator &NextMBBI) { 932 bool IsThumb = STI->isThumb(); 933 MachineInstr &MI = *MBBI; 934 DebugLoc DL = MI.getDebugLoc(); 935 const MachineOperand &Dest = MI.getOperand(0); 936 Register TempReg = MI.getOperand(1).getReg(); 937 // Duplicating undef operands into 2 instructions does not guarantee the same 938 // value on both; However undef should be replaced by xzr anyway. 939 assert(!MI.getOperand(2).isUndef() && "cannot handle undef"); 940 Register AddrReg = MI.getOperand(2).getReg(); 941 Register DesiredReg = MI.getOperand(3).getReg(); 942 Register NewReg = MI.getOperand(4).getReg(); 943 944 MachineFunction *MF = MBB.getParent(); 945 auto LoadCmpBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); 946 auto StoreBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); 947 auto DoneBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); 948 949 MF->insert(++MBB.getIterator(), LoadCmpBB); 950 MF->insert(++LoadCmpBB->getIterator(), StoreBB); 951 MF->insert(++StoreBB->getIterator(), DoneBB); 952 953 if (UxtOp) { 954 MachineInstrBuilder MIB = 955 BuildMI(MBB, MBBI, DL, TII->get(UxtOp), DesiredReg) 956 .addReg(DesiredReg, RegState::Kill); 957 if (!IsThumb) 958 MIB.addImm(0); 959 MIB.add(predOps(ARMCC::AL)); 960 } 961 962 // .Lloadcmp: 963 // ldrex rDest, [rAddr] 964 // cmp rDest, rDesired 965 // bne .Ldone 966 967 MachineInstrBuilder MIB; 968 MIB = BuildMI(LoadCmpBB, DL, TII->get(LdrexOp), Dest.getReg()); 969 MIB.addReg(AddrReg); 970 if (LdrexOp == ARM::t2LDREX) 971 MIB.addImm(0); // a 32-bit Thumb ldrex (only) allows an offset. 972 MIB.add(predOps(ARMCC::AL)); 973 974 unsigned CMPrr = IsThumb ? ARM::tCMPhir : ARM::CMPrr; 975 BuildMI(LoadCmpBB, DL, TII->get(CMPrr)) 976 .addReg(Dest.getReg(), getKillRegState(Dest.isDead())) 977 .addReg(DesiredReg) 978 .add(predOps(ARMCC::AL)); 979 unsigned Bcc = IsThumb ? ARM::tBcc : ARM::Bcc; 980 BuildMI(LoadCmpBB, DL, TII->get(Bcc)) 981 .addMBB(DoneBB) 982 .addImm(ARMCC::NE) 983 .addReg(ARM::CPSR, RegState::Kill); 984 LoadCmpBB->addSuccessor(DoneBB); 985 LoadCmpBB->addSuccessor(StoreBB); 986 987 // .Lstore: 988 // strex rTempReg, rNew, [rAddr] 989 // cmp rTempReg, #0 990 // bne .Lloadcmp 991 MIB = BuildMI(StoreBB, DL, TII->get(StrexOp), TempReg) 992 .addReg(NewReg) 993 .addReg(AddrReg); 994 if (StrexOp == ARM::t2STREX) 995 MIB.addImm(0); // a 32-bit Thumb strex (only) allows an offset. 996 MIB.add(predOps(ARMCC::AL)); 997 998 unsigned CMPri = IsThumb ? ARM::t2CMPri : ARM::CMPri; 999 BuildMI(StoreBB, DL, TII->get(CMPri)) 1000 .addReg(TempReg, RegState::Kill) 1001 .addImm(0) 1002 .add(predOps(ARMCC::AL)); 1003 BuildMI(StoreBB, DL, TII->get(Bcc)) 1004 .addMBB(LoadCmpBB) 1005 .addImm(ARMCC::NE) 1006 .addReg(ARM::CPSR, RegState::Kill); 1007 StoreBB->addSuccessor(LoadCmpBB); 1008 StoreBB->addSuccessor(DoneBB); 1009 1010 DoneBB->splice(DoneBB->end(), &MBB, MI, MBB.end()); 1011 DoneBB->transferSuccessors(&MBB); 1012 1013 MBB.addSuccessor(LoadCmpBB); 1014 1015 NextMBBI = MBB.end(); 1016 MI.eraseFromParent(); 1017 1018 // Recompute livein lists. 1019 LivePhysRegs LiveRegs; 1020 computeAndAddLiveIns(LiveRegs, *DoneBB); 1021 computeAndAddLiveIns(LiveRegs, *StoreBB); 1022 computeAndAddLiveIns(LiveRegs, *LoadCmpBB); 1023 // Do an extra pass around the loop to get loop carried registers right. 1024 StoreBB->clearLiveIns(); 1025 computeAndAddLiveIns(LiveRegs, *StoreBB); 1026 LoadCmpBB->clearLiveIns(); 1027 computeAndAddLiveIns(LiveRegs, *LoadCmpBB); 1028 1029 return true; 1030} 1031 1032/// ARM's ldrexd/strexd take a consecutive register pair (represented as a 1033/// single GPRPair register), Thumb's take two separate registers so we need to 1034/// extract the subregs from the pair. 1035static void addExclusiveRegPair(MachineInstrBuilder &MIB, MachineOperand &Reg, 1036 unsigned Flags, bool IsThumb, 1037 const TargetRegisterInfo *TRI) { 1038 if (IsThumb) { 1039 Register RegLo = TRI->getSubReg(Reg.getReg(), ARM::gsub_0); 1040 Register RegHi = TRI->getSubReg(Reg.getReg(), ARM::gsub_1); 1041 MIB.addReg(RegLo, Flags); 1042 MIB.addReg(RegHi, Flags); 1043 } else 1044 MIB.addReg(Reg.getReg(), Flags); 1045} 1046 1047/// Expand a 64-bit CMP_SWAP to an ldrexd/strexd loop. 1048bool ARMExpandPseudo::ExpandCMP_SWAP_64(MachineBasicBlock &MBB, 1049 MachineBasicBlock::iterator MBBI, 1050 MachineBasicBlock::iterator &NextMBBI) { 1051 bool IsThumb = STI->isThumb(); 1052 MachineInstr &MI = *MBBI; 1053 DebugLoc DL = MI.getDebugLoc(); 1054 MachineOperand &Dest = MI.getOperand(0); 1055 Register TempReg = MI.getOperand(1).getReg(); 1056 // Duplicating undef operands into 2 instructions does not guarantee the same 1057 // value on both; However undef should be replaced by xzr anyway. 1058 assert(!MI.getOperand(2).isUndef() && "cannot handle undef"); 1059 Register AddrReg = MI.getOperand(2).getReg(); 1060 Register DesiredReg = MI.getOperand(3).getReg(); 1061 MachineOperand New = MI.getOperand(4); 1062 New.setIsKill(false); 1063 1064 Register DestLo = TRI->getSubReg(Dest.getReg(), ARM::gsub_0); 1065 Register DestHi = TRI->getSubReg(Dest.getReg(), ARM::gsub_1); 1066 Register DesiredLo = TRI->getSubReg(DesiredReg, ARM::gsub_0); 1067 Register DesiredHi = TRI->getSubReg(DesiredReg, ARM::gsub_1); 1068 1069 MachineFunction *MF = MBB.getParent(); 1070 auto LoadCmpBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); 1071 auto StoreBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); 1072 auto DoneBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); 1073 1074 MF->insert(++MBB.getIterator(), LoadCmpBB); 1075 MF->insert(++LoadCmpBB->getIterator(), StoreBB); 1076 MF->insert(++StoreBB->getIterator(), DoneBB); 1077 1078 // .Lloadcmp: 1079 // ldrexd rDestLo, rDestHi, [rAddr] 1080 // cmp rDestLo, rDesiredLo 1081 // sbcs dead rTempReg, rDestHi, rDesiredHi 1082 // bne .Ldone 1083 unsigned LDREXD = IsThumb ? ARM::t2LDREXD : ARM::LDREXD; 1084 MachineInstrBuilder MIB; 1085 MIB = BuildMI(LoadCmpBB, DL, TII->get(LDREXD)); 1086 addExclusiveRegPair(MIB, Dest, RegState::Define, IsThumb, TRI); 1087 MIB.addReg(AddrReg).add(predOps(ARMCC::AL)); 1088 1089 unsigned CMPrr = IsThumb ? ARM::tCMPhir : ARM::CMPrr; 1090 BuildMI(LoadCmpBB, DL, TII->get(CMPrr)) 1091 .addReg(DestLo, getKillRegState(Dest.isDead())) 1092 .addReg(DesiredLo) 1093 .add(predOps(ARMCC::AL)); 1094 1095 BuildMI(LoadCmpBB, DL, TII->get(CMPrr)) 1096 .addReg(DestHi, getKillRegState(Dest.isDead())) 1097 .addReg(DesiredHi) 1098 .addImm(ARMCC::EQ).addReg(ARM::CPSR, RegState::Kill); 1099 1100 unsigned Bcc = IsThumb ? ARM::tBcc : ARM::Bcc; 1101 BuildMI(LoadCmpBB, DL, TII->get(Bcc)) 1102 .addMBB(DoneBB) 1103 .addImm(ARMCC::NE) 1104 .addReg(ARM::CPSR, RegState::Kill); 1105 LoadCmpBB->addSuccessor(DoneBB); 1106 LoadCmpBB->addSuccessor(StoreBB); 1107 1108 // .Lstore: 1109 // strexd rTempReg, rNewLo, rNewHi, [rAddr] 1110 // cmp rTempReg, #0 1111 // bne .Lloadcmp 1112 unsigned STREXD = IsThumb ? ARM::t2STREXD : ARM::STREXD; 1113 MIB = BuildMI(StoreBB, DL, TII->get(STREXD), TempReg); 1114 unsigned Flags = getKillRegState(New.isDead()); 1115 addExclusiveRegPair(MIB, New, Flags, IsThumb, TRI); 1116 MIB.addReg(AddrReg).add(predOps(ARMCC::AL)); 1117 1118 unsigned CMPri = IsThumb ? ARM::t2CMPri : ARM::CMPri; 1119 BuildMI(StoreBB, DL, TII->get(CMPri)) 1120 .addReg(TempReg, RegState::Kill) 1121 .addImm(0) 1122 .add(predOps(ARMCC::AL)); 1123 BuildMI(StoreBB, DL, TII->get(Bcc)) 1124 .addMBB(LoadCmpBB) 1125 .addImm(ARMCC::NE) 1126 .addReg(ARM::CPSR, RegState::Kill); 1127 StoreBB->addSuccessor(LoadCmpBB); 1128 StoreBB->addSuccessor(DoneBB); 1129 1130 DoneBB->splice(DoneBB->end(), &MBB, MI, MBB.end()); 1131 DoneBB->transferSuccessors(&MBB); 1132 1133 MBB.addSuccessor(LoadCmpBB); 1134 1135 NextMBBI = MBB.end(); 1136 MI.eraseFromParent(); 1137 1138 // Recompute livein lists. 1139 LivePhysRegs LiveRegs; 1140 computeAndAddLiveIns(LiveRegs, *DoneBB); 1141 computeAndAddLiveIns(LiveRegs, *StoreBB); 1142 computeAndAddLiveIns(LiveRegs, *LoadCmpBB); 1143 // Do an extra pass around the loop to get loop carried registers right. 1144 StoreBB->clearLiveIns(); 1145 computeAndAddLiveIns(LiveRegs, *StoreBB); 1146 LoadCmpBB->clearLiveIns(); 1147 computeAndAddLiveIns(LiveRegs, *LoadCmpBB); 1148 1149 return true; 1150} 1151 1152 1153bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB, 1154 MachineBasicBlock::iterator MBBI, 1155 MachineBasicBlock::iterator &NextMBBI) { 1156 MachineInstr &MI = *MBBI; 1157 unsigned Opcode = MI.getOpcode(); 1158 switch (Opcode) { 1159 default: 1160 return false; 1161 1162 case ARM::TCRETURNdi: 1163 case ARM::TCRETURNri: { 1164 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr(); 1165 assert(MBBI->isReturn() && 1166 "Can only insert epilog into returning blocks"); 1167 unsigned RetOpcode = MBBI->getOpcode(); 1168 DebugLoc dl = MBBI->getDebugLoc(); 1169 const ARMBaseInstrInfo &TII = *static_cast<const ARMBaseInstrInfo *>( 1170 MBB.getParent()->getSubtarget().getInstrInfo()); 1171 1172 // Tail call return: adjust the stack pointer and jump to callee. 1173 MBBI = MBB.getLastNonDebugInstr(); 1174 MachineOperand &JumpTarget = MBBI->getOperand(0); 1175 1176 // Jump to label or value in register. 1177 if (RetOpcode == ARM::TCRETURNdi) { 1178 unsigned TCOpcode = 1179 STI->isThumb() 1180 ? (STI->isTargetMachO() ? ARM::tTAILJMPd : ARM::tTAILJMPdND) 1181 : ARM::TAILJMPd; 1182 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(TCOpcode)); 1183 if (JumpTarget.isGlobal()) 1184 MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(), 1185 JumpTarget.getTargetFlags()); 1186 else { 1187 assert(JumpTarget.isSymbol()); 1188 MIB.addExternalSymbol(JumpTarget.getSymbolName(), 1189 JumpTarget.getTargetFlags()); 1190 } 1191 1192 // Add the default predicate in Thumb mode. 1193 if (STI->isThumb()) 1194 MIB.add(predOps(ARMCC::AL)); 1195 } else if (RetOpcode == ARM::TCRETURNri) { 1196 unsigned Opcode = 1197 STI->isThumb() ? ARM::tTAILJMPr 1198 : (STI->hasV4TOps() ? ARM::TAILJMPr : ARM::TAILJMPr4); 1199 BuildMI(MBB, MBBI, dl, 1200 TII.get(Opcode)) 1201 .addReg(JumpTarget.getReg(), RegState::Kill); 1202 } 1203 1204 auto NewMI = std::prev(MBBI); 1205 for (unsigned i = 1, e = MBBI->getNumOperands(); i != e; ++i) 1206 NewMI->addOperand(MBBI->getOperand(i)); 1207 1208 1209 // Update call site info and delete the pseudo instruction TCRETURN. 1210 MBB.getParent()->moveCallSiteInfo(&MI, &*NewMI); 1211 MBB.erase(MBBI); 1212 1213 MBBI = NewMI; 1214 return true; 1215 } 1216 case ARM::VMOVHcc: 1217 case ARM::VMOVScc: 1218 case ARM::VMOVDcc: { 1219 unsigned newOpc = Opcode != ARM::VMOVDcc ? ARM::VMOVS : ARM::VMOVD; 1220 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(newOpc), 1221 MI.getOperand(1).getReg()) 1222 .add(MI.getOperand(2)) 1223 .addImm(MI.getOperand(3).getImm()) // 'pred' 1224 .add(MI.getOperand(4)) 1225 .add(makeImplicit(MI.getOperand(1))); 1226 1227 MI.eraseFromParent(); 1228 return true; 1229 } 1230 case ARM::t2MOVCCr: 1231 case ARM::MOVCCr: { 1232 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MOVr : ARM::MOVr; 1233 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc), 1234 MI.getOperand(1).getReg()) 1235 .add(MI.getOperand(2)) 1236 .addImm(MI.getOperand(3).getImm()) // 'pred' 1237 .add(MI.getOperand(4)) 1238 .add(condCodeOp()) // 's' bit 1239 .add(makeImplicit(MI.getOperand(1))); 1240 1241 MI.eraseFromParent(); 1242 return true; 1243 } 1244 case ARM::MOVCCsi: { 1245 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi), 1246 (MI.getOperand(1).getReg())) 1247 .add(MI.getOperand(2)) 1248 .addImm(MI.getOperand(3).getImm()) 1249 .addImm(MI.getOperand(4).getImm()) // 'pred' 1250 .add(MI.getOperand(5)) 1251 .add(condCodeOp()) // 's' bit 1252 .add(makeImplicit(MI.getOperand(1))); 1253 1254 MI.eraseFromParent(); 1255 return true; 1256 } 1257 case ARM::MOVCCsr: { 1258 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsr), 1259 (MI.getOperand(1).getReg())) 1260 .add(MI.getOperand(2)) 1261 .add(MI.getOperand(3)) 1262 .addImm(MI.getOperand(4).getImm()) 1263 .addImm(MI.getOperand(5).getImm()) // 'pred' 1264 .add(MI.getOperand(6)) 1265 .add(condCodeOp()) // 's' bit 1266 .add(makeImplicit(MI.getOperand(1))); 1267 1268 MI.eraseFromParent(); 1269 return true; 1270 } 1271 case ARM::t2MOVCCi16: 1272 case ARM::MOVCCi16: { 1273 unsigned NewOpc = AFI->isThumbFunction() ? ARM::t2MOVi16 : ARM::MOVi16; 1274 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc), 1275 MI.getOperand(1).getReg()) 1276 .addImm(MI.getOperand(2).getImm()) 1277 .addImm(MI.getOperand(3).getImm()) // 'pred' 1278 .add(MI.getOperand(4)) 1279 .add(makeImplicit(MI.getOperand(1))); 1280 MI.eraseFromParent(); 1281 return true; 1282 } 1283 case ARM::t2MOVCCi: 1284 case ARM::MOVCCi: { 1285 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MOVi : ARM::MOVi; 1286 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc), 1287 MI.getOperand(1).getReg()) 1288 .addImm(MI.getOperand(2).getImm()) 1289 .addImm(MI.getOperand(3).getImm()) // 'pred' 1290 .add(MI.getOperand(4)) 1291 .add(condCodeOp()) // 's' bit 1292 .add(makeImplicit(MI.getOperand(1))); 1293 1294 MI.eraseFromParent(); 1295 return true; 1296 } 1297 case ARM::t2MVNCCi: 1298 case ARM::MVNCCi: { 1299 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MVNi : ARM::MVNi; 1300 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc), 1301 MI.getOperand(1).getReg()) 1302 .addImm(MI.getOperand(2).getImm()) 1303 .addImm(MI.getOperand(3).getImm()) // 'pred' 1304 .add(MI.getOperand(4)) 1305 .add(condCodeOp()) // 's' bit 1306 .add(makeImplicit(MI.getOperand(1))); 1307 1308 MI.eraseFromParent(); 1309 return true; 1310 } 1311 case ARM::t2MOVCClsl: 1312 case ARM::t2MOVCClsr: 1313 case ARM::t2MOVCCasr: 1314 case ARM::t2MOVCCror: { 1315 unsigned NewOpc; 1316 switch (Opcode) { 1317 case ARM::t2MOVCClsl: NewOpc = ARM::t2LSLri; break; 1318 case ARM::t2MOVCClsr: NewOpc = ARM::t2LSRri; break; 1319 case ARM::t2MOVCCasr: NewOpc = ARM::t2ASRri; break; 1320 case ARM::t2MOVCCror: NewOpc = ARM::t2RORri; break; 1321 default: llvm_unreachable("unexpeced conditional move"); 1322 } 1323 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc), 1324 MI.getOperand(1).getReg()) 1325 .add(MI.getOperand(2)) 1326 .addImm(MI.getOperand(3).getImm()) 1327 .addImm(MI.getOperand(4).getImm()) // 'pred' 1328 .add(MI.getOperand(5)) 1329 .add(condCodeOp()) // 's' bit 1330 .add(makeImplicit(MI.getOperand(1))); 1331 MI.eraseFromParent(); 1332 return true; 1333 } 1334 case ARM::Int_eh_sjlj_dispatchsetup: { 1335 MachineFunction &MF = *MI.getParent()->getParent(); 1336 const ARMBaseInstrInfo *AII = 1337 static_cast<const ARMBaseInstrInfo*>(TII); 1338 const ARMBaseRegisterInfo &RI = AII->getRegisterInfo(); 1339 // For functions using a base pointer, we rematerialize it (via the frame 1340 // pointer) here since eh.sjlj.setjmp and eh.sjlj.longjmp don't do it 1341 // for us. Otherwise, expand to nothing. 1342 if (RI.hasBasePointer(MF)) { 1343 int32_t NumBytes = AFI->getFramePtrSpillOffset(); 1344 Register FramePtr = RI.getFrameRegister(MF); 1345 assert(MF.getSubtarget().getFrameLowering()->hasFP(MF) && 1346 "base pointer without frame pointer?"); 1347 1348 if (AFI->isThumb2Function()) { 1349 emitT2RegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6, 1350 FramePtr, -NumBytes, ARMCC::AL, 0, *TII); 1351 } else if (AFI->isThumbFunction()) { 1352 emitThumbRegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6, 1353 FramePtr, -NumBytes, *TII, RI); 1354 } else { 1355 emitARMRegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6, 1356 FramePtr, -NumBytes, ARMCC::AL, 0, 1357 *TII); 1358 } 1359 // If there's dynamic realignment, adjust for it. 1360 if (RI.needsStackRealignment(MF)) { 1361 MachineFrameInfo &MFI = MF.getFrameInfo(); 1362 unsigned MaxAlign = MFI.getMaxAlignment(); 1363 assert (!AFI->isThumb1OnlyFunction()); 1364 // Emit bic r6, r6, MaxAlign 1365 assert(MaxAlign <= 256 && "The BIC instruction cannot encode " 1366 "immediates larger than 256 with all lower " 1367 "bits set."); 1368 unsigned bicOpc = AFI->isThumbFunction() ? 1369 ARM::t2BICri : ARM::BICri; 1370 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(bicOpc), ARM::R6) 1371 .addReg(ARM::R6, RegState::Kill) 1372 .addImm(MaxAlign - 1) 1373 .add(predOps(ARMCC::AL)) 1374 .add(condCodeOp()); 1375 } 1376 1377 } 1378 MI.eraseFromParent(); 1379 return true; 1380 } 1381 1382 case ARM::MOVsrl_flag: 1383 case ARM::MOVsra_flag: { 1384 // These are just fancy MOVs instructions. 1385 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi), 1386 MI.getOperand(0).getReg()) 1387 .add(MI.getOperand(1)) 1388 .addImm(ARM_AM::getSORegOpc( 1389 (Opcode == ARM::MOVsrl_flag ? ARM_AM::lsr : ARM_AM::asr), 1)) 1390 .add(predOps(ARMCC::AL)) 1391 .addReg(ARM::CPSR, RegState::Define); 1392 MI.eraseFromParent(); 1393 return true; 1394 } 1395 case ARM::RRX: { 1396 // This encodes as "MOVs Rd, Rm, rrx 1397 MachineInstrBuilder MIB = 1398 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi), 1399 MI.getOperand(0).getReg()) 1400 .add(MI.getOperand(1)) 1401 .addImm(ARM_AM::getSORegOpc(ARM_AM::rrx, 0)) 1402 .add(predOps(ARMCC::AL)) 1403 .add(condCodeOp()); 1404 TransferImpOps(MI, MIB, MIB); 1405 MI.eraseFromParent(); 1406 return true; 1407 } 1408 case ARM::tTPsoft: 1409 case ARM::TPsoft: { 1410 const bool Thumb = Opcode == ARM::tTPsoft; 1411 1412 MachineInstrBuilder MIB; 1413 if (STI->genLongCalls()) { 1414 MachineFunction *MF = MBB.getParent(); 1415 MachineConstantPool *MCP = MF->getConstantPool(); 1416 unsigned PCLabelID = AFI->createPICLabelUId(); 1417 MachineConstantPoolValue *CPV = 1418 ARMConstantPoolSymbol::Create(MF->getFunction().getContext(), 1419 "__aeabi_read_tp", PCLabelID, 0); 1420 Register Reg = MI.getOperand(0).getReg(); 1421 MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), 1422 TII->get(Thumb ? ARM::tLDRpci : ARM::LDRi12), Reg) 1423 .addConstantPoolIndex(MCP->getConstantPoolIndex(CPV, 4)); 1424 if (!Thumb) 1425 MIB.addImm(0); 1426 MIB.add(predOps(ARMCC::AL)); 1427 1428 MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), 1429 TII->get(Thumb ? ARM::tBLXr : ARM::BLX)); 1430 if (Thumb) 1431 MIB.add(predOps(ARMCC::AL)); 1432 MIB.addReg(Reg, RegState::Kill); 1433 } else { 1434 MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), 1435 TII->get(Thumb ? ARM::tBL : ARM::BL)); 1436 if (Thumb) 1437 MIB.add(predOps(ARMCC::AL)); 1438 MIB.addExternalSymbol("__aeabi_read_tp", 0); 1439 } 1440 1441 MIB.cloneMemRefs(MI); 1442 TransferImpOps(MI, MIB, MIB); 1443 MI.getMF()->moveCallSiteInfo(&MI, &*MIB); 1444 MI.eraseFromParent(); 1445 return true; 1446 } 1447 case ARM::tLDRpci_pic: 1448 case ARM::t2LDRpci_pic: { 1449 unsigned NewLdOpc = (Opcode == ARM::tLDRpci_pic) 1450 ? ARM::tLDRpci : ARM::t2LDRpci; 1451 Register DstReg = MI.getOperand(0).getReg(); 1452 bool DstIsDead = MI.getOperand(0).isDead(); 1453 MachineInstrBuilder MIB1 = 1454 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewLdOpc), DstReg) 1455 .add(MI.getOperand(1)) 1456 .add(predOps(ARMCC::AL)); 1457 MIB1.cloneMemRefs(MI); 1458 MachineInstrBuilder MIB2 = 1459 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::tPICADD)) 1460 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) 1461 .addReg(DstReg) 1462 .add(MI.getOperand(2)); 1463 TransferImpOps(MI, MIB1, MIB2); 1464 MI.eraseFromParent(); 1465 return true; 1466 } 1467 1468 case ARM::LDRLIT_ga_abs: 1469 case ARM::LDRLIT_ga_pcrel: 1470 case ARM::LDRLIT_ga_pcrel_ldr: 1471 case ARM::tLDRLIT_ga_abs: 1472 case ARM::tLDRLIT_ga_pcrel: { 1473 Register DstReg = MI.getOperand(0).getReg(); 1474 bool DstIsDead = MI.getOperand(0).isDead(); 1475 const MachineOperand &MO1 = MI.getOperand(1); 1476 auto Flags = MO1.getTargetFlags(); 1477 const GlobalValue *GV = MO1.getGlobal(); 1478 bool IsARM = 1479 Opcode != ARM::tLDRLIT_ga_pcrel && Opcode != ARM::tLDRLIT_ga_abs; 1480 bool IsPIC = 1481 Opcode != ARM::LDRLIT_ga_abs && Opcode != ARM::tLDRLIT_ga_abs; 1482 unsigned LDRLITOpc = IsARM ? ARM::LDRi12 : ARM::tLDRpci; 1483 unsigned PICAddOpc = 1484 IsARM 1485 ? (Opcode == ARM::LDRLIT_ga_pcrel_ldr ? ARM::PICLDR : ARM::PICADD) 1486 : ARM::tPICADD; 1487 1488 // We need a new const-pool entry to load from. 1489 MachineConstantPool *MCP = MBB.getParent()->getConstantPool(); 1490 unsigned ARMPCLabelIndex = 0; 1491 MachineConstantPoolValue *CPV; 1492 1493 if (IsPIC) { 1494 unsigned PCAdj = IsARM ? 8 : 4; 1495 auto Modifier = (Flags & ARMII::MO_GOT) 1496 ? ARMCP::GOT_PREL 1497 : ARMCP::no_modifier; 1498 ARMPCLabelIndex = AFI->createPICLabelUId(); 1499 CPV = ARMConstantPoolConstant::Create( 1500 GV, ARMPCLabelIndex, ARMCP::CPValue, PCAdj, Modifier, 1501 /*AddCurrentAddr*/ Modifier == ARMCP::GOT_PREL); 1502 } else 1503 CPV = ARMConstantPoolConstant::Create(GV, ARMCP::no_modifier); 1504 1505 MachineInstrBuilder MIB = 1506 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(LDRLITOpc), DstReg) 1507 .addConstantPoolIndex(MCP->getConstantPoolIndex(CPV, 4)); 1508 if (IsARM) 1509 MIB.addImm(0); 1510 MIB.add(predOps(ARMCC::AL)); 1511 1512 if (IsPIC) { 1513 MachineInstrBuilder MIB = 1514 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(PICAddOpc)) 1515 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) 1516 .addReg(DstReg) 1517 .addImm(ARMPCLabelIndex); 1518 1519 if (IsARM) 1520 MIB.add(predOps(ARMCC::AL)); 1521 } 1522 1523 MI.eraseFromParent(); 1524 return true; 1525 } 1526 case ARM::MOV_ga_pcrel: 1527 case ARM::MOV_ga_pcrel_ldr: 1528 case ARM::t2MOV_ga_pcrel: { 1529 // Expand into movw + movw. Also "add pc" / ldr [pc] in PIC mode. 1530 unsigned LabelId = AFI->createPICLabelUId(); 1531 Register DstReg = MI.getOperand(0).getReg(); 1532 bool DstIsDead = MI.getOperand(0).isDead(); 1533 const MachineOperand &MO1 = MI.getOperand(1); 1534 const GlobalValue *GV = MO1.getGlobal(); 1535 unsigned TF = MO1.getTargetFlags(); 1536 bool isARM = Opcode != ARM::t2MOV_ga_pcrel; 1537 unsigned LO16Opc = isARM ? ARM::MOVi16_ga_pcrel : ARM::t2MOVi16_ga_pcrel; 1538 unsigned HI16Opc = isARM ? ARM::MOVTi16_ga_pcrel :ARM::t2MOVTi16_ga_pcrel; 1539 unsigned LO16TF = TF | ARMII::MO_LO16; 1540 unsigned HI16TF = TF | ARMII::MO_HI16; 1541 unsigned PICAddOpc = isARM 1542 ? (Opcode == ARM::MOV_ga_pcrel_ldr ? ARM::PICLDR : ARM::PICADD) 1543 : ARM::tPICADD; 1544 MachineInstrBuilder MIB1 = BuildMI(MBB, MBBI, MI.getDebugLoc(), 1545 TII->get(LO16Opc), DstReg) 1546 .addGlobalAddress(GV, MO1.getOffset(), TF | LO16TF) 1547 .addImm(LabelId); 1548 1549 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(HI16Opc), DstReg) 1550 .addReg(DstReg) 1551 .addGlobalAddress(GV, MO1.getOffset(), TF | HI16TF) 1552 .addImm(LabelId); 1553 1554 MachineInstrBuilder MIB3 = BuildMI(MBB, MBBI, MI.getDebugLoc(), 1555 TII->get(PICAddOpc)) 1556 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) 1557 .addReg(DstReg).addImm(LabelId); 1558 if (isARM) { 1559 MIB3.add(predOps(ARMCC::AL)); 1560 if (Opcode == ARM::MOV_ga_pcrel_ldr) 1561 MIB3.cloneMemRefs(MI); 1562 } 1563 TransferImpOps(MI, MIB1, MIB3); 1564 MI.eraseFromParent(); 1565 return true; 1566 } 1567 1568 case ARM::MOVi32imm: 1569 case ARM::MOVCCi32imm: 1570 case ARM::t2MOVi32imm: 1571 case ARM::t2MOVCCi32imm: 1572 ExpandMOV32BitImm(MBB, MBBI); 1573 return true; 1574 1575 case ARM::SUBS_PC_LR: { 1576 MachineInstrBuilder MIB = 1577 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::SUBri), ARM::PC) 1578 .addReg(ARM::LR) 1579 .add(MI.getOperand(0)) 1580 .add(MI.getOperand(1)) 1581 .add(MI.getOperand(2)) 1582 .addReg(ARM::CPSR, RegState::Undef); 1583 TransferImpOps(MI, MIB, MIB); 1584 MI.eraseFromParent(); 1585 return true; 1586 } 1587 case ARM::VLDMQIA: { 1588 unsigned NewOpc = ARM::VLDMDIA; 1589 MachineInstrBuilder MIB = 1590 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc)); 1591 unsigned OpIdx = 0; 1592 1593 // Grab the Q register destination. 1594 bool DstIsDead = MI.getOperand(OpIdx).isDead(); 1595 Register DstReg = MI.getOperand(OpIdx++).getReg(); 1596 1597 // Copy the source register. 1598 MIB.add(MI.getOperand(OpIdx++)); 1599 1600 // Copy the predicate operands. 1601 MIB.add(MI.getOperand(OpIdx++)); 1602 MIB.add(MI.getOperand(OpIdx++)); 1603 1604 // Add the destination operands (D subregs). 1605 Register D0 = TRI->getSubReg(DstReg, ARM::dsub_0); 1606 Register D1 = TRI->getSubReg(DstReg, ARM::dsub_1); 1607 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)) 1608 .addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); 1609 1610 // Add an implicit def for the super-register. 1611 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); 1612 TransferImpOps(MI, MIB, MIB); 1613 MIB.cloneMemRefs(MI); 1614 MI.eraseFromParent(); 1615 return true; 1616 } 1617 1618 case ARM::VSTMQIA: { 1619 unsigned NewOpc = ARM::VSTMDIA; 1620 MachineInstrBuilder MIB = 1621 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc)); 1622 unsigned OpIdx = 0; 1623 1624 // Grab the Q register source. 1625 bool SrcIsKill = MI.getOperand(OpIdx).isKill(); 1626 Register SrcReg = MI.getOperand(OpIdx++).getReg(); 1627 1628 // Copy the destination register. 1629 MachineOperand Dst(MI.getOperand(OpIdx++)); 1630 MIB.add(Dst); 1631 1632 // Copy the predicate operands. 1633 MIB.add(MI.getOperand(OpIdx++)); 1634 MIB.add(MI.getOperand(OpIdx++)); 1635 1636 // Add the source operands (D subregs). 1637 Register D0 = TRI->getSubReg(SrcReg, ARM::dsub_0); 1638 Register D1 = TRI->getSubReg(SrcReg, ARM::dsub_1); 1639 MIB.addReg(D0, SrcIsKill ? RegState::Kill : 0) 1640 .addReg(D1, SrcIsKill ? RegState::Kill : 0); 1641 1642 if (SrcIsKill) // Add an implicit kill for the Q register. 1643 MIB->addRegisterKilled(SrcReg, TRI, true); 1644 1645 TransferImpOps(MI, MIB, MIB); 1646 MIB.cloneMemRefs(MI); 1647 MI.eraseFromParent(); 1648 return true; 1649 } 1650 1651 case ARM::VLD2q8Pseudo: 1652 case ARM::VLD2q16Pseudo: 1653 case ARM::VLD2q32Pseudo: 1654 case ARM::VLD2q8PseudoWB_fixed: 1655 case ARM::VLD2q16PseudoWB_fixed: 1656 case ARM::VLD2q32PseudoWB_fixed: 1657 case ARM::VLD2q8PseudoWB_register: 1658 case ARM::VLD2q16PseudoWB_register: 1659 case ARM::VLD2q32PseudoWB_register: 1660 case ARM::VLD3d8Pseudo: 1661 case ARM::VLD3d16Pseudo: 1662 case ARM::VLD3d32Pseudo: 1663 case ARM::VLD1d8TPseudo: 1664 case ARM::VLD1d16TPseudo: 1665 case ARM::VLD1d32TPseudo: 1666 case ARM::VLD1d64TPseudo: 1667 case ARM::VLD1d64TPseudoWB_fixed: 1668 case ARM::VLD1d64TPseudoWB_register: 1669 case ARM::VLD3d8Pseudo_UPD: 1670 case ARM::VLD3d16Pseudo_UPD: 1671 case ARM::VLD3d32Pseudo_UPD: 1672 case ARM::VLD3q8Pseudo_UPD: 1673 case ARM::VLD3q16Pseudo_UPD: 1674 case ARM::VLD3q32Pseudo_UPD: 1675 case ARM::VLD3q8oddPseudo: 1676 case ARM::VLD3q16oddPseudo: 1677 case ARM::VLD3q32oddPseudo: 1678 case ARM::VLD3q8oddPseudo_UPD: 1679 case ARM::VLD3q16oddPseudo_UPD: 1680 case ARM::VLD3q32oddPseudo_UPD: 1681 case ARM::VLD4d8Pseudo: 1682 case ARM::VLD4d16Pseudo: 1683 case ARM::VLD4d32Pseudo: 1684 case ARM::VLD1d8QPseudo: 1685 case ARM::VLD1d16QPseudo: 1686 case ARM::VLD1d32QPseudo: 1687 case ARM::VLD1d64QPseudo: 1688 case ARM::VLD1d64QPseudoWB_fixed: 1689 case ARM::VLD1d64QPseudoWB_register: 1690 case ARM::VLD1q8HighQPseudo: 1691 case ARM::VLD1q8LowQPseudo_UPD: 1692 case ARM::VLD1q8HighTPseudo: 1693 case ARM::VLD1q8LowTPseudo_UPD: 1694 case ARM::VLD1q16HighQPseudo: 1695 case ARM::VLD1q16LowQPseudo_UPD: 1696 case ARM::VLD1q16HighTPseudo: 1697 case ARM::VLD1q16LowTPseudo_UPD: 1698 case ARM::VLD1q32HighQPseudo: 1699 case ARM::VLD1q32LowQPseudo_UPD: 1700 case ARM::VLD1q32HighTPseudo: 1701 case ARM::VLD1q32LowTPseudo_UPD: 1702 case ARM::VLD1q64HighQPseudo: 1703 case ARM::VLD1q64LowQPseudo_UPD: 1704 case ARM::VLD1q64HighTPseudo: 1705 case ARM::VLD1q64LowTPseudo_UPD: 1706 case ARM::VLD4d8Pseudo_UPD: 1707 case ARM::VLD4d16Pseudo_UPD: 1708 case ARM::VLD4d32Pseudo_UPD: 1709 case ARM::VLD4q8Pseudo_UPD: 1710 case ARM::VLD4q16Pseudo_UPD: 1711 case ARM::VLD4q32Pseudo_UPD: 1712 case ARM::VLD4q8oddPseudo: 1713 case ARM::VLD4q16oddPseudo: 1714 case ARM::VLD4q32oddPseudo: 1715 case ARM::VLD4q8oddPseudo_UPD: 1716 case ARM::VLD4q16oddPseudo_UPD: 1717 case ARM::VLD4q32oddPseudo_UPD: 1718 case ARM::VLD3DUPd8Pseudo: 1719 case ARM::VLD3DUPd16Pseudo: 1720 case ARM::VLD3DUPd32Pseudo: 1721 case ARM::VLD3DUPd8Pseudo_UPD: 1722 case ARM::VLD3DUPd16Pseudo_UPD: 1723 case ARM::VLD3DUPd32Pseudo_UPD: 1724 case ARM::VLD4DUPd8Pseudo: 1725 case ARM::VLD4DUPd16Pseudo: 1726 case ARM::VLD4DUPd32Pseudo: 1727 case ARM::VLD4DUPd8Pseudo_UPD: 1728 case ARM::VLD4DUPd16Pseudo_UPD: 1729 case ARM::VLD4DUPd32Pseudo_UPD: 1730 case ARM::VLD2DUPq8EvenPseudo: 1731 case ARM::VLD2DUPq8OddPseudo: 1732 case ARM::VLD2DUPq16EvenPseudo: 1733 case ARM::VLD2DUPq16OddPseudo: 1734 case ARM::VLD2DUPq32EvenPseudo: 1735 case ARM::VLD2DUPq32OddPseudo: 1736 case ARM::VLD3DUPq8EvenPseudo: 1737 case ARM::VLD3DUPq8OddPseudo: 1738 case ARM::VLD3DUPq16EvenPseudo: 1739 case ARM::VLD3DUPq16OddPseudo: 1740 case ARM::VLD3DUPq32EvenPseudo: 1741 case ARM::VLD3DUPq32OddPseudo: 1742 case ARM::VLD4DUPq8EvenPseudo: 1743 case ARM::VLD4DUPq8OddPseudo: 1744 case ARM::VLD4DUPq16EvenPseudo: 1745 case ARM::VLD4DUPq16OddPseudo: 1746 case ARM::VLD4DUPq32EvenPseudo: 1747 case ARM::VLD4DUPq32OddPseudo: 1748 ExpandVLD(MBBI); 1749 return true; 1750 1751 case ARM::VST2q8Pseudo: 1752 case ARM::VST2q16Pseudo: 1753 case ARM::VST2q32Pseudo: 1754 case ARM::VST2q8PseudoWB_fixed: 1755 case ARM::VST2q16PseudoWB_fixed: 1756 case ARM::VST2q32PseudoWB_fixed: 1757 case ARM::VST2q8PseudoWB_register: 1758 case ARM::VST2q16PseudoWB_register: 1759 case ARM::VST2q32PseudoWB_register: 1760 case ARM::VST3d8Pseudo: 1761 case ARM::VST3d16Pseudo: 1762 case ARM::VST3d32Pseudo: 1763 case ARM::VST1d8TPseudo: 1764 case ARM::VST1d16TPseudo: 1765 case ARM::VST1d32TPseudo: 1766 case ARM::VST1d64TPseudo: 1767 case ARM::VST3d8Pseudo_UPD: 1768 case ARM::VST3d16Pseudo_UPD: 1769 case ARM::VST3d32Pseudo_UPD: 1770 case ARM::VST1d64TPseudoWB_fixed: 1771 case ARM::VST1d64TPseudoWB_register: 1772 case ARM::VST3q8Pseudo_UPD: 1773 case ARM::VST3q16Pseudo_UPD: 1774 case ARM::VST3q32Pseudo_UPD: 1775 case ARM::VST3q8oddPseudo: 1776 case ARM::VST3q16oddPseudo: 1777 case ARM::VST3q32oddPseudo: 1778 case ARM::VST3q8oddPseudo_UPD: 1779 case ARM::VST3q16oddPseudo_UPD: 1780 case ARM::VST3q32oddPseudo_UPD: 1781 case ARM::VST4d8Pseudo: 1782 case ARM::VST4d16Pseudo: 1783 case ARM::VST4d32Pseudo: 1784 case ARM::VST1d8QPseudo: 1785 case ARM::VST1d16QPseudo: 1786 case ARM::VST1d32QPseudo: 1787 case ARM::VST1d64QPseudo: 1788 case ARM::VST4d8Pseudo_UPD: 1789 case ARM::VST4d16Pseudo_UPD: 1790 case ARM::VST4d32Pseudo_UPD: 1791 case ARM::VST1d64QPseudoWB_fixed: 1792 case ARM::VST1d64QPseudoWB_register: 1793 case ARM::VST1q8HighQPseudo: 1794 case ARM::VST1q8LowQPseudo_UPD: 1795 case ARM::VST1q8HighTPseudo: 1796 case ARM::VST1q8LowTPseudo_UPD: 1797 case ARM::VST1q16HighQPseudo: 1798 case ARM::VST1q16LowQPseudo_UPD: 1799 case ARM::VST1q16HighTPseudo: 1800 case ARM::VST1q16LowTPseudo_UPD: 1801 case ARM::VST1q32HighQPseudo: 1802 case ARM::VST1q32LowQPseudo_UPD: 1803 case ARM::VST1q32HighTPseudo: 1804 case ARM::VST1q32LowTPseudo_UPD: 1805 case ARM::VST1q64HighQPseudo: 1806 case ARM::VST1q64LowQPseudo_UPD: 1807 case ARM::VST1q64HighTPseudo: 1808 case ARM::VST1q64LowTPseudo_UPD: 1809 case ARM::VST4q8Pseudo_UPD: 1810 case ARM::VST4q16Pseudo_UPD: 1811 case ARM::VST4q32Pseudo_UPD: 1812 case ARM::VST4q8oddPseudo: 1813 case ARM::VST4q16oddPseudo: 1814 case ARM::VST4q32oddPseudo: 1815 case ARM::VST4q8oddPseudo_UPD: 1816 case ARM::VST4q16oddPseudo_UPD: 1817 case ARM::VST4q32oddPseudo_UPD: 1818 ExpandVST(MBBI); 1819 return true; 1820 1821 case ARM::VLD1LNq8Pseudo: 1822 case ARM::VLD1LNq16Pseudo: 1823 case ARM::VLD1LNq32Pseudo: 1824 case ARM::VLD1LNq8Pseudo_UPD: 1825 case ARM::VLD1LNq16Pseudo_UPD: 1826 case ARM::VLD1LNq32Pseudo_UPD: 1827 case ARM::VLD2LNd8Pseudo: 1828 case ARM::VLD2LNd16Pseudo: 1829 case ARM::VLD2LNd32Pseudo: 1830 case ARM::VLD2LNq16Pseudo: 1831 case ARM::VLD2LNq32Pseudo: 1832 case ARM::VLD2LNd8Pseudo_UPD: 1833 case ARM::VLD2LNd16Pseudo_UPD: 1834 case ARM::VLD2LNd32Pseudo_UPD: 1835 case ARM::VLD2LNq16Pseudo_UPD: 1836 case ARM::VLD2LNq32Pseudo_UPD: 1837 case ARM::VLD3LNd8Pseudo: 1838 case ARM::VLD3LNd16Pseudo: 1839 case ARM::VLD3LNd32Pseudo: 1840 case ARM::VLD3LNq16Pseudo: 1841 case ARM::VLD3LNq32Pseudo: 1842 case ARM::VLD3LNd8Pseudo_UPD: 1843 case ARM::VLD3LNd16Pseudo_UPD: 1844 case ARM::VLD3LNd32Pseudo_UPD: 1845 case ARM::VLD3LNq16Pseudo_UPD: 1846 case ARM::VLD3LNq32Pseudo_UPD: 1847 case ARM::VLD4LNd8Pseudo: 1848 case ARM::VLD4LNd16Pseudo: 1849 case ARM::VLD4LNd32Pseudo: 1850 case ARM::VLD4LNq16Pseudo: 1851 case ARM::VLD4LNq32Pseudo: 1852 case ARM::VLD4LNd8Pseudo_UPD: 1853 case ARM::VLD4LNd16Pseudo_UPD: 1854 case ARM::VLD4LNd32Pseudo_UPD: 1855 case ARM::VLD4LNq16Pseudo_UPD: 1856 case ARM::VLD4LNq32Pseudo_UPD: 1857 case ARM::VST1LNq8Pseudo: 1858 case ARM::VST1LNq16Pseudo: 1859 case ARM::VST1LNq32Pseudo: 1860 case ARM::VST1LNq8Pseudo_UPD: 1861 case ARM::VST1LNq16Pseudo_UPD: 1862 case ARM::VST1LNq32Pseudo_UPD: 1863 case ARM::VST2LNd8Pseudo: 1864 case ARM::VST2LNd16Pseudo: 1865 case ARM::VST2LNd32Pseudo: 1866 case ARM::VST2LNq16Pseudo: 1867 case ARM::VST2LNq32Pseudo: 1868 case ARM::VST2LNd8Pseudo_UPD: 1869 case ARM::VST2LNd16Pseudo_UPD: 1870 case ARM::VST2LNd32Pseudo_UPD: 1871 case ARM::VST2LNq16Pseudo_UPD: 1872 case ARM::VST2LNq32Pseudo_UPD: 1873 case ARM::VST3LNd8Pseudo: 1874 case ARM::VST3LNd16Pseudo: 1875 case ARM::VST3LNd32Pseudo: 1876 case ARM::VST3LNq16Pseudo: 1877 case ARM::VST3LNq32Pseudo: 1878 case ARM::VST3LNd8Pseudo_UPD: 1879 case ARM::VST3LNd16Pseudo_UPD: 1880 case ARM::VST3LNd32Pseudo_UPD: 1881 case ARM::VST3LNq16Pseudo_UPD: 1882 case ARM::VST3LNq32Pseudo_UPD: 1883 case ARM::VST4LNd8Pseudo: 1884 case ARM::VST4LNd16Pseudo: 1885 case ARM::VST4LNd32Pseudo: 1886 case ARM::VST4LNq16Pseudo: 1887 case ARM::VST4LNq32Pseudo: 1888 case ARM::VST4LNd8Pseudo_UPD: 1889 case ARM::VST4LNd16Pseudo_UPD: 1890 case ARM::VST4LNd32Pseudo_UPD: 1891 case ARM::VST4LNq16Pseudo_UPD: 1892 case ARM::VST4LNq32Pseudo_UPD: 1893 ExpandLaneOp(MBBI); 1894 return true; 1895 1896 case ARM::VTBL3Pseudo: ExpandVTBL(MBBI, ARM::VTBL3, false); return true; 1897 case ARM::VTBL4Pseudo: ExpandVTBL(MBBI, ARM::VTBL4, false); return true; 1898 case ARM::VTBX3Pseudo: ExpandVTBL(MBBI, ARM::VTBX3, true); return true; 1899 case ARM::VTBX4Pseudo: ExpandVTBL(MBBI, ARM::VTBX4, true); return true; 1900 1901 case ARM::CMP_SWAP_8: 1902 if (STI->isThumb()) 1903 return ExpandCMP_SWAP(MBB, MBBI, ARM::t2LDREXB, ARM::t2STREXB, 1904 ARM::tUXTB, NextMBBI); 1905 else 1906 return ExpandCMP_SWAP(MBB, MBBI, ARM::LDREXB, ARM::STREXB, 1907 ARM::UXTB, NextMBBI); 1908 case ARM::CMP_SWAP_16: 1909 if (STI->isThumb()) 1910 return ExpandCMP_SWAP(MBB, MBBI, ARM::t2LDREXH, ARM::t2STREXH, 1911 ARM::tUXTH, NextMBBI); 1912 else 1913 return ExpandCMP_SWAP(MBB, MBBI, ARM::LDREXH, ARM::STREXH, 1914 ARM::UXTH, NextMBBI); 1915 case ARM::CMP_SWAP_32: 1916 if (STI->isThumb()) 1917 return ExpandCMP_SWAP(MBB, MBBI, ARM::t2LDREX, ARM::t2STREX, 0, 1918 NextMBBI); 1919 else 1920 return ExpandCMP_SWAP(MBB, MBBI, ARM::LDREX, ARM::STREX, 0, NextMBBI); 1921 1922 case ARM::CMP_SWAP_64: 1923 return ExpandCMP_SWAP_64(MBB, MBBI, NextMBBI); 1924 1925 case ARM::tBL_PUSHLR: 1926 case ARM::BL_PUSHLR: { 1927 const bool Thumb = Opcode == ARM::tBL_PUSHLR; 1928 Register Reg = MI.getOperand(0).getReg(); 1929 assert(Reg == ARM::LR && "expect LR register!"); 1930 MachineInstrBuilder MIB; 1931 if (Thumb) { 1932 // push {lr} 1933 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::tPUSH)) 1934 .add(predOps(ARMCC::AL)) 1935 .addReg(Reg); 1936 1937 // bl __gnu_mcount_nc 1938 MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::tBL)); 1939 } else { 1940 // stmdb sp!, {lr} 1941 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::STMDB_UPD)) 1942 .addReg(ARM::SP, RegState::Define) 1943 .addReg(ARM::SP) 1944 .add(predOps(ARMCC::AL)) 1945 .addReg(Reg); 1946 1947 // bl __gnu_mcount_nc 1948 MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::BL)); 1949 } 1950 MIB.cloneMemRefs(MI); 1951 for (unsigned i = 1; i < MI.getNumOperands(); ++i) MIB.add(MI.getOperand(i)); 1952 MI.eraseFromParent(); 1953 return true; 1954 } 1955 } 1956} 1957 1958bool ARMExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) { 1959 bool Modified = false; 1960 1961 MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end(); 1962 while (MBBI != E) { 1963 MachineBasicBlock::iterator NMBBI = std::next(MBBI); 1964 Modified |= ExpandMI(MBB, MBBI, NMBBI); 1965 MBBI = NMBBI; 1966 } 1967 1968 return Modified; 1969} 1970 1971bool ARMExpandPseudo::runOnMachineFunction(MachineFunction &MF) { 1972 STI = &static_cast<const ARMSubtarget &>(MF.getSubtarget()); 1973 TII = STI->getInstrInfo(); 1974 TRI = STI->getRegisterInfo(); 1975 AFI = MF.getInfo<ARMFunctionInfo>(); 1976 1977 LLVM_DEBUG(dbgs() << "********** ARM EXPAND PSEUDO INSTRUCTIONS **********\n" 1978 << "********** Function: " << MF.getName() << '\n'); 1979 1980 bool Modified = false; 1981 for (MachineBasicBlock &MBB : MF) 1982 Modified |= ExpandMBB(MBB); 1983 if (VerifyARMPseudo) 1984 MF.verify(this, "After expanding ARM pseudo instructions."); 1985 1986 LLVM_DEBUG(dbgs() << "***************************************************\n"); 1987 return Modified; 1988} 1989 1990/// createARMExpandPseudoPass - returns an instance of the pseudo instruction 1991/// expansion pass. 1992FunctionPass *llvm::createARMExpandPseudoPass() { 1993 return new ARMExpandPseudo(); 1994} 1995