EvergreenInstructions.td revision 360784
1//===-- EvergreenInstructions.td - EG Instruction defs  ----*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// TableGen definitions for instructions which are:
10// - Available to Evergreen and newer VLIW4/VLIW5 GPUs
11// - Available only on Evergreen family GPUs.
12//
13//===----------------------------------------------------------------------===//
14
15def isEG : Predicate<
16  "Subtarget->getGeneration() >= AMDGPUSubtarget::EVERGREEN && "
17  "!Subtarget->hasCaymanISA()"
18>;
19
20def isEGorCayman : Predicate<
21  "Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||"
22  "Subtarget->getGeneration() == AMDGPUSubtarget::NORTHERN_ISLANDS"
23>;
24
25class EGPat<dag pattern, dag result> : AMDGPUPat<pattern, result> {
26  let SubtargetPredicate = isEG;
27}
28
29class EGOrCaymanPat<dag pattern, dag result> : AMDGPUPat<pattern, result> {
30  let SubtargetPredicate = isEGorCayman;
31}
32
33//===----------------------------------------------------------------------===//
34// Evergreen / Cayman store instructions
35//===----------------------------------------------------------------------===//
36
37let SubtargetPredicate = isEGorCayman in {
38
39class CF_MEM_RAT_CACHELESS <bits<6> rat_inst, bits<4> rat_id, bits<4> mask, dag ins,
40                           string name, list<dag> pattern>
41    : EG_CF_RAT <0x57, rat_inst, rat_id, mask, (outs), ins,
42                 "MEM_RAT_CACHELESS "#name, pattern>;
43
44class CF_MEM_RAT <bits<6> rat_inst, bits<4> rat_id, bits<4> mask, dag ins,
45                  dag outs, string name, list<dag> pattern>
46    : EG_CF_RAT <0x56, rat_inst, rat_id, mask, outs, ins,
47                 "MEM_RAT "#name, pattern>;
48
49class CF_MEM_RAT_STORE_TYPED<bits<1> has_eop>
50    : CF_MEM_RAT <0x1, ?, 0xf, (ins R600_Reg128:$rw_gpr, R600_Reg128:$index_gpr,
51                           i32imm:$rat_id, InstFlag:$eop), (outs),
52                  "STORE_TYPED RAT($rat_id) $rw_gpr, $index_gpr"
53                               #!if(has_eop, ", $eop", ""),
54                  [(int_r600_rat_store_typed R600_Reg128:$rw_gpr,
55                                             R600_Reg128:$index_gpr,
56                                             (i32 imm:$rat_id))]>;
57
58def RAT_MSKOR : CF_MEM_RAT <0x11, 0, 0xf,
59  (ins R600_Reg128:$rw_gpr, R600_TReg32_X:$index_gpr), (outs),
60  "MSKOR $rw_gpr.XW, $index_gpr",
61  [(mskor_global v4i32:$rw_gpr, i32:$index_gpr)]
62> {
63  let eop = 0;
64}
65
66
67multiclass RAT_ATOMIC<bits<6> op_ret, bits<6> op_noret, string name> {
68  let Constraints = "$rw_gpr = $out_gpr", eop = 0, mayStore = 1 in {
69  def  _RTN: CF_MEM_RAT <op_ret, 0, 0xf,
70             (ins R600_Reg128:$rw_gpr, R600_TReg32_X:$index_gpr),
71             (outs R600_Reg128:$out_gpr),
72             name ## "_RTN" ## " $rw_gpr, $index_gpr", [] >;
73  def _NORET: CF_MEM_RAT <op_noret, 0, 0xf,
74              (ins R600_Reg128:$rw_gpr, R600_TReg32_X:$index_gpr),
75              (outs R600_Reg128:$out_gpr),
76              name ## " $rw_gpr, $index_gpr", [] >;
77  }
78}
79
80// Swap no-ret is just store. Raw store to cached target
81// can only store on dword, which exactly matches swap_no_ret.
82defm RAT_ATOMIC_XCHG_INT : RAT_ATOMIC<1, 34, "ATOMIC_XCHG_INT">;
83defm RAT_ATOMIC_CMPXCHG_INT : RAT_ATOMIC<4, 36, "ATOMIC_CMPXCHG_INT">;
84defm RAT_ATOMIC_ADD : RAT_ATOMIC<7, 39, "ATOMIC_ADD">;
85defm RAT_ATOMIC_SUB : RAT_ATOMIC<8, 40, "ATOMIC_SUB">;
86defm RAT_ATOMIC_RSUB : RAT_ATOMIC<9, 41, "ATOMIC_RSUB">;
87defm RAT_ATOMIC_MIN_INT : RAT_ATOMIC<10, 42, "ATOMIC_MIN_INT">;
88defm RAT_ATOMIC_MIN_UINT : RAT_ATOMIC<11, 43, "ATOMIC_MIN_UINT">;
89defm RAT_ATOMIC_MAX_INT : RAT_ATOMIC<12, 44, "ATOMIC_MAX_INT">;
90defm RAT_ATOMIC_MAX_UINT : RAT_ATOMIC<13, 45, "ATOMIC_MAX_UINT">;
91defm RAT_ATOMIC_AND : RAT_ATOMIC<14, 46, "ATOMIC_AND">;
92defm RAT_ATOMIC_OR : RAT_ATOMIC<15, 47, "ATOMIC_OR">;
93defm RAT_ATOMIC_XOR : RAT_ATOMIC<16, 48, "ATOMIC_XOR">;
94defm RAT_ATOMIC_INC_UINT : RAT_ATOMIC<18, 50, "ATOMIC_INC_UINT">;
95defm RAT_ATOMIC_DEC_UINT : RAT_ATOMIC<19, 51, "ATOMIC_DEC_UINT">;
96
97} // End SubtargetPredicate = isEGorCayman
98
99//===----------------------------------------------------------------------===//
100// Evergreen Only instructions
101//===----------------------------------------------------------------------===//
102
103let SubtargetPredicate = isEG in {
104
105def RECIP_IEEE_eg : RECIP_IEEE_Common<0x86>;
106defm DIV_eg : DIV_Common<RECIP_IEEE_eg>;
107
108def MULLO_INT_eg : MULLO_INT_Common<0x8F>;
109def MULHI_INT_eg : MULHI_INT_Common<0x90>;
110def MULLO_UINT_eg : MULLO_UINT_Common<0x91>;
111def MULHI_UINT_eg : MULHI_UINT_Common<0x92>;
112def MULHI_UINT24_eg : MULHI_UINT24_Common<0xb2>;
113
114def RECIP_UINT_eg : RECIP_UINT_Common<0x94>;
115def RECIPSQRT_CLAMPED_eg : RECIPSQRT_CLAMPED_Common<0x87>;
116def EXP_IEEE_eg : EXP_IEEE_Common<0x81>;
117def LOG_IEEE_eg : LOG_IEEE_Common<0x83>;
118def RECIP_CLAMPED_eg : RECIP_CLAMPED_Common<0x84>;
119def RECIPSQRT_IEEE_eg : RECIPSQRT_IEEE_Common<0x89>;
120def : RsqPat<RECIPSQRT_IEEE_eg, f32>;
121def : SqrtPat<RECIPSQRT_IEEE_eg, RECIP_IEEE_eg>;
122
123def SIN_eg : SIN_Common<0x8D>;
124def COS_eg : COS_Common<0x8E>;
125
126def : POW_Common <LOG_IEEE_eg, EXP_IEEE_eg, MUL>;
127} // End SubtargetPredicate = isEG
128
129//===----------------------------------------------------------------------===//
130// Memory read/write instructions
131//===----------------------------------------------------------------------===//
132
133let usesCustomInserter = 1 in {
134
135// 32-bit store
136def RAT_WRITE_CACHELESS_32_eg : CF_MEM_RAT_CACHELESS <0x2, 0, 0x1,
137  (ins R600_TReg32_X:$rw_gpr, R600_TReg32_X:$index_gpr, InstFlag:$eop),
138  "STORE_RAW $rw_gpr, $index_gpr, $eop",
139  [(store_global i32:$rw_gpr, i32:$index_gpr)]
140>;
141
142// 64-bit store
143def RAT_WRITE_CACHELESS_64_eg : CF_MEM_RAT_CACHELESS <0x2, 0, 0x3,
144  (ins R600_Reg64:$rw_gpr, R600_TReg32_X:$index_gpr, InstFlag:$eop),
145  "STORE_RAW $rw_gpr.XY, $index_gpr, $eop",
146  [(store_global v2i32:$rw_gpr, i32:$index_gpr)]
147>;
148
149//128-bit store
150def RAT_WRITE_CACHELESS_128_eg : CF_MEM_RAT_CACHELESS <0x2, 0, 0xf,
151  (ins R600_Reg128:$rw_gpr, R600_TReg32_X:$index_gpr, InstFlag:$eop),
152  "STORE_RAW $rw_gpr.XYZW, $index_gpr, $eop",
153  [(store_global v4i32:$rw_gpr, i32:$index_gpr)]
154>;
155
156def RAT_STORE_TYPED_eg: CF_MEM_RAT_STORE_TYPED<1>;
157
158} // End usesCustomInserter = 1
159
160class VTX_READ_eg <string name, dag outs>
161    : VTX_WORD0_eg, VTX_READ<name, outs, []> {
162
163  // Static fields
164  let VC_INST = 0;
165  let FETCH_TYPE = 2;
166  let FETCH_WHOLE_QUAD = 0;
167  let SRC_REL = 0;
168  // XXX: We can infer this field based on the SRC_GPR.  This would allow us
169  // to store vertex addresses in any channel, not just X.
170  let SRC_SEL_X = 0;
171
172  let Inst{31-0} = Word0;
173}
174
175def VTX_READ_8_eg
176    : VTX_READ_eg <"VTX_READ_8 $dst_gpr, $src_gpr",
177                   (outs R600_TReg32_X:$dst_gpr)> {
178
179  let MEGA_FETCH_COUNT = 1;
180  let DST_SEL_X = 0;
181  let DST_SEL_Y = 7;   // Masked
182  let DST_SEL_Z = 7;   // Masked
183  let DST_SEL_W = 7;   // Masked
184  let DATA_FORMAT = 1; // FMT_8
185}
186
187def VTX_READ_16_eg
188    : VTX_READ_eg <"VTX_READ_16 $dst_gpr, $src_gpr",
189                   (outs R600_TReg32_X:$dst_gpr)> {
190  let MEGA_FETCH_COUNT = 2;
191  let DST_SEL_X = 0;
192  let DST_SEL_Y = 7;   // Masked
193  let DST_SEL_Z = 7;   // Masked
194  let DST_SEL_W = 7;   // Masked
195  let DATA_FORMAT = 5; // FMT_16
196
197}
198
199def VTX_READ_32_eg
200    : VTX_READ_eg <"VTX_READ_32 $dst_gpr, $src_gpr",
201                   (outs R600_TReg32_X:$dst_gpr)> {
202
203  let MEGA_FETCH_COUNT = 4;
204  let DST_SEL_X        = 0;
205  let DST_SEL_Y        = 7;   // Masked
206  let DST_SEL_Z        = 7;   // Masked
207  let DST_SEL_W        = 7;   // Masked
208  let DATA_FORMAT      = 0xD; // COLOR_32
209
210  // This is not really necessary, but there were some GPU hangs that appeared
211  // to be caused by ALU instructions in the next instruction group that wrote
212  // to the $src_gpr registers of the VTX_READ.
213  // e.g.
214  // %t3_x = VTX_READ_PARAM_32_eg killed %t2_x, 24
215  // %t2_x = MOV %zero
216  //Adding this constraint prevents this from happening.
217  let Constraints = "$src_gpr.ptr = $dst_gpr";
218}
219
220def VTX_READ_64_eg
221    : VTX_READ_eg <"VTX_READ_64 $dst_gpr.XY, $src_gpr",
222                   (outs R600_Reg64:$dst_gpr)> {
223
224  let MEGA_FETCH_COUNT = 8;
225  let DST_SEL_X        = 0;
226  let DST_SEL_Y        = 1;
227  let DST_SEL_Z        = 7;
228  let DST_SEL_W        = 7;
229  let DATA_FORMAT      = 0x1D; // COLOR_32_32
230}
231
232def VTX_READ_128_eg
233    : VTX_READ_eg <"VTX_READ_128 $dst_gpr.XYZW, $src_gpr",
234                   (outs R600_Reg128:$dst_gpr)> {
235
236  let MEGA_FETCH_COUNT = 16;
237  let DST_SEL_X        =  0;
238  let DST_SEL_Y        =  1;
239  let DST_SEL_Z        =  2;
240  let DST_SEL_W        =  3;
241  let DATA_FORMAT      =  0x22; // COLOR_32_32_32_32
242
243  // XXX: Need to force VTX_READ_128 instructions to write to the same register
244  // that holds its buffer address to avoid potential hangs.  We can't use
245  // the same constraint as VTX_READ_32_eg, because the $src_gpr.ptr and $dst
246  // registers are different sizes.
247}
248
249//===----------------------------------------------------------------------===//
250// VTX Read from parameter memory space
251//===----------------------------------------------------------------------===//
252def : EGPat<(i32:$dst_gpr (vtx_id3_az_extloadi8 ADDRVTX_READ:$src_gpr)),
253          (VTX_READ_8_eg MEMxi:$src_gpr, 3)>;
254def : EGPat<(i32:$dst_gpr (vtx_id3_az_extloadi16 ADDRVTX_READ:$src_gpr)),
255          (VTX_READ_16_eg MEMxi:$src_gpr, 3)>;
256def : EGPat<(i32:$dst_gpr (vtx_id3_load ADDRVTX_READ:$src_gpr)),
257          (VTX_READ_32_eg MEMxi:$src_gpr, 3)>;
258def : EGPat<(v2i32:$dst_gpr (vtx_id3_load ADDRVTX_READ:$src_gpr)),
259          (VTX_READ_64_eg MEMxi:$src_gpr, 3)>;
260def : EGPat<(v4i32:$dst_gpr (vtx_id3_load ADDRVTX_READ:$src_gpr)),
261          (VTX_READ_128_eg MEMxi:$src_gpr, 3)>;
262
263//===----------------------------------------------------------------------===//
264// VTX Read from constant memory space
265//===----------------------------------------------------------------------===//
266def : EGPat<(i32:$dst_gpr (vtx_id2_az_extloadi8 ADDRVTX_READ:$src_gpr)),
267          (VTX_READ_8_eg MEMxi:$src_gpr, 2)>;
268def : EGPat<(i32:$dst_gpr (vtx_id2_az_extloadi16 ADDRVTX_READ:$src_gpr)),
269          (VTX_READ_16_eg MEMxi:$src_gpr, 2)>;
270def : EGPat<(i32:$dst_gpr (vtx_id2_load ADDRVTX_READ:$src_gpr)),
271          (VTX_READ_32_eg MEMxi:$src_gpr, 2)>;
272def : EGPat<(v2i32:$dst_gpr (vtx_id2_load ADDRVTX_READ:$src_gpr)),
273          (VTX_READ_64_eg MEMxi:$src_gpr, 2)>;
274def : EGPat<(v4i32:$dst_gpr (vtx_id2_load ADDRVTX_READ:$src_gpr)),
275          (VTX_READ_128_eg MEMxi:$src_gpr, 2)>;
276
277//===----------------------------------------------------------------------===//
278// VTX Read from global memory space
279//===----------------------------------------------------------------------===//
280def : EGPat<(i32:$dst_gpr (vtx_id1_az_extloadi8 ADDRVTX_READ:$src_gpr)),
281          (VTX_READ_8_eg MEMxi:$src_gpr, 1)>;
282def : EGPat<(i32:$dst_gpr (vtx_id1_az_extloadi16 ADDRVTX_READ:$src_gpr)),
283          (VTX_READ_16_eg MEMxi:$src_gpr, 1)>;
284def : EGPat<(i32:$dst_gpr (vtx_id1_load ADDRVTX_READ:$src_gpr)),
285          (VTX_READ_32_eg MEMxi:$src_gpr, 1)>;
286def : EGPat<(v2i32:$dst_gpr (vtx_id1_load ADDRVTX_READ:$src_gpr)),
287          (VTX_READ_64_eg MEMxi:$src_gpr, 1)>;
288def : EGPat<(v4i32:$dst_gpr (vtx_id1_load ADDRVTX_READ:$src_gpr)),
289          (VTX_READ_128_eg MEMxi:$src_gpr, 1)>;
290
291//===----------------------------------------------------------------------===//
292// Evergreen / Cayman Instructions
293//===----------------------------------------------------------------------===//
294
295let SubtargetPredicate = isEGorCayman in {
296
297multiclass AtomicPat<Instruction inst_ret, Instruction inst_noret,
298                     SDPatternOperator node_ret, SDPatternOperator node_noret> {
299  // FIXME: Add _RTN version. We need per WI scratch location to store the old value
300  // EXTRACT_SUBREG here is dummy, we know the node has no uses
301  def : EGOrCaymanPat<(i32 (node_noret i32:$ptr, i32:$data)),
302            (EXTRACT_SUBREG (inst_noret
303              (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), $data, sub0), $ptr), sub1)>;
304}
305multiclass AtomicIncDecPat<Instruction inst_ret, Instruction inst_noret,
306                     SDPatternOperator node_ret, SDPatternOperator node_noret, int C> {
307  // FIXME: Add _RTN version. We need per WI scratch location to store the old value
308  // EXTRACT_SUBREG here is dummy, we know the node has no uses
309  def : EGOrCaymanPat<(i32 (node_noret i32:$ptr, C)),
310            (EXTRACT_SUBREG (inst_noret
311              (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), (MOV_IMM_I32 -1), sub0), $ptr), sub1)>;
312}
313
314// CMPSWAP is pattern is special
315// EXTRACT_SUBREG here is dummy, we know the node has no uses
316// FIXME: Add _RTN version. We need per WI scratch location to store the old value
317def : EGOrCaymanPat<(i32 (atomic_cmp_swap_global_noret i32:$ptr, i32:$cmp, i32:$data)),
318          (EXTRACT_SUBREG (RAT_ATOMIC_CMPXCHG_INT_NORET
319            (INSERT_SUBREG
320              (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), $cmp, sub3),
321            $data, sub0),
322          $ptr), sub1)>;
323
324defm AtomicSwapPat : AtomicPat <RAT_ATOMIC_XCHG_INT_RTN,
325                                RAT_ATOMIC_XCHG_INT_NORET,
326                                atomic_swap_global_ret_32,
327                                atomic_swap_global_noret_32>;
328defm AtomicAddPat : AtomicPat <RAT_ATOMIC_ADD_RTN, RAT_ATOMIC_ADD_NORET,
329                               atomic_load_add_global_ret_32, atomic_load_add_global_noret_32>;
330defm AtomicSubPat : AtomicPat <RAT_ATOMIC_SUB_RTN, RAT_ATOMIC_SUB_NORET,
331                               atomic_load_sub_global_ret_32, atomic_load_sub_global_noret_32>;
332defm AtomicMinPat : AtomicPat <RAT_ATOMIC_MIN_INT_RTN,
333                               RAT_ATOMIC_MIN_INT_NORET,
334                               atomic_load_min_global_ret_32, atomic_load_min_global_noret_32>;
335defm AtomicUMinPat : AtomicPat <RAT_ATOMIC_MIN_UINT_RTN,
336                                RAT_ATOMIC_MIN_UINT_NORET,
337                                atomic_load_umin_global_ret_32, atomic_load_umin_global_noret_32>;
338defm AtomicMaxPat : AtomicPat <RAT_ATOMIC_MAX_INT_RTN,
339                               RAT_ATOMIC_MAX_INT_NORET,
340                               atomic_load_max_global_ret_32, atomic_load_max_global_noret_32>;
341defm AtomicUMaxPat : AtomicPat <RAT_ATOMIC_MAX_UINT_RTN,
342                                RAT_ATOMIC_MAX_UINT_NORET,
343                                atomic_load_umax_global_ret_32, atomic_load_umax_global_noret_32>;
344defm AtomicAndPat : AtomicPat <RAT_ATOMIC_AND_RTN, RAT_ATOMIC_AND_NORET,
345                               atomic_load_and_global_ret_32, atomic_load_and_global_noret_32>;
346defm AtomicOrPat : AtomicPat <RAT_ATOMIC_OR_RTN, RAT_ATOMIC_OR_NORET,
347                              atomic_load_or_global_ret_32, atomic_load_or_global_noret_32>;
348defm AtomicXorPat : AtomicPat <RAT_ATOMIC_XOR_RTN, RAT_ATOMIC_XOR_NORET,
349                               atomic_load_xor_global_ret_32, atomic_load_xor_global_noret_32>;
350defm AtomicIncAddPat : AtomicIncDecPat <RAT_ATOMIC_INC_UINT_RTN,
351                                        RAT_ATOMIC_INC_UINT_NORET,
352                                        atomic_load_add_global_ret_32,
353                                        atomic_load_add_global_noret_32, 1>;
354defm AtomicIncSubPat : AtomicIncDecPat <RAT_ATOMIC_INC_UINT_RTN,
355                                        RAT_ATOMIC_INC_UINT_NORET,
356                                        atomic_load_sub_global_ret_32,
357                                        atomic_load_sub_global_noret_32, -1>;
358defm AtomicDecAddPat : AtomicIncDecPat <RAT_ATOMIC_DEC_UINT_RTN,
359                                        RAT_ATOMIC_DEC_UINT_NORET,
360                                        atomic_load_add_global_ret_32,
361                                        atomic_load_add_global_noret_32, -1>;
362defm AtomicDecSubPat : AtomicIncDecPat <RAT_ATOMIC_DEC_UINT_RTN,
363                                        RAT_ATOMIC_DEC_UINT_NORET,
364                                        atomic_load_sub_global_ret_32,
365                                        atomic_load_sub_global_noret_32, 1>;
366
367// Should be predicated on FeatureFP64
368// def FMA_64 : R600_3OP <
369//   0xA, "FMA_64",
370//   [(set f64:$dst, (fma f64:$src0, f64:$src1, f64:$src2))]
371// >;
372
373// BFE_UINT - bit_extract, an optimization for mask and shift
374// Src0 = Input
375// Src1 = Offset
376// Src2 = Width
377//
378// bit_extract = (Input << (32 - Offset - Width)) >> (32 - Width)
379//
380// Example Usage:
381// (Offset, Width)
382//
383// (0, 8)  = (Input << 24) >> 24 = (Input &  0xff)       >> 0
384// (8, 8)  = (Input << 16) >> 24 = (Input &  0xffff)     >> 8
385// (16, 8) = (Input <<  8) >> 24 = (Input &  0xffffff)   >> 16
386// (24, 8) = (Input <<  0) >> 24 = (Input &  0xffffffff) >> 24
387def BFE_UINT_eg : R600_3OP <0x4, "BFE_UINT",
388  [(set i32:$dst, (AMDGPUbfe_u32 i32:$src0, i32:$src1, i32:$src2))],
389  VecALU
390>;
391
392def BFE_INT_eg : R600_3OP <0x5, "BFE_INT",
393  [(set i32:$dst, (AMDGPUbfe_i32 i32:$src0, i32:$src1, i32:$src2))],
394  VecALU
395>;
396
397defm : BFEPattern <BFE_UINT_eg, BFE_INT_eg, MOV_IMM_I32>;
398
399def BFI_INT_eg : R600_3OP <0x06, "BFI_INT",
400  [(set i32:$dst, (AMDGPUbfi i32:$src0, i32:$src1, i32:$src2))],
401  VecALU
402>;
403
404def : EGOrCaymanPat<(i32 (sext_inreg i32:$src, i1)),
405  (BFE_INT_eg i32:$src, (i32 ZERO), (i32 ONE_INT))>;
406def : EGOrCaymanPat<(i32 (sext_inreg i32:$src, i8)),
407  (BFE_INT_eg i32:$src, (i32 ZERO), (MOV_IMM_I32 8))>;
408def : EGOrCaymanPat<(i32 (sext_inreg i32:$src, i16)),
409  (BFE_INT_eg i32:$src, (i32 ZERO), (MOV_IMM_I32 16))>;
410
411defm : BFIPatterns <BFI_INT_eg, MOV_IMM_I32, R600_Reg64>;
412
413def BFM_INT_eg : R600_2OP <0xA0, "BFM_INT",
414  [(set i32:$dst, (AMDGPUbfm i32:$src0, i32:$src1))],
415  VecALU
416>;
417
418def MULADD_UINT24_eg : R600_3OP <0x10, "MULADD_UINT24",
419  [(set i32:$dst, (AMDGPUmad_u24 i32:$src0, i32:$src1, i32:$src2))], VecALU
420>;
421
422def : UMad24Pat<MULADD_UINT24_eg>;
423
424def BIT_ALIGN_INT_eg : R600_3OP <0xC, "BIT_ALIGN_INT", [], VecALU>;
425def : ROTRPattern <BIT_ALIGN_INT_eg>;
426def MULADD_eg : MULADD_Common<0x14>;
427def MULADD_IEEE_eg : MULADD_IEEE_Common<0x18>;
428def FMA_eg : FMA_Common<0x7>;
429def ASHR_eg : ASHR_Common<0x15>;
430def LSHR_eg : LSHR_Common<0x16>;
431def LSHL_eg : LSHL_Common<0x17>;
432def CNDE_eg : CNDE_Common<0x19>;
433def CNDGT_eg : CNDGT_Common<0x1A>;
434def CNDGE_eg : CNDGE_Common<0x1B>;
435def MUL_LIT_eg : MUL_LIT_Common<0x1F>;
436def LOG_CLAMPED_eg : LOG_CLAMPED_Common<0x82>;
437def MUL_UINT24_eg : R600_2OP <0xB5, "MUL_UINT24",
438  [(set i32:$dst, (AMDGPUmul_u24 i32:$src0, i32:$src1))], VecALU
439>;
440def DOT4_eg : DOT4_Common<0xBE>;
441defm CUBE_eg : CUBE_Common<0xC0>;
442
443
444def ADDC_UINT : R600_2OP_Helper <0x52, "ADDC_UINT", AMDGPUcarry>;
445def SUBB_UINT : R600_2OP_Helper <0x53, "SUBB_UINT", AMDGPUborrow>;
446
447def FLT32_TO_FLT16 : R600_1OP_Helper <0xA2, "FLT32_TO_FLT16", AMDGPUfp_to_f16, VecALU>;
448def FLT16_TO_FLT32 : R600_1OP_Helper <0xA3, "FLT16_TO_FLT32", f16_to_fp, VecALU>;
449def BCNT_INT : R600_1OP_Helper <0xAA, "BCNT_INT", ctpop, VecALU>;
450def FFBH_UINT : R600_1OP_Helper <0xAB, "FFBH_UINT", AMDGPUffbh_u32, VecALU>;
451def FFBL_INT : R600_1OP_Helper <0xAC, "FFBL_INT", AMDGPUffbl_b32, VecALU>;
452
453let hasSideEffects = 1 in {
454  def MOVA_INT_eg : R600_1OP <0xCC, "MOVA_INT", [], VecALU>;
455}
456
457def FLT_TO_INT_eg : FLT_TO_INT_Common<0x50> {
458  let Pattern = [];
459  let Itinerary = AnyALU;
460}
461
462def INT_TO_FLT_eg : INT_TO_FLT_Common<0x9B>;
463
464def FLT_TO_UINT_eg : FLT_TO_UINT_Common<0x9A> {
465  let Pattern = [];
466}
467
468def UINT_TO_FLT_eg : UINT_TO_FLT_Common<0x9C>;
469
470def GROUP_BARRIER : InstR600 <
471    (outs), (ins), "  GROUP_BARRIER", [(int_r600_group_barrier)], AnyALU>,
472    R600ALU_Word0,
473    R600ALU_Word1_OP2 <0x54> {
474
475  let dst = 0;
476  let dst_rel = 0;
477  let src0 = 0;
478  let src0_rel = 0;
479  let src0_neg = 0;
480  let src0_abs = 0;
481  let src1 = 0;
482  let src1_rel = 0;
483  let src1_neg = 0;
484  let src1_abs = 0;
485  let write = 0;
486  let omod = 0;
487  let clamp = 0;
488  let last = 1;
489  let bank_swizzle = 0;
490  let pred_sel = 0;
491  let update_exec_mask = 0;
492  let update_pred = 0;
493
494  let Inst{31-0}  = Word0;
495  let Inst{63-32} = Word1;
496
497  let ALUInst = 1;
498}
499
500//===----------------------------------------------------------------------===//
501// LDS Instructions
502//===----------------------------------------------------------------------===//
503class R600_LDS  <bits<6> op, dag outs, dag ins, string asm,
504                 list<dag> pattern = []> :
505
506    InstR600 <outs, ins, asm, pattern, XALU>,
507    R600_ALU_LDS_Word0,
508    R600LDS_Word1 {
509
510  bits<6>  offset = 0;
511  let lds_op = op;
512
513  let Word1{27} = offset{0};
514  let Word1{12} = offset{1};
515  let Word1{28} = offset{2};
516  let Word1{31} = offset{3};
517  let Word0{12} = offset{4};
518  let Word0{25} = offset{5};
519
520
521  let Inst{31-0}  = Word0;
522  let Inst{63-32} = Word1;
523
524  let ALUInst = 1;
525  let HasNativeOperands = 1;
526  let UseNamedOperandTable = 1;
527}
528
529class R600_LDS_1A <bits<6> lds_op, string name, list<dag> pattern> : R600_LDS <
530  lds_op,
531  (outs R600_Reg32:$dst),
532  (ins R600_Reg32:$src0, REL:$src0_rel, SEL:$src0_sel,
533       LAST:$last, R600_Pred:$pred_sel,
534       BANK_SWIZZLE:$bank_swizzle),
535  "  "#name#" $last OQAP, $src0$src0_rel $pred_sel",
536  pattern
537  > {
538
539  let src1 = 0;
540  let src1_rel = 0;
541  let src2 = 0;
542  let src2_rel = 0;
543
544  let usesCustomInserter = 1;
545  let LDS_1A = 1;
546  let DisableEncoding = "$dst";
547}
548
549class R600_LDS_1A1D <bits<6> lds_op, dag outs, string name, list<dag> pattern,
550                     string dst =""> :
551    R600_LDS <
552  lds_op, outs,
553  (ins R600_Reg32:$src0, REL:$src0_rel, SEL:$src0_sel,
554       R600_Reg32:$src1, REL:$src1_rel, SEL:$src1_sel,
555       LAST:$last, R600_Pred:$pred_sel,
556       BANK_SWIZZLE:$bank_swizzle),
557  "  "#name#" $last "#dst#"$src0$src0_rel, $src1$src1_rel, $pred_sel",
558  pattern
559  > {
560
561  field string BaseOp;
562
563  let src2 = 0;
564  let src2_rel = 0;
565  let LDS_1A1D = 1;
566}
567
568class R600_LDS_1A1D_NORET <bits<6> lds_op, string name, list<dag> pattern> :
569    R600_LDS_1A1D <lds_op, (outs), name, pattern> {
570  let BaseOp = name;
571}
572
573class R600_LDS_1A1D_RET <bits<6> lds_op, string name, list<dag> pattern> :
574    R600_LDS_1A1D <lds_op,  (outs R600_Reg32:$dst), name##"_RET", pattern, "OQAP, "> {
575
576  let BaseOp = name;
577  let usesCustomInserter = 1;
578  let DisableEncoding = "$dst";
579}
580
581class R600_LDS_1A2D <bits<6> lds_op, dag outs, string name, list<dag> pattern,
582                     string dst =""> :
583    R600_LDS <
584  lds_op, outs,
585  (ins R600_Reg32:$src0, REL:$src0_rel, SEL:$src0_sel,
586       R600_Reg32:$src1, REL:$src1_rel, SEL:$src1_sel,
587       R600_Reg32:$src2, REL:$src2_rel, SEL:$src2_sel,
588       LAST:$last, R600_Pred:$pred_sel, BANK_SWIZZLE:$bank_swizzle),
589  "  "#name# "$last "#dst#"$src0$src0_rel, $src1$src1_rel, $src2$src2_rel, $pred_sel",
590  pattern> {
591
592  field string BaseOp;
593
594  let LDS_1A1D = 0;
595  let LDS_1A2D = 1;
596}
597
598class R600_LDS_1A2D_NORET <bits<6> lds_op, string name, list<dag> pattern> :
599    R600_LDS_1A2D <lds_op, (outs), name, pattern> {
600  let BaseOp = name;
601}
602
603class R600_LDS_1A2D_RET <bits<6> lds_op, string name, list<dag> pattern> :
604    R600_LDS_1A2D <lds_op, (outs R600_Reg32:$dst), name, pattern> {
605
606  let BaseOp = name;
607  let usesCustomInserter = 1;
608  let DisableEncoding = "$dst";
609}
610
611def LDS_ADD : R600_LDS_1A1D_NORET <0x0, "LDS_ADD", [] >;
612def LDS_SUB : R600_LDS_1A1D_NORET <0x1, "LDS_SUB", [] >;
613def LDS_AND : R600_LDS_1A1D_NORET <0x9, "LDS_AND", [] >;
614def LDS_OR : R600_LDS_1A1D_NORET <0xa, "LDS_OR", [] >;
615def LDS_XOR : R600_LDS_1A1D_NORET <0xb, "LDS_XOR", [] >;
616def LDS_WRXCHG: R600_LDS_1A1D_NORET <0xd, "LDS_WRXCHG", [] >;
617def LDS_CMPST: R600_LDS_1A2D_NORET <0x10, "LDS_CMPST", [] >;
618def LDS_MIN_INT : R600_LDS_1A1D_NORET <0x5, "LDS_MIN_INT", [] >;
619def LDS_MAX_INT : R600_LDS_1A1D_NORET <0x6, "LDS_MAX_INT", [] >;
620def LDS_MIN_UINT : R600_LDS_1A1D_NORET <0x7, "LDS_MIN_UINT", [] >;
621def LDS_MAX_UINT : R600_LDS_1A1D_NORET <0x8, "LDS_MAX_UINT", [] >;
622def LDS_WRITE : R600_LDS_1A1D_NORET <0xD, "LDS_WRITE",
623  [(store_local (i32 R600_Reg32:$src1), R600_Reg32:$src0)]
624>;
625def LDS_BYTE_WRITE : R600_LDS_1A1D_NORET<0x12, "LDS_BYTE_WRITE",
626  [(truncstorei8_local i32:$src1, i32:$src0)]
627>;
628def LDS_SHORT_WRITE : R600_LDS_1A1D_NORET<0x13, "LDS_SHORT_WRITE",
629  [(truncstorei16_local i32:$src1, i32:$src0)]
630>;
631def LDS_ADD_RET : R600_LDS_1A1D_RET <0x20, "LDS_ADD",
632  [(set i32:$dst, (atomic_load_add_local_32 i32:$src0, i32:$src1))]
633>;
634def LDS_SUB_RET : R600_LDS_1A1D_RET <0x21, "LDS_SUB",
635  [(set i32:$dst, (atomic_load_sub_local_32 i32:$src0, i32:$src1))]
636>;
637def LDS_AND_RET : R600_LDS_1A1D_RET <0x29, "LDS_AND",
638  [(set i32:$dst, (atomic_load_and_local_32 i32:$src0, i32:$src1))]
639>;
640def LDS_OR_RET : R600_LDS_1A1D_RET <0x2a, "LDS_OR",
641  [(set i32:$dst, (atomic_load_or_local_32 i32:$src0, i32:$src1))]
642>;
643def LDS_XOR_RET : R600_LDS_1A1D_RET <0x2b, "LDS_XOR",
644  [(set i32:$dst, (atomic_load_xor_local_32 i32:$src0, i32:$src1))]
645>;
646def LDS_MIN_INT_RET : R600_LDS_1A1D_RET <0x25, "LDS_MIN_INT",
647  [(set i32:$dst, (atomic_load_min_local_32 i32:$src0, i32:$src1))]
648>;
649def LDS_MAX_INT_RET : R600_LDS_1A1D_RET <0x26, "LDS_MAX_INT",
650  [(set i32:$dst, (atomic_load_max_local_32 i32:$src0, i32:$src1))]
651>;
652def LDS_MIN_UINT_RET : R600_LDS_1A1D_RET <0x27, "LDS_MIN_UINT",
653  [(set i32:$dst, (atomic_load_umin_local_32 i32:$src0, i32:$src1))]
654>;
655def LDS_MAX_UINT_RET : R600_LDS_1A1D_RET <0x28, "LDS_MAX_UINT",
656  [(set i32:$dst, (atomic_load_umax_local_32 i32:$src0, i32:$src1))]
657>;
658def LDS_WRXCHG_RET : R600_LDS_1A1D_RET <0x2d, "LDS_WRXCHG",
659  [(set i32:$dst, (atomic_swap_local_32 i32:$src0, i32:$src1))]
660>;
661def LDS_CMPST_RET : R600_LDS_1A2D_RET <0x30, "LDS_CMPST",
662  [(set i32:$dst, (atomic_cmp_swap_local_32 i32:$src0, i32:$src1, i32:$src2))]
663>;
664def LDS_READ_RET : R600_LDS_1A <0x32, "LDS_READ_RET",
665  [(set (i32 R600_Reg32:$dst), (load_local R600_Reg32:$src0))]
666>;
667def LDS_BYTE_READ_RET : R600_LDS_1A <0x36, "LDS_BYTE_READ_RET",
668  [(set i32:$dst, (sextloadi8_local i32:$src0))]
669>;
670def LDS_UBYTE_READ_RET : R600_LDS_1A <0x37, "LDS_UBYTE_READ_RET",
671  [(set i32:$dst, (az_extloadi8_local i32:$src0))]
672>;
673def LDS_SHORT_READ_RET : R600_LDS_1A <0x38, "LDS_SHORT_READ_RET",
674  [(set i32:$dst, (sextloadi16_local i32:$src0))]
675>;
676def LDS_USHORT_READ_RET : R600_LDS_1A <0x39, "LDS_USHORT_READ_RET",
677  [(set i32:$dst, (az_extloadi16_local i32:$src0))]
678>;
679
680// TRUNC is used for the FLT_TO_INT instructions to work around a
681// perceived problem where the rounding modes are applied differently
682// depending on the instruction and the slot they are in.
683// See:
684// https://bugs.freedesktop.org/show_bug.cgi?id=50232
685// Mesa commit: a1a0974401c467cb86ef818f22df67c21774a38c
686//
687// XXX: Lowering SELECT_CC will sometimes generate fp_to_[su]int nodes,
688// which do not need to be truncated since the fp values are 0.0f or 1.0f.
689// We should look into handling these cases separately.
690def : EGOrCaymanPat<(fp_to_sint f32:$src0), (FLT_TO_INT_eg (TRUNC $src0))>;
691
692def : EGOrCaymanPat<(fp_to_uint f32:$src0), (FLT_TO_UINT_eg (TRUNC $src0))>;
693
694// SHA-256 Patterns
695defm : SHA256MaPattern <BFI_INT_eg, XOR_INT, R600_Reg64>;
696
697def EG_ExportSwz : ExportSwzInst {
698  let Word1{19-16} = 0; // BURST_COUNT
699  let Word1{20} = 0; // VALID_PIXEL_MODE
700  let Word1{21} = eop;
701  let Word1{29-22} = inst;
702  let Word1{30} = 0; // MARK
703  let Word1{31} = 1; // BARRIER
704}
705defm : ExportPattern<EG_ExportSwz, 83>;
706
707def EG_ExportBuf : ExportBufInst {
708  let Word1{19-16} = 0; // BURST_COUNT
709  let Word1{20} = 0; // VALID_PIXEL_MODE
710  let Word1{21} = eop;
711  let Word1{29-22} = inst;
712  let Word1{30} = 0; // MARK
713  let Word1{31} = 1; // BARRIER
714}
715defm : SteamOutputExportPattern<EG_ExportBuf, 0x40, 0x41, 0x42, 0x43>;
716
717def CF_TC_EG : CF_CLAUSE_EG<1, (ins i32imm:$ADDR, i32imm:$COUNT),
718  "TEX $COUNT @$ADDR"> {
719  let POP_COUNT = 0;
720}
721def CF_VC_EG : CF_CLAUSE_EG<2, (ins i32imm:$ADDR, i32imm:$COUNT),
722  "VTX $COUNT @$ADDR"> {
723  let POP_COUNT = 0;
724}
725def WHILE_LOOP_EG : CF_CLAUSE_EG<6, (ins i32imm:$ADDR),
726  "LOOP_START_DX10 @$ADDR"> {
727  let POP_COUNT = 0;
728  let COUNT = 0;
729}
730def END_LOOP_EG : CF_CLAUSE_EG<5, (ins i32imm:$ADDR), "END_LOOP @$ADDR"> {
731  let POP_COUNT = 0;
732  let COUNT = 0;
733}
734def LOOP_BREAK_EG : CF_CLAUSE_EG<9, (ins i32imm:$ADDR),
735  "LOOP_BREAK @$ADDR"> {
736  let POP_COUNT = 0;
737  let COUNT = 0;
738}
739def CF_CONTINUE_EG : CF_CLAUSE_EG<8, (ins i32imm:$ADDR),
740  "CONTINUE @$ADDR"> {
741  let POP_COUNT = 0;
742  let COUNT = 0;
743}
744def CF_JUMP_EG : CF_CLAUSE_EG<10, (ins i32imm:$ADDR, i32imm:$POP_COUNT),
745  "JUMP @$ADDR POP:$POP_COUNT"> {
746  let COUNT = 0;
747}
748def CF_PUSH_EG : CF_CLAUSE_EG<11, (ins i32imm:$ADDR, i32imm:$POP_COUNT),
749                              "PUSH @$ADDR POP:$POP_COUNT"> {
750  let COUNT = 0;
751}
752def CF_ELSE_EG : CF_CLAUSE_EG<13, (ins i32imm:$ADDR, i32imm:$POP_COUNT),
753  "ELSE @$ADDR POP:$POP_COUNT"> {
754  let COUNT = 0;
755}
756def CF_CALL_FS_EG : CF_CLAUSE_EG<19, (ins), "CALL_FS"> {
757  let ADDR = 0;
758  let COUNT = 0;
759  let POP_COUNT = 0;
760}
761def POP_EG : CF_CLAUSE_EG<14, (ins i32imm:$ADDR, i32imm:$POP_COUNT),
762  "POP @$ADDR POP:$POP_COUNT"> {
763  let COUNT = 0;
764}
765def CF_END_EG :  CF_CLAUSE_EG<0, (ins), "CF_END"> {
766  let COUNT = 0;
767  let POP_COUNT = 0;
768  let ADDR = 0;
769  let END_OF_PROGRAM = 1;
770}
771
772} // End Predicates = [isEGorCayman]
773