CaymanInstructions.td revision 360784
1//===-- CaymanInstructions.td - CM Instruction defs -------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// TableGen definitions for instructions which are available only on Cayman 10// family GPUs. 11// 12//===----------------------------------------------------------------------===// 13 14def isCayman : Predicate<"Subtarget->hasCaymanISA()">; 15 16//===----------------------------------------------------------------------===// 17// Cayman Instructions 18//===----------------------------------------------------------------------===// 19 20let SubtargetPredicate = isCayman in { 21 22def MULADD_INT24_cm : R600_3OP <0x08, "MULADD_INT24", 23 [(set i32:$dst, (AMDGPUmad_i24 i32:$src0, i32:$src1, i32:$src2))], VecALU 24>; 25def MUL_INT24_cm : R600_2OP <0x5B, "MUL_INT24", 26 [(set i32:$dst, (AMDGPUmul_i24 i32:$src0, i32:$src1))], VecALU 27>; 28 29def : IMad24Pat<MULADD_INT24_cm>; 30 31let isVector = 1 in { 32 33def RECIP_IEEE_cm : RECIP_IEEE_Common<0x86>; 34 35def MULLO_INT_cm : MULLO_INT_Common<0x8F>; 36def MULHI_INT_cm : MULHI_INT_Common<0x90>; 37def MULLO_UINT_cm : MULLO_UINT_Common<0x91>; 38def MULHI_UINT_cm : MULHI_UINT_Common<0x92>; 39def MULHI_INT_cm24 : MULHI_INT24_Common<0x5c>; 40def MULHI_UINT_cm24 : MULHI_UINT24_Common<0xb2>; 41 42def RECIPSQRT_CLAMPED_cm : RECIPSQRT_CLAMPED_Common<0x87>; 43def EXP_IEEE_cm : EXP_IEEE_Common<0x81>; 44def LOG_IEEE_cm : LOG_IEEE_Common<0x83>; 45def RECIP_CLAMPED_cm : RECIP_CLAMPED_Common<0x84>; 46def RECIPSQRT_IEEE_cm : RECIPSQRT_IEEE_Common<0x89>; 47def SIN_cm : SIN_Common<0x8D>; 48def COS_cm : COS_Common<0x8E>; 49} // End isVector = 1 50 51def : RsqPat<RECIPSQRT_IEEE_cm, f32>; 52 53def : SqrtPat<RECIPSQRT_IEEE_cm, RECIP_IEEE_cm>; 54 55def : POW_Common <LOG_IEEE_cm, EXP_IEEE_cm, MUL>; 56 57defm DIV_cm : DIV_Common<RECIP_IEEE_cm>; 58 59// RECIP_UINT emulation for Cayman 60// The multiplication scales from [0,1] to the unsigned integer range 61def : R600Pat < 62 (AMDGPUurecip i32:$src0), 63 (FLT_TO_UINT_eg (MUL_IEEE (RECIP_IEEE_cm (UINT_TO_FLT_eg $src0)), 64 (MOV_IMM_I32 CONST.FP_UINT_MAX_PLUS_1))) 65>; 66 67def CF_END_CM : CF_CLAUSE_EG<32, (ins), "CF_END"> { 68 let ADDR = 0; 69 let POP_COUNT = 0; 70 let COUNT = 0; 71 } 72 73 74 75class RAT_STORE_DWORD <RegisterClass rc, ValueType vt, bits<4> mask> : 76 CF_MEM_RAT_CACHELESS <0x14, 0, mask, 77 (ins rc:$rw_gpr, R600_TReg32_X:$index_gpr), 78 "STORE_DWORD $rw_gpr, $index_gpr", 79 [(store_global vt:$rw_gpr, i32:$index_gpr)]> { 80 let eop = 0; // This bit is not used on Cayman. 81} 82 83def RAT_STORE_DWORD32 : RAT_STORE_DWORD <R600_TReg32_X, i32, 0x1>; 84def RAT_STORE_DWORD64 : RAT_STORE_DWORD <R600_Reg64, v2i32, 0x3>; 85def RAT_STORE_DWORD128 : RAT_STORE_DWORD <R600_Reg128, v4i32, 0xf>; 86 87def RAT_STORE_TYPED_cm: CF_MEM_RAT_STORE_TYPED<0> { 88 let eop = 0; // This bit is not used on Cayman. 89} 90 91class VTX_READ_cm <string name, dag outs> 92 : VTX_WORD0_cm, VTX_READ<name, outs, []> { 93 94 // Static fields 95 let VC_INST = 0; 96 let FETCH_TYPE = 2; 97 let FETCH_WHOLE_QUAD = 0; 98 let SRC_REL = 0; 99 // XXX: We can infer this field based on the SRC_GPR. This would allow us 100 // to store vertex addresses in any channel, not just X. 101 let SRC_SEL_X = 0; 102 let SRC_SEL_Y = 0; 103 let STRUCTURED_READ = 0; 104 let LDS_REQ = 0; 105 let COALESCED_READ = 0; 106 107 let Inst{31-0} = Word0; 108} 109 110def VTX_READ_8_cm 111 : VTX_READ_cm <"VTX_READ_8 $dst_gpr, $src_gpr", 112 (outs R600_TReg32_X:$dst_gpr)> { 113 114 let DST_SEL_X = 0; 115 let DST_SEL_Y = 7; // Masked 116 let DST_SEL_Z = 7; // Masked 117 let DST_SEL_W = 7; // Masked 118 let DATA_FORMAT = 1; // FMT_8 119} 120 121def VTX_READ_16_cm 122 : VTX_READ_cm <"VTX_READ_16 $dst_gpr, $src_gpr", 123 (outs R600_TReg32_X:$dst_gpr)> { 124 let DST_SEL_X = 0; 125 let DST_SEL_Y = 7; // Masked 126 let DST_SEL_Z = 7; // Masked 127 let DST_SEL_W = 7; // Masked 128 let DATA_FORMAT = 5; // FMT_16 129 130} 131 132def VTX_READ_32_cm 133 : VTX_READ_cm <"VTX_READ_32 $dst_gpr, $src_gpr", 134 (outs R600_TReg32_X:$dst_gpr)> { 135 136 let DST_SEL_X = 0; 137 let DST_SEL_Y = 7; // Masked 138 let DST_SEL_Z = 7; // Masked 139 let DST_SEL_W = 7; // Masked 140 let DATA_FORMAT = 0xD; // COLOR_32 141 142 // This is not really necessary, but there were some GPU hangs that appeared 143 // to be caused by ALU instructions in the next instruction group that wrote 144 // to the $src_gpr registers of the VTX_READ. 145 // e.g. 146 // %t3_x = VTX_READ_PARAM_32_eg killed %t2_x, 24 147 // %t2_x = MOV %zero 148 //Adding this constraint prevents this from happening. 149 let Constraints = "$src_gpr.ptr = $dst_gpr"; 150} 151 152def VTX_READ_64_cm 153 : VTX_READ_cm <"VTX_READ_64 $dst_gpr.XY, $src_gpr", 154 (outs R600_Reg64:$dst_gpr)> { 155 156 let DST_SEL_X = 0; 157 let DST_SEL_Y = 1; 158 let DST_SEL_Z = 7; 159 let DST_SEL_W = 7; 160 let DATA_FORMAT = 0x1D; // COLOR_32_32 161} 162 163def VTX_READ_128_cm 164 : VTX_READ_cm <"VTX_READ_128 $dst_gpr.XYZW, $src_gpr", 165 (outs R600_Reg128:$dst_gpr)> { 166 167 let DST_SEL_X = 0; 168 let DST_SEL_Y = 1; 169 let DST_SEL_Z = 2; 170 let DST_SEL_W = 3; 171 let DATA_FORMAT = 0x22; // COLOR_32_32_32_32 172 173 // XXX: Need to force VTX_READ_128 instructions to write to the same register 174 // that holds its buffer address to avoid potential hangs. We can't use 175 // the same constraint as VTX_READ_32_eg, because the $src_gpr.ptr and $dst 176 // registers are different sizes. 177} 178 179//===----------------------------------------------------------------------===// 180// VTX Read from parameter memory space 181//===----------------------------------------------------------------------===// 182def : R600Pat<(i32:$dst_gpr (vtx_id3_az_extloadi8 ADDRVTX_READ:$src_gpr)), 183 (VTX_READ_8_cm MEMxi:$src_gpr, 3)>; 184def : R600Pat<(i32:$dst_gpr (vtx_id3_az_extloadi16 ADDRVTX_READ:$src_gpr)), 185 (VTX_READ_16_cm MEMxi:$src_gpr, 3)>; 186def : R600Pat<(i32:$dst_gpr (vtx_id3_load ADDRVTX_READ:$src_gpr)), 187 (VTX_READ_32_cm MEMxi:$src_gpr, 3)>; 188def : R600Pat<(v2i32:$dst_gpr (vtx_id3_load ADDRVTX_READ:$src_gpr)), 189 (VTX_READ_64_cm MEMxi:$src_gpr, 3)>; 190def : R600Pat<(v4i32:$dst_gpr (vtx_id3_load ADDRVTX_READ:$src_gpr)), 191 (VTX_READ_128_cm MEMxi:$src_gpr, 3)>; 192 193//===----------------------------------------------------------------------===// 194// VTX Read from constant memory space 195//===----------------------------------------------------------------------===// 196def : R600Pat<(i32:$dst_gpr (vtx_id2_az_extloadi8 ADDRVTX_READ:$src_gpr)), 197 (VTX_READ_8_cm MEMxi:$src_gpr, 2)>; 198def : R600Pat<(i32:$dst_gpr (vtx_id2_az_extloadi16 ADDRVTX_READ:$src_gpr)), 199 (VTX_READ_16_cm MEMxi:$src_gpr, 2)>; 200def : R600Pat<(i32:$dst_gpr (vtx_id2_load ADDRVTX_READ:$src_gpr)), 201 (VTX_READ_32_cm MEMxi:$src_gpr, 2)>; 202def : R600Pat<(v2i32:$dst_gpr (vtx_id2_load ADDRVTX_READ:$src_gpr)), 203 (VTX_READ_64_cm MEMxi:$src_gpr, 2)>; 204def : R600Pat<(v4i32:$dst_gpr (vtx_id2_load ADDRVTX_READ:$src_gpr)), 205 (VTX_READ_128_cm MEMxi:$src_gpr, 2)>; 206 207//===----------------------------------------------------------------------===// 208// VTX Read from global memory space 209//===----------------------------------------------------------------------===// 210def : R600Pat<(i32:$dst_gpr (vtx_id1_az_extloadi8 ADDRVTX_READ:$src_gpr)), 211 (VTX_READ_8_cm MEMxi:$src_gpr, 1)>; 212def : R600Pat<(i32:$dst_gpr (vtx_id1_az_extloadi16 ADDRVTX_READ:$src_gpr)), 213 (VTX_READ_16_cm MEMxi:$src_gpr, 1)>; 214def : R600Pat<(i32:$dst_gpr (vtx_id1_load ADDRVTX_READ:$src_gpr)), 215 (VTX_READ_32_cm MEMxi:$src_gpr, 1)>; 216def : R600Pat<(v2i32:$dst_gpr (vtx_id1_load ADDRVTX_READ:$src_gpr)), 217 (VTX_READ_64_cm MEMxi:$src_gpr, 1)>; 218def : R600Pat<(v4i32:$dst_gpr (vtx_id1_load ADDRVTX_READ:$src_gpr)), 219 (VTX_READ_128_cm MEMxi:$src_gpr, 1)>; 220 221} // End let SubtargetPredicate = isCayman 222